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features ? high performance, low power avr ? 32 uc 32-bit microcontroller ? compact single-cycle risc instruction set including dsp instructions ? read-modify-write instructions and atomic bit manipulation ? performance ? up to 64 dmips running at 50mhz from flash (1 flash wait state) ? up to 36 dmips running at 25mhz from flash (0 flash wait state) ? memory protection unit ? picopower ? technology for ultra-low power consumption ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 12 peripheral dma channels improve speed for peripheral communication ? internal high-speed flash ? 64kbytes, 32kbytes, and 16kbytes versions ? single-cycle access up to 25mhz ?flashvault ? technology allows pre-programmed secure library support for end user applications ? prefetch buffer optimizing instru ction execution at maximum speed ? 4ms page programming time and 8ms full-chip erase time ? 100,000 write cycles, 15-year data retention capability ? flash security locks and us er defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ? 16kbytes (64kbytes and 32kbytes fl ash), or 8kbytes (16kbytes flash) ? interrupt controller (intc) ? autovectored low latency interrupt service with programmable priority ? external interrupt controller (eic) ? peripheral event system for direct pe ripheral to periph eral communication ? system functions ? power and clock manager ? sleepwalking ? power saving control ? internal system rc oscillator (rcsys) ? 32 khz oscillator ? multipurpose oscillator and digi tal frequency locked loop (dfll) ? windowed watchdog timer (wdt) ? asynchronous timer (ast) with real-tim e clock capability ? counter or calendar mode supported ? frequency meter (freqm) for accurate measuring of clock frequency ? six 16-bit timer/co unter (tc) channels ? external clock inputs, pwm, capture and various counting capabilities ? pwm channels on all i/o pins (pwma) ? 8-bit pwm up to 15 0mhz source clock ? four universal synchronous/asynchro nous receiver/transmitters (usart) ? independent baudrate generator, support for spi ? support for hardware handshaking ? one master/slave serial peripheral inte rfaces (spi) with ch ip select signals ? up to 15 spi slaves can be addressed ? two master and two slave two-wire interfaces (twi), 400kbit/s i 2 c-compatible ? one 9-channel analog-to-digi tal converter (adc) with up to 12 bits resolution ? internal temperature sensor 32099a?avr32?06/09 avr ? 32 32-bit microcontroller at32uc3l064 at32uc3l032 at32uc3l016 preliminary
2 32099a?avr32?06/09 at32uc3l ? eight analog comparators (ac) with optional window detection ? capacitive touch (cat) module ? support qtouch ? and qmatrix ? capture from capacitive touch sensors ? on-chip non-intrusive debug system ? nexus class 2+, runtime control, non-intrusive data and program trace ?awire ? single-pin programming trace and debug interface muxed with reset pin ? nanotrace ? provides trace capabilities through jtag or awire interface ? 48-pin tqfp/qfn/tllga (36 gpio pins) ? five high-drive i/o pins ? single 1.62-3.6v power supply
3 32099a?avr32?06/09 at32uc3l 1. description the at32uc3l is a complete system-on-chip microcontroller based on the avr32 uc risc processor running at frequencies up to 50mhz. avr32 uc is a high-performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density, and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting modern operating systems and re al-time operating systems. higher computation capability is achieved using a rich set of dsp instructions. the at32uc3l embeds state-of-the-art picopower technology for ultra-low power consumption. combined power control techniques are used to bring active power as low as 0.5mw/mhz, and leakage down to 100na while still retaining a bank of backup regist ers. the device allows a wide range of trade-offs between functionalit y and power consumpt ion, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. the peripheral direct memory access (dma) controller enables data transfers between periph- erals and memories without processor involvement. the peripheral dma controller drastically reduces processing overhead when transferring continuous and large data streams. the at32uc3l incorporates on-chip flash and sram memories for secure and fast access. the flashvault technology allows secure libraries to be programmed into the device. the secure libraries can be executed while the cpu is in secure state, but not read by non-secure software in the device. the device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secu re libraries, but withou t risk of compromising the proprietary secure code. the peripheral event system allows peripherals to receive, react to, and send peripheral events without cpu intervention. asynchronous interrupts allow advanced peripheral operation in low power sleep modes. the power manager improves design flexibility and security. the power manager supports sleepwalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. power monitoring is supported by on-chip power-on reset (por), brown-out detector (bod), and supply monitor (sm). the device features several oscillators, such as dig ital frequency locked l oop (dfll), oscillator 0 (osc0), and system rc oscillator (rcsys). either of these oscillators can be used as source for the system clock. th e dfll is a programmable internal os cillator from 20 to 150mhz. it can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32khz crystal oscillator. the watchdog timer (wdt) will reset the device unless it is periodically serviced by the soft- ware. this allows the device to recover from a condition that has caused the system to be unstable. the asynchronous timer (ast) combined with th e 32khz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeou t of up to 136 years. the ast can operate in counter mode or calendar mode. the frequency meter (freqm) allows accurate measuring of a clock frequency by comparing it to a known reference clock. the device includes six identical 16-bit timer/counter (tc) channels. each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation.
4 32099a?avr32?06/09 at32uc3l the pulse width modulation controller (pwma) provides 8-bit pwm channels which can be syn- chronized and controlled from a common timer. one pwm channel is available for each i/o pin on the device, enabling applications that require multiple pwm outputs, such as lcd backlight control. the pwm channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. the at32uc3l also features many communication interfaces for communication intensive applications like usart, spi, or twi. a general purpose 9-channel adc is provided, as well as eight analog comparators (ac). the adc can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. the adc also provides an internal temperature sensor input channel. the analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. the capacitive touch (cat) module senses touch on external capacitive touch sensors, using the qtouch technology. capacitive touch sensor s use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. the cat module allows up to 17 touch sensors, or up to 18 by 8 matrix sensors to be interfaced. one touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. the at32uc3l integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intru- sive real-time trace, full-speed read/write memory access, in addition to basic runtime control. the nanotrace interface enables trace feature for awire- or jtag-based debuggers. the sin- gle-pin awire interface allows all features av ailable through the jtag interface to be accessed through the reset pin, allowing the jtag pins to be used for gpio or peripherals.
5 32099a?avr32?06/09 at32uc3l 2. overview 2.1 block diagram figure 2-1. block diagram system control interface interrupt controller asynchronous timer peripheral dma controller hsb-pb bridge b hsb-pb bridge a s mm m s s m external interrupt controller high speed bus matrix generalpurpose i/os general purpose i/os pa pb extint[5..1] nmi g c l k [ 4 . . 0 ] pa pb spi dma miso, mosi npcs[3..0] usart0 usart1 usart2 usart3 dma rxd txd clk rts, cts watchdog timer sck jtag interface mcko mdo[5..0] mseo[1..0] evti_n tdo tdi tms configuration registers bus 64 kb flash s flash controller evto_n uc cpu nexus class 2+ ocd instr interface data interface memory interface local bus 16 kb sram memory protection unit local bus interface frequency meter pwm controller pwm[35..0] timer/counter 0 timer/counter 1 a[2..0] b [ 2 . . 0 ] clk[2..0] twi master 0 twi master 1 dma twi slave 0 twi slave 1 dma 9-channel adc interface dma ad[8..0] advref power manager reset controller sleep controller clock controller xin32 xout32 osc32k rcsys xin0 xout0 osc0 dfll bod tck awire reset_n capacitive touch module dma csb[16:0] smp csa[16:0] sync ac interface acrefn acan[3..0] acbn[3..0] acbp[3..0] acap[3..0] twck twd twalm twck twd twalm rc32k rc120m glue logic controller in[7..0] out[1:0]
6 32099a?avr32?06/09 at32uc3l 2.2 configuration summary table 2-1. configuration summary feature at32uc3l0 at32uc3l1 at32uc3l2 flash 64kb 32kb 16kb sram 16kb 16kb 8kb gpio 36 hi-drive pins 5 external interrupts 8 twi 2 usart 4 peripheral dma channels 12 peripheral event system 1 spi 1 asynchronous timers 1 timer/counter channels 6 pwm channels 36 frequency meter 1 watchdog timer 1 power manager 1 oscillators digital frequency locked loop 20-150 mhz (dfll) crystal oscillator 3-16 mhz (osc0) crystal oscillator 32 khz (osc32k) rc oscillator 120mhz (rc120m) rc oscillator 115 khz (rcsys) rc oscillator 32 khz (rc32k) adc 9 channel 10-bit temperature sensor 1 analog comparators 8 capacitive touch module 1 jtag 1 awire 1 max frequency 50 mhz package tqfp48/qfn48/tllga48
7 32099a?avr32?06/09 at32uc3l 3. package and pinout 3.1 package the device pins are multiplexed with pe ripheral functions as described in section 3.2 . figure 3-1. tqfp48/qfn48/tllga48 pinout 3.2 peripheral multiplexing on i/o lines 3.2.1 multiplexed signals each gpio line can be assigned to one of the peripheral functions.the following table describes the peripheral signals multiplexed to the gpio lines. gnd 1 pa09 2 pa08 3 pa03 4 pb12 5 pb00 6 pb02 7 pb03 8 pa22 9 pa06 10 pa00 11 pa05 12 pa02 13 pa01 14 pa07 15 pb01 16 vddin 17 vddcore 18 gnd 19 pb05 20 pb04 21 reset_n 22 pb10 23 pa21 24 pa14 36 vddana 35 advrefp 34 gndana 33 pb08 32 pb07 31 pb06 30 pb09 29 pa04 28 pa11 27 pa13 26 pa20 25 pa15 37 pa16 38 pa17 39 pa19 40 pa18 41 vddio 42 gnd 43 pb11 44 gnd 45 pa10 46 pa12 47 vddio 48
8 32099a?avr32?06/09 at32uc3l table 3-1. gpio controller func tion multiplexing q f p 48 pin g pi o supply pad type gpio function abcde f gh 11 pa00 0 vddio normal i/o usart0- txd usart1- rts spi- npcs[2] pwma- pwma[0] scif- gclk[0] cat-csa[2] 14 pa01 1 vddio normal i/o usart0- rxd usart1- cts spi- npcs[3] usart1- clk pwma- pwma[1] acifb- acap[0] twims0- twalm cat-csa[1] 13 pa02 2 vddio high- drive i/o usart0- rts adcifb- trigger usart2- txd tc0-a0 pwma- pwma[2] acifb- acbp[0] usart0- clk cat-csa[3] 4 pa03 3 vddio normal i/o usart0- cts spi- npcs[1] usart2- txd tc0-b0 pwma- pwma[3] acifb- acbn[3] usart0- clk cat-csb[3] 28 pa04 4 vddio normal i/o spi-miso twims0- twck usart1- rxd tc0-b1 pwma- pwma[4] acifb- acbp[1] cat-csa[7] 12 pa05 5 vddio twi, normal i/o spi-mosi twims1- twck usart1- txd tc0-a1 pwma- pwma[5] acifb- acbn[0] twims0- twd cat-csb[7] 10 pa06 6 vddio high- drive i/o, 5v tolerant spi-sck usart2- txd usart1- clk tc0-b0 pwma- pwma[6] scif- gclk[1] cat-csb[1] 15 pa07 7 vddio twi, normal i/o spi- npcs[0] usart2- rxd twims1- twalm twims0- twck pwma- pwma[7] acifb- acan[0] eic- extint[0] cat-csb[2] 3 pa08 8 vddio high- drive i/o usart1- txd spi- npcs[2] tc0-a2 adcifb- adp[0] pwma- pwma[8] cat-csa[4] 2 pa09 9 vddio high- drive i/o usart1- rxd spi- npcs[3] tc0-b2 adcifb- adp[1] pwma- pwma[9] scif-gclk[2] eic- extint[1] cat-csb[4] 46 pa10 10 vddio normal i/o twims0- twd tc0-a0 pwma- pwma[10] acifb- acap[1] scif- gclk[2] cat-csa[5] 27 pa11 11 vddin normal i/o pwma- pwma[11] 47 pa12 12 vddio normal i/o adcifb- prnd usart2- clk tc0-clk1 cat-smp pwma- pwma[12] acifb- acan[1] scif- gclk[3] cat-csb[5] 26 pa13 13 vddin normal i/o gloc- out[0] gloc-in[7] tc0-a0 scif- gclk[2] pwma- pwma[13] cat-smp eic- extint[2] cat-csa[0] 36 pa14 14 vddio normal i/o adcifb- ad[0] tc0-clk2 usart2- rts cat-smp pwma- pwma[14] scif- gclk[4] cat-csa[6] 37 pa15 15 vddio normal i/o adcifb- ad[1] tc0-clk1 gloc-in[6] pwma- pwma[15] cat-sync eic- extint[3] cat-csb[6] 38 pa16 16 vddio normal i/o adcifb- ad[2] tc0-clk0 gloc-in[5] pwma- pwma[16] acifb- acrefn eic- extint[4] cat-csa[8] 39 pa17 17 vddio twi, normal i/o adcifb- ad[3] tc0-a1 usart2- cts twims1- twd pwma- pwma[17] cat-smp cat-dis cat-csb[8] 41 pa18 18 vddio normal i/o adcifb- ad[4] tc0-b1 gloc-in[4] pwma- pwma[18] cat-sync eic- extint[5] cat-csb[0] 40 pa19 19 vddio normal i/o adcifb- ad[5] tc0-a2 twims1- twalm pwma- pwma[19] cat-sync cat- csa[10] 25 pa20 20 vddin normal i/o usart2- txd twims0- twck tc0-a1 gloc-in[3] pwma- pwma[20] scif- rc32out cat- csa[12]
9 32099a?avr32?06/09 at32uc3l see section 3.3 for a description of the various peripheral signals. signals are prioritized according to the function priority listed in table 3-2 on page 10 if multiple functions are enabled simultaneously. refer to ?electrical characteristics? on page 786 for a description of the electrical properties of the pad types used. 24 pa21 21 vddin twi, 5v tolerant, smbus, normal i/o usart2- rxd twims0- twd tc0-b1 adcifb- trigger pwma- pwma[21] pwma- pwmaod[21] scif- gclk[0] cat-smp 9 pa22 22 vddio normal i/o usart0- cts usart2- clk tc0-b2 cat-smp pwma- pwma[22] acifb- acbn[2] cat- csb[10] 6 pb00 32 vddio normal i/o usart3- txd adcifb- adp[0] spi- npcs[0] tc0-a1 pwma- pwma[23] acifb- acap[2] tc1-a0 cat-csa[9] 16 pb01 33 vddio high- drive i/o usart3- rxd adcifb- adp[1] spi-sck tc0-b1 pwma- pwma[24] tc1-a1 cat-csb[9] 7 pb02 34 vddio normal i/o usart3- rts usart3- clk spi-miso tc0-a2 pwma- pwma[25] acifb- acan[2] scif- gclk[1] cat- csb[11] 8 pb03 35 vddio normal i/o usart3- cts usart3- clk spi-mosi tc0-b2 pwma- pwma[26] acifb- acbp[2] tc1-a2 cat- csa[11] 21 pb04 36 vddin twi, 5v tolerant, smbus, normal i/o tc1-a0 usart1- rts usart1- clk twims0- twalm pwma- pwma[27] pwma- pwmaod[27] twims1- twck cat- csa[14] 20 pb05 37 vddin twi, 5v tolerant, smbus, normal i/o tc1-b0 usart1- cts usart1- clk twims0- twck pwma- pwma[28] pwma- pwmaod[28] scif- gclk[3] cat- csb[14] 30 pb06 38 vddio normal i/o tc1-a1 usart3- txd adcifb- ad[6] gloc-in[2] pwma- pwma[29] acifb- acan[3] eic- extint[0] cat- csb[13] 31 pb07 39 vddio normal i/o tc1-b1 usart3- rxd adcifb- ad[7] gloc-in[1] pwma- pwma[30] acifb- acap[3] eic- extint[1] cat- csa[13] 32 pb08 40 vddio normal i/o tc1-a2 usart3- rts adcifb- ad[8] gloc-in[0] pwma- pwma[31] cat-sync eic- extint[2] cat- csb[12] 29 pb09 41 vddio normal i/o tc1-b2 usart3- cts usart3- clk pwma- pwma[32] acifb- acbn[1] eic- extint[3] cat- csb[15] 23 pb10 42 vddin normal i/o tc1-clk0 usart1- txd usart3- clk gloc- out[1] pwma- pwma[33] eic- extint[4] cat- csb[16] 44 pb11 43 vddio normal i/o tc1-clk1 usart1- rxd adcifb- trigger pwma- pwma[34] cat-vdiven eic- extint[5] cat- csa[16] 5 pb12 44 vddio normal i/o tc1-clk2 twims1- twalm cat-sync pwma- pwma[35] acifb- acbp[3] scif- gclk[4] cat- csa[15] table 3-1. gpio controller func tion multiplexing
10 32099a?avr32?06/09 at32uc3l 3.2.2 peripheral functions each gpio line can be assigned to one of several peripheral functions. the following table describes how the various peripheral functions are selected. the last listed function has priority in case multiple functions are enabled. 3.2.3 jtag port connections if the jtag is enabled, the jtag will take control over a number of pins, irre spective of the i/o controller configuration. 3.2.4 nexus ocd aux port connections if the ocd trace system is enabled, the trace s ystem will take control ov er a number of pins, respectively of the i/o controller configuration. two different ocd trace pin mappings are possi- ble, depending on the configuration of the ocd axs register. for details, see the avr32 uc technical reference manual . table 3-2. peripheral functions function description a gpio peripheral selection a b gpio peripheral selection b c gpio peripheral selection c d gpio peripheral selection d e gpio peripheral selection e f gpio peripheral selection f g gpio peripheral selection g h gpio peripheral selection h table 3-3. jtag pinout 48tqfp/qfn pin pin name jtag pin 11 pa00 tck 14 pa01 tms 13 pa02 tdo 4pa03tdi table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 evti_n pa05 pb08 mdo[5] pa10 pb00 mdo[4] pa18 pb04 mdo[3] pa17 pb05 mdo[2] pa16 pb03 mdo[1] pa15 pb02 mdo[0] pa14 pb09 evto_n pa04 pa04
11 32099a?avr32?06/09 at32uc3l 3.2.5 oscillator pinout the oscillators are not mapped to the normal gp io functions and their muxings are controlled by registers in the system control interface (scif). please refer to the scif chapter for more information about this. 3.2.6 other functions the functions listed in table 3-6 are not mapped to the normal gpio functions.the awire data pin will only be active after the awire is e nabled. the awire dataout pin will only be actice after the awire is enabled and the full duple x command has been se nt. the wake_n pin is always enabled. please refer to section 3.5.4 on page 20 for constraints on the wake_n pin. mcko pa06 pb01 mseo[1] pa07 pb11 mseo[0] pa11 pb12 table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 table 3-5. oscillator pinout 48tqfp/qfn/tllga pin oscillator function 3pa08xin0 46 pa10 xin32 26 pa13 xin32_2 2pa09xout0 47 pa12 xout32 25 pa20 xout32_2 table 3-6. other functions 48tqfp/tqfn/tllga pin function 27 pa11 wake_n 22 reset_n awire data 11 pa00 awire dataout
12 32099a?avr32?06/09 at32uc3l 3.3 signal descriptions the following table gives details on signal name classified by peripheral. table 3-7. signal descriptions list signal name function type active level comments analog comparator interface - acifb acan3 - acan0 negative inputs for comparators "a" analog acap3 - acap0 positive inputs for comparators "a" analog acbn3 - acbn0 negative inputs for comparators "b" analog acbp3 - acbp0 positive inputs for comparators "b" analog acrefn common negative reference analog adc interface - adcifb ad8 - ad0 analog signal analog adp1 - adp0 drive pin for touch screen output prnd pseudorandom output signal output trigger external trigger input awire - aw data awire data i/o dataout awire data output for full duplex mode i/o capacitive touch module - cat csa16 - csa0 capacitive sense a i/o csb16 - csb0 capacitive sense b i/o smp smp signal output sync synchronize signal input vdiven voltage divider enable output external interrup t controller - eic nmi non-maskable interrupt input extint5 - extint1 exte rnal interrupt input glue logic controller - gloc in7 - in0 inputs to lookup tables input out1 - out0 outputs from lookup tables output jtag module - jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input
13 32099a?avr32?06/09 at32uc3l power manager - pm reset_n reset input low basic pulse width modulation controller - pwma pwma35 - pwma0 pwma channel waveforms output pwmaod35 - pwmaod0 pwma channel waveforms, open drain mode output not all channels support open drain mode system control interface - scif gclk4 - gclk0 generic clock output output rc32out rc32k output at startup output xin0 crystal 0 input analog/ digital xin32 crystal 32 inpu t (primary location) analog/ digital xin32_2 crystal 32 input (secondary location) analog/ digital xout0 crystal 0 output analog xout32 crystal 32 output (primary location) analog xout32_2 crystal 32 output (secondary location) analog serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o npcs3 - npcs0 spi peripheral chip select i/o low sck clock i/o timer/counter - tc0, tc1 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twims0, twims1 twalm smbus smbalert i/o low twck two-wire serial clock i/o twd two-wire serial data i/o universal synchronous/asynchronous receiver/transmitter - usart0, usart1, usart2, usart3 table 3-7. signal descriptions list
14 32099a?avr32?06/09 at32uc3l clk clock i/o cts clear to send input low rts request to send output low rxd receive data input txd transmit data output table 3-7. signal descriptions list table 3-8. signal description list, continued signal name function type active level comments power vddcore core power supply / voltage regulator output power input/output 1.62 v to 1.98 v vddio i/o power supply power input 1.62 v to 3.6 v. vddio should always be equal to or lower than vddin. vddana analog power supply power input 1.62 v to 1.98 v advrefp analog reference voltage power input tbd to 1.98 v vddin voltage regulator input power input 1.62 v to 3.6v (1) gndana analog ground ground gnd ground ground auxiliary port - aux mcko trace data output clock output mdo5 - mdo0 trace data output output mseo1 - mseo0 trace frame control output evti_n event in input low evto_n event out output low general purpose i/o pin - gpioa, gpiob pa22 - pa0 parallel i/o controller gpioa i/o pb12 - pb0 parallel i/o controller gpiob i/o 1. see section 3.5
15 32099a?avr32?06/09 at32uc3l 3.4 i/o line considerations 3.4.1 jtag pins the jtag is enabled if tck is low while the reset_n pin is re leased. the tck, tms, and tdi pins have pull-up resistors when jtag is enabled. tdo pin is an output, driven at vddio, and has no pull-up resistor. these jtag pins can be used as gpio pins and muxed with peripherals when the jtag is disabled. 3.4.2 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddio. as the product integrates a power-on reset detector, the reset_n pin can be left unconnected in case no reset from the system nee ds to be applied to the product. the reset_n pin is also used for the awire de bug protocol. when the pin is used for debug- ging, it must not be driven by the application. 3.4.3 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. when used as gpio pins or used for other peripherals, the pins have the same charac teristics as gpio pins. 3.4.4 gpio pins all the i/o lines integrate a pull-up resistor . programming of this pull-up resistor is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up resistors disabled, except pa00. 3.4.5 adc input pins these pins are regular i/o pins powered from the vddio. however, when these pins are used for adc inputs, the voltage applied to the pin must not exceed 1.98v. internal circuitry ensures that the pin cannot be used as an analog input pin when the i/o drives to vdd. when the pins are not used for adc inputs, the pins may be driven to the full i/o voltage range. 3.5 power considerations 3.5.1 power supplies the at32uc3l has several types of power supply pins: ? vddio: powers i/o lines. voltage is 1.8 to 3.3v nominal. ? vddin: powers i/o lines and the internal regulator. voltage is 1.8 to 3.3v nominal. ? vddana: powers the adc. voltage is 1.8v nominal. ? vddcore: powers the core, memories, and peripherals. voltage is 1.8v nominal. the ground pins gnd are comm on to vddcore and vddio. th e ground pin for vddana is gndana. refer to ?electrical characteristics? on page 786 for power consumption on the various supply pins.
16 32099a?avr32?06/09 at32uc3l 3.5.2 voltage regulator the at32uc3l embeds a voltage regulator that converts from 3.3v nominal to 1.8v with a load of up to 60 ma. the regulator supplies the output voltage on vddcore. vddcore should be externally connected to the 1.8v domains. see section 3.5.3 for regulator connection figures. adequate output supply decoupling is mandat ory for vddcore to reduce ripple and avoid oscillations. the best way to achieve this is to use two capacitors in parallell between vddcore and gnd as close to the chip as possible. please refer to section 32.9.1 for decou- pling capacitors values and regulator characteristics. figure 3-2. supply decoupling 3.5.3 regulator connection the at32uc3l supports three power supply configurations: ?3.3v single supply mode ?1.8v single supply mode ?3.3v supply mode, with 1.8v regulated i/o lines 3.5.3.1 3.3v single supply mode in 3.3v single supply mode the internal regulator is connected to the 3.3v source (vddin pin) and its output feeds vddcore. figure 3-3 shows the power schematics to be used for 3.3v sin- gle supply mode. all i/o lines will be powered by the same power (vddin=vddio). 3.3v 1.8v vddin vddcore 1.8v regulator c in1 c out1 c out2 c in2
17 32099a?avr32?06/09 at32uc3l figure 3-3. 3.3v single power supply mode vddio vddcore cpu, peripherals, memories, scif, bod, rcsys, dfll linear + - tbd-3.6v osc32k rc32k ast wake por33 sm33 vddana adc vddin gnd gndana i/o pins i/o pins
18 32099a?avr32?06/09 at32uc3l 3.5.3.2 1.8v single supply mode in 1.8v single supply mode the internal regul ator is not used, and vddio and vddcore are powered by a single 1.8v supply as shown in figure 3-4 . all i/o lines will be powered by the same power (vddin = vddio = vddcore). figure 3-4. 1.8v single power supply mode. vddio vddcore linear + - 1.62-1.98v vddana adc vddin gnd gndana cpu, peripherals, memories, scif, bod, rcsys, dfll osc32k rc32k ast wake por33 sm33 i/o pins i/o pins
19 32099a?avr32?06/09 at32uc3l 3.5.3.3 3.3v supply mode with 1.8v regulated i/o lines in this mode, the internal regulator is connecte d to the 3.3v source and its output is connected to both vddcore and vddio as shown in figure 3-5 . this configuration is required in order to use shutdown mode. figure 3-5. 3.3v power with 1.8v regulated i/o lines in this mode, some i/o lines are powered by vddin while others i/o lines are powered by vddio. refer to table 1-1 on page 8 for description of power supply for each i/o line. important note: as the regulator has a maximum output current of 60ma, this mode can only be used in applications where the maximum i/o current is known and compatible with the core and peripheral power consumption. typically, great care must be used to ensure that only a few i/o lines are toggling at the same time and drive very small loads. vddio vddcore linear + - tbd-3.6v vddana adc vddin gnd gndana cpu, peripherals, memories, scif, bod, rcsys, dfll osc32k rc32k ast wake por33 sm33 i/o pins i/o pins
20 32099a?avr32?06/09 at32uc3l 3.5.4 power-up sequence 3.5.4.1 maximum rise rate to avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in table 32-3 on page 787 . recommended order for power supplies is also described in this table. 3.5.4.2 minimum rise rate the integrated power-reset circuitry monitoring the vddin powering supply requires a mini- mum rise rate for the vddin power supply. see table 32-3 on page 787 for the minimum rise rate value. if the application can not ensure that the minimum rise rate condition for the vddin power sup- ply is met, one of the following configuration can be used: ?a logic ?0? value is applied during power-up on pin pa11 until vddin rises above 1.2v. ?a logic ?0? value is applied during power- up on pin reset_n until vddin rises above 1.2v.
21 32099a?avr32?06/09 at32uc3l 4. processor and architecture rev: 2.1.0.0 this chapter gives an overview of the avr32uc cpu. avr32uc is an implementation of the avr32 architecture. a summary of the programming model, instruction set, and mpu is pre- sented. for further details, see the avr32 architecture manual and the avr32uc technical reference manual . 4.1 features ? 32-bit load/store avr32a risc architecture ? 15 general-purpose 32-bit registers ? 32-bit stack pointer, program counter and link register reside in register file ? fully orthogonal instruction set ? privileged and unprivileged modes enabling efficient and secure operating systems ? innovative instruction set together with variable instruction length ensu ring industry leading code density ? dsp extention with saturating arithmetic, and a wide vari ety of multiply instructions ? 3-stage pipeline allowing one instruction per clock cy cle for most instructions ? byte, halfword, word, and double word memory access ? multiple interrupt priority levels ? mpu allows for operating s ystems with memory protection ? secure state for supporting flashvault tm technology 4.2 avr32 architecture avr32 is a new, high-performance 32-bit risc mi croprocessor architectu re, designed for cost- sensitive embedded applications, with particul ar emphasis on low power consumption and high code density. in addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the avr32 to be implemented as low-, mid-, or high-performance processors. avr32 extends the avr family into the world of 32- and 64-bit applications. through a quantitative approach, a large set of industry recognized benchmarks has been com- piled and analyzed to achieve the best code density in its class. in addition to lowering the memory requirements, a compact code size also contributes to the core?s low power characteris- tics. the processor supports byte and halfword data types without penalty in code size and performance. memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfw ord and byte data. the c-compiler is closely linked to the architecture and is able to expl oit code optimization features, both for size and speed. in order to reduce code size to a minimum, so me instructions have multiple addressing modes. as an example, instructions with immediates often have a compact format with a smaller imme- diate, and an extended format with a larger immediate. in this way, the compiler is able to use the format giving the smallest code size. another feature of the instruction set is that frequently used instructions, like add, have a com- pact format with two operands as well as an extended format with three operands. the larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. load and store instructions have seve ral different formats in order to reduce code size and speed up execution.
22 32099a?avr32?06/09 at32uc3l the register file is organized as sixteen 32-bi t registers and includes the program counter, the link register, and the stack pointer. in addition, register r12 is designed to hold return values from function calls and is used im plicitly by some instructions. 4.3 the avr32uc cpu the avr32uc cpu targets low- and mediu m-performance applications, and provides an advanced on-chip debug (ocd) system, no ca ches, and a memory protection unit (mpu). java acceleration hardware is not implemented. avr32uc provides three memory interfaces, one high speed bus master for instruction fetch, one high speed bus master for data access, an d one high speed bus slave interface allowing other bus masters to access data rams internal to the cpu. keeping data rams internal to the cpu allows fast access to the rams, reduces latency, and guarantees deterministic timing. also, power consumption is reduced by not needing a full high speed bus access for memory accesses. a dedicated data ram interface is prov ided for communicating with the internal data rams. a local bus interface is provided for connecting the cpu to device-specific high-speed systems, such as floating-point units and i/o controller port s. this local bus has to be enabled by writing a one to the locen bit in the cpucr system regi ster. the local bus is able to transfer data between the cpu and the local bus slave in a single clock cycle. the local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. details on which devices that are mapped into the local bus space is given in the cpu local bus section in the memories chapter. figure 4-1 on page 23 displays the contents of avr32uc.
23 32099a?avr32?06/09 at32uc3l figure 4-1. overview of the avr32uc cpu 4.3.1 pipeline overview avr32uc has three pipeline stages, instruction fetch (if), instruction decode (id), and instruc- tion execute (ex). the ex stage is split into three parallel subsections, one arithmetic/logic (alu) section, one multiply (mul) sect ion, and one load/store (ls) section. instructions are issued and complete in order. certain operations require several clock cycles to complete, and in this case, the instruction resides in the id and ex stages for the required num- ber of clock cycles. since there is only three pipeline stages, no inte rnal data forwarding is required, and no data dependencies can arise in the pipeline. figure 4-2 on page 24 shows an overview of the avr32uc pipeline stages. avr32uc cpu pipeline instruction memory controller high speed bus master mpu high speed bus high speed bus ocd system ocd interface interrupt controller interface high speed bus slave high speed bus high speed bus master power/ reset control reset interface cpu local bus master cpu local bus data memory controller cpu ram
24 32099a?avr32?06/09 at32uc3l figure 4-2. the avr32uc pipeline 4.3.2 avr32a microarchitecture compliance avr32uc implements an avr32a microarchitecture. the avr32a microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. this microarchitecture does not provide dedicated hard ware registers for shadowing of register file registers in interrupt contexts. additionally, it does not provide hardware registers for the return address registers and return status registers. instead, all this information is stored on the system stack. this saves chip area at the expense of slower interrupt handling. 4.3.2.1 interrupt handling upon interrupt initiation, registers r8-r12 are automatically pushed to the system stack. these registers are pushed regardless of the priority level of the pending interrupt. the return address and status register are also automatically pushed to stack. the interrupt handler can therefore use r8-r12 freely. upon interrupt completion, the old r8-r12 registers and status register are restored, and execution continues at the return address stored popped from stack. the stack is also used to store the status register and return address for exceptions and scall . executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.2 java support avr32uc does not provide java hardware acceleration. 4.3.2.3 memory protection the mpu allows the user to check all memory accesses for privilege violations. if an access is attempted to an illegal memory address, the access is aborted and an exception is taken. the mpu in avr32uc is specified in t he avr32uc technical reference manual. 4.3.2.4 unaligned reference handling avr32uc does not support unaligned accesses, except for doubleword accesses. avr32uc is able to perform word-aligned st.d and ld.d . any other unaligned memory access will cause an address exception. doubleword -sized accesses with word-align ed pointers will automatically be performed as two word-sized accesses. if id alu mul regfile write prefetch unit decode unit alu unit multiply unit load-store unit ls regfile read
25 32099a?avr32?06/09 at32uc3l the following table shows the instructions with support for unaligned addresses. all other instructions requir e aligned addresses. 4.3.2.5 unimplemented instructions the following instructions are unimplemented in avr32uc, and will cause an unimplemented instruction exception if executed: ? all simd instructions ? all coprocessor instructions if no coprocessors are present ? retj, incjosp, popjc, pushjc ? tlbr, tlbs, tlbw ? cache 4.3.2.6 cpu and architecture revision three major revisions of the avr32uc cpu currently exist. the device described in this datasheet uses cpu revision 3. the architecture revision field in the config0 system register identifies which architecture revision is implemented in a specific device. avr32uc cpu revision 3 is fully backward-compatibl e with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 cpus. table 4-1. instructions with una ligned reference support instruction supported alignment ld.d word st.d word
26 32099a?avr32?06/09 at32uc3l 4.4 programming model 4.4.1 register file configuration the avr32uc register file is shown below. figure 4-3. the avr32uc register file 4.4.2 status register configuration the status register (sr) is split into two halfwords, one upper and one lower, see figure 4-4 and figure 4-5 . the lower word contains the c, z, n, v, and q condition code flags and the r, t, and l bits, while the upper halfword contains information about the mode and state the proces- sor executes in. refer to the avr32 architecture manual for details. figure 4-4. the status register high halfword application bit 0 supervisor bit 31 pc sr int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 int0 sp_app sp_sys r12 r11 r9 r10 r8 exception nmi int1 int2 int3 lr lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sys lr secure bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 sp_sec lr ss_status ss_adrf ss_adrr ss_adr0 ss_adr1 ss_sp_sys ss_sp_app ss_rar ss_rsr bit 31 0 0 0 bit 16 interrupt level 0 mask interrupt level 1 mask interrupt level 3 mask interrupt level 2 mask 1 0 0 0 0 1 1 0 0 0 0 0 0 fe i0m gm m1 - d m0 em i2m dm - m2 lc 1 ss initial value bit name i1m mode bit 0 mode bit 1 - mode bit 2 reserved debug state - i3m reserved exception mask global interrupt mask debug state mask secure state
27 32099a?avr32?06/09 at32uc3l figure 4-5. the status register low halfword 4.4.3 processor states 4.4.3.1 normal risc state the avr32 processor supports several diff erent execution contexts as shown in table 4-2 . mode changes can be made under software control, or can be caused by external interrupts or exception processing. a mode can be interrupted by a higher priority mode, but never by one with lower priority. nested exceptions can be supported with a minimal software overhead. when running an operating system on the avr32, user processes will typically execute in the application mode. the programs executed in this mode are restricted from executing certain instructions. furthermore, most system registers together with the upper halfword of the status register cannot be accessed. protected memory areas are also not available. all other operating modes are privileged and are collectively called system modes. they have full access to all priv- ileged and unprivileged re sources. after a reset, the proc essor will be in su pervisor mode. 4.4.3.2 debug state the avr32 can be set in a debug state, which allows implementation of software monitor rou- tines that can read out and alter system information for use during application development. this implies that all system and application regist ers, including the status registers and program counters, are accessible in debug state. th e privileged instructions are also available. all interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. bit 15 bit 0 reserved carry zero sign 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - t - bit name initial value 0 0 l q v n z c - overflow saturation - - - lock reserved scratch table 4-2. overview of execution modes, thei r priorities and privilege levels. priority mode securi ty description 1 non maskable interrupt privileged non maskable high priority interrupt mode 2 exception privileged execute exceptions 3 interrupt 3 privileged general purpose interrupt mode 4 interrupt 2 privileged general purpose interrupt mode 5 interrupt 1 privileged general purpose interrupt mode 6 interrupt 0 privileged general purpose interrupt mode n/a supervisor privileged runs supervisor calls n/a application unprivileged normal program execution mode
28 32099a?avr32?06/09 at32uc3l debug state can be entered as described in the avr32uc technical reference manual . debug state is exited by the retd instruction. 4.4.3.3 secure state the avr32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. the rest of the code can not access resources reserved for this secure code. secure state is used to implemen t flashvault technology. refer to the avr32uc techni- cal reference manual for details. 4.4.4 system registers the system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. the table below lis ts the system registers speci- fied in the avr32 architecture, some of which are unused in avr32uc. the programmer is responsible for maintaining correct sequen cing of any instructions following a mtsr instruction. for detail on the system registers, refer to the avr32uc technical reference manual . table 4-3. system registers reg # address name function 0 0 sr status register 1 4 evba exception vector base address 2 8 acba application call base address 3 12 cpucr cpu control register 4 16 ecr exception cause register 5 20 rsr_sup unused in avr32uc 6 24 rsr_int0 unused in avr32uc 7 28 rsr_int1 unused in avr32uc 8 32 rsr_int2 unused in avr32uc 9 36 rsr_int3 unused in avr32uc 10 40 rsr_ex unused in avr32uc 11 44 rsr_nmi unused in avr32uc 12 48 rsr_dbg return status register for debug mode 13 52 rar_sup unused in avr32uc 14 56 rar_int0 unused in avr32uc 15 60 rar_int1 unused in avr32uc 16 64 rar_int2 unused in avr32uc 17 68 rar_int3 unused in avr32uc 18 72 rar_ex unused in avr32uc 19 76 rar_nmi unused in avr32uc 20 80 rar_dbg return address register for debug mode 21 84 jecr unused in avr32uc 22 88 josp unused in avr32uc 23 92 java_lv0 unused in avr32uc
29 32099a?avr32?06/09 at32uc3l 24 96 java_lv1 unused in avr32uc 25 100 java_lv2 unused in avr32uc 26 104 java_lv3 unused in avr32uc 27 108 java_lv4 unused in avr32uc 28 112 java_lv5 unused in avr32uc 29 116 java_lv6 unused in avr32uc 30 120 java_lv7 unused in avr32uc 31 124 jtba unused in avr32uc 32 128 jbcr unused in avr32uc 33-63 132-252 reserved reserved for future use 64 256 config0 configuration register 0 65 260 config1 configuration register 1 66 264 count cycle counter register 67 268 compare compare register 68 272 tlbehi unused in avr32uc 69 276 tlbelo unused in avr32uc 70 280 ptbr unused in avr32uc 71 284 tlbear unused in avr32uc 72 288 mmucr unused in avr32uc 73 292 tlbarlo unused in avr32uc 74 296 tlbarhi unused in avr32uc 75 300 pccnt unused in avr32uc 76 304 pcnt0 unused in avr32uc 77 308 pcnt1 unused in avr32uc 78 312 pccr unused in avr32uc 79 316 bear bus error address register 80 320 mpuar0 mpu address register region 0 81 324 mpuar1 mpu address register region 1 82 328 mpuar2 mpu address register region 2 83 332 mpuar3 mpu address register region 3 84 336 mpuar4 mpu address register region 4 85 340 mpuar5 mpu address register region 5 86 344 mpuar6 mpu address register region 6 87 348 mpuar7 mpu address register region 7 88 352 mpupsr0 mpu privilege select register region 0 89 356 mpupsr1 mpu privilege select register region 1 table 4-3. system registers (continued) reg # address name function
30 32099a?avr32?06/09 at32uc3l 4.5 exceptions and interrupts in the avr32 architecture, events are used as a common term for exceptions and interrupts. avr32uc incorporates a powerful event handling scheme. the different event sources, like ille- gal op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. when an event occurs, the execution of the instru ction stream is halted, and execution is passed to an event handler at an address specified in table 4-4 on page 34 . most of the handlers are placed sequentially in the code sp ace starting at the ad dress specified by evba, with four bytes between each handler. this gives ample space for a jump instruction to be placed there, jump- ing to the event routine itself. a few critical handlers have larg er spacing between them, allowing the entire event routine to be placed directly at the address specified by the evba-relative offset generated by hardware. all interrupt sources have autovectored interrupt service routine (isr) addresses. this allows the interrupt controller to directly specify the isr address as an address 90 360 mpupsr2 mpu privilege select register region 2 91 364 mpupsr3 mpu privilege select register region 3 92 368 mpupsr4 mpu privilege select register region 4 93 372 mpupsr5 mpu privilege select register region 5 94 376 mpupsr6 mpu privilege select register region 6 95 380 mpupsr7 mpu privilege select register region 7 96 384 mpucra unused in this version of avr32uc 97 388 mpucrb unused in this version of avr32uc 98 392 mpubra unused in this version of avr32uc 99 396 mpubrb unused in this version of avr32uc 100 400 mpuapra mpu access permission register a 101 404 mpuaprb mpu access permission register b 102 408 mpucr mpu control register 103 412 ss_status secure state status register 104 416 ss_adrf secure state address flash register 105 420 ss_adrr secure state address ram register 106 424 ss_adr0 secure state address 0 register 107 428 ss_adr1 secure state address 1 register 108 432 ss_sp_sys secure state stack pointer system register 109 436 ss_sp_app secure state stac k pointer application register 110 440 ss_rar secure state return address register 111 444 ss_rsr secure state return status register 112-191 448-764 reserved reserved for future use 192-255 768-1020 impl implementation defined table 4-3. system registers (continued) reg # address name function
31 32099a?avr32?06/09 at32uc3l relative to evba. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. the target address of the event handle r is calculated as (evba | event_handler_offset), not (evba + event_handler_offse t), so evba and exception code segments must be set up appropriately. the same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. an interrupt controller does the priority handling of the interrupts and provides the autovector off- set to the cpu. 4.5.1 system stack issues event handling in avr32uc uses the system stack pointed to by the system stack pointer, sp_sys, for pushing and popping r8 -r12, lr, status register, and return ad dress. since event code may be timing-critical, sp_sys should point to memory addresses in the iram section, since the timing of accesses to this memory section is both fast and deterministic. the user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. if the system stack is full, and an event occurs, the system will enter an undefined state. 4.5.2 exceptions and interrupt requests when an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. the pending event will not be acce pted if it is masked. the i3 m, i2m, i1m, i0m, em, and gm bits in the status register are used to mask different events. not all events can be masked. a few critical events (nmi, unreco verable exception, tlb multiple hit, and bus error) can not be masked. when an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. this inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. it is the event source?s respons- ability to ensure that their events are left pending until accepted by the cpu. 2. when a request is accepted, the status register and program counter of the current context is stored to the system stack. if the event is an int0, int1, int2, or int3, reg- isters r8-r12 and lr are also automatically stored to stack. storing the status register ensures that the core is returned to the previous execution mode when the current event handling is completed. when exceptions occur, both the em and gm bits are set, and the application may manually enable nested exceptions if desired by clear- ing the appropriate bit. each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. the mode bits are set to reflect the priority of the accepted event, and the correct regis- ter file bank is selected. the address of the event handler, as shown in table 4-4 on page 34 , is loaded into the program counter. the execution of the event handler routine then continues from the effective address calculated. the rete instruction signals the end of the event. when encountered, the return status register and return address register are popped from the system stack and restored to the status reg- ister and program counter. if the rete instruction returns from int0, int1, int2, or int3, registers r8-r12 and lr are also popped from the system stack. the restored status register contains information allowing the core to resume operation in the previous execution mode. this concludes the event handling.
32 32099a?avr32?06/09 at32uc3l 4.5.3 supervisor calls the avr32 instruction set provides a supervisor mode call instruction. the scall instruction is designed so that privileged routines can be called from any context. this facilitates sharing of code between different execution modes. the scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from time- critical event handlers. the scall instruction behaves differently depending on which mode it is called from. the behav- iour is detailed in the instruction se t reference. in order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets , is implemented. in the avr32uc cpu, scall and rets uses the system stack to store the return address and the status register. 4.5.4 debug requests the avr32 architecture defines a dedicated debug mode. when a debug request is received by the core, debug mode is entered. entry into debug mode can be masked by the dm bit in the status register. upon entry into debug mode, hardware sets the sr.d bit and jumps to the debug exception handler. by default, debug mode executes in the exception context, but with dedicated return address register and return status register. these dedicated registers remove the need for storing this data to the system stack, t hereby improving debuggability. the mode bits in the status register can freely be manipulated in debug mode, to observe registers in all contexts, while retaining full privileges. debug mode is exited by executing the retd instruction. this return s to the previous context. 4.5.5 entry points for events several different event handler entry points exist. in avr32uc, the reset address is 0x80000000. this places the reset address in the boot flash memory area. tlb miss exceptions and scall have a dedicated space relative to evba where their event han- dler can be placed. this speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. all other exceptions have a dedicated event routine entry point located relative to evba. the handler routine address identifies the exception source directly. avr32uc uses the itlb and dtlb protection exc eptions to signal a mp u protection violation. itlb and dtlb miss exceptions are used to signal that an access address did not map to any of the entries in the mpu. tlb multiple hit exception indicates that an access address did map to multiple tlb entries, signalling an error. all interrupt requests have entry points located at an offset relative to evba. this autovector off- set is specified by an interrupt controller. the programmer must make sure that none of the autovector offsets interfere with the placement of other code. the autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. special considerations should be made when loading evba with a po inter. due to security con- siderations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an mpu is present. if several events occur on the same instruction, they are handled in a prioritized way. the priority ordering is presented in table 4-4 on page 34 . if events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority
33 32099a?avr32?06/09 at32uc3l than the oldest instruction. an instruction b is younger than an instruction a if it was sent down the pipeline later than a. the addresses and priority of simultaneous events are shown in table 4-4 on page 34 . some of the exceptions are unused in avr32uc since it has no mmu, coprocessor interface, or floating- point unit.
34 32099a?avr32?06/09 at32uc3l table 4-4. priority and handler addresses for events priority handler address name event source stored return address 1 0x80000000 reset external input undefined 2 provided by ocd system ocd stop cpu ocd system first non-compl eted instruction 3 evba+0x00 unrecoverable exception int ernal pc of offending instruction 4 evba+0x04 tlb multiple hit mpu pc of offending instruction 5 evba+0x08 bus error data fetch data bu s first non-completed instruction 6 evba+0x0c bus error instruction fetch dat a bus first non-completed instruction 7 evba+0x10 nmi external input first non-completed instruction 8 autovectored interrupt 3 request external input first non-completed instruction 9 autovectored interrupt 2 request external input first non-completed instruction 10 autovectored interrupt 1 request external input first non-completed instruction 11 autovectored interrupt 0 request external input first non-completed instruction 12 evba+0x14 instruction address cp u pc of offending instruction 13 evba+0x50 itlb miss mpu pc of offending instruction 14 evba+0x18 itlb protection mpu pc of offending instruction 15 evba+0x1c breakpoint ocd system firs t non-completed instruction 16 evba+0x20 illegal opcode instructio n pc of offending instruction 17 evba+0x24 unimplemented instruction instr uction pc of offending instruction 18 evba+0x28 privilege violation instruc tion pc of offending instruction 19 evba+0x2c floating-point unused 20 evba+0x30 coprocessor absent instruct ion pc of offending instruction 21 evba+0x100 supervisor call instru ction pc(supervisor call) +2 22 evba+0x34 data address (read) cp u pc of offending instruction 23 evba+0x38 data address (write) cpu pc of offending instruction 24 evba+0x60 dtlb miss (read) mpu pc of offending instruction 25 evba+0x70 dtlb miss (write) mpu pc of offending instruction 26 evba+0x3c dtlb protection (read) mpu pc of offending instruction 27 evba+0x40 dtlb protection (write) m pu pc of offending instruction 28 evba+0x44 dtlb modified unused
35 32099a?avr32?06/09 at32uc3l 5. memories 5.1 embedded memories ? internal high-speed flash ? 64kbytes (at32uc3l064) ? 32kbytes (at32uc3l032) ? 16kbytes (at32uc3l016) ? - 0 wait state access at up to 25 mhz in worst case conditions ? - 1 wait state access at up to 50 mhz in worst case conditions ? - pipelined flash architecture, allowing bu rst reads from sequen tial flash locations, hiding penalty of 1 wait state access ? - pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation ? - 100 000 write cycles, 15-year data retention capability ? - 4ms page programming time, 8 ms chip erase time ? - sector lock capabilities, boot loader protection, security bit ? - 32 fuses, erased during chip erase ? - user page for data to be preserved during chip erase ? internal high-speed sram, singl e-cycle access at full speed ? 16kbytes (at32uc3l064, at32uc3l032) ? 8kbytes (at32uc3l016) 5.2 physical memory map the system bus is implemented as a bus matrix . all system bus addresses are fixed, and they are never remapped in any way, not even in boot. note that avr32 uc cpu uses unsegmented translation, as described in the avr32 architecture manual. the 32-bit physical address space is mapped as follows: table 5-1. at32uc3l physical memory map device start address size at32uc3l064 at32uc3l032 at32uc3l016 embedded sram 0x00000000 16 kbytes 16 kbytes 8 kbytes embedded flash 0x80000000 64 kbytes 32 kbytes 16 kbytes hsb-pb bridge b 0xfffe0000 64 kbytes 64 kbytes 64 kbytes hsb-pb bridge a 0xffff0000 64 kbytes 64 kbytes 64 kbytes table 5-2. flash memory parameters part number flash size ( flash_pw ) number of pages ( flash_p ) page size ( flash_w ) at32uc3l064 64 kbytes 256 64 words at32uc3l032 32 kbytes 128 64 words at32uc3l016 16 kbytes 64 64 words
36 32099a?avr32?06/09 at32uc3l 5.3 peripheral address map table 5-3. peripheral address mapping address peripheral name bus 0xfffe0000 flashcdw flash controller - flashcdw 0xfffe0400 hmatrix hsb matrix - hmatrix 0xfffe0800 sau secure access unit - sau 0xffff0000 pdca peripheral dma controller - pdca 0xffff1000 intc interrupt controller - intc 0xffff1400 pm power manager - pm 0xffff1800 scif system control interface - scif 0xffff1c00 ast asynchronous timer - ast 0xffff2000 wdt watchdog timer - wdt 0xffff2400 eic external interrupt controller - eic 0xffff2800 freqm frequency meter - freqm 0xffff2c00 gpio general purpose input/ output controller - gpio 0xffff3000 usart0 universal synchronous/asynchronous receiver/transmitter - usart0 0xffff3400 usart1 universal synchronous/asynchronous receiver/transmitter - usart1 0xffff3800 usart2 universal synchronous/asynchronous receiver/transmitter - usart2 0xffff3c00 usart3 universal synchronous/asynchronous receiver/transmitter - usart3 0xffff4000 spi serial peripheral interface - spi 0xffff4400 twim0 two-wire master interface - twim0
37 32099a?avr32?06/09 at32uc3l 5.4 cpu local bus mapping some of the registers in the gpio module are mapped onto the cpu local bus, in addition to being mapped on the peripheral bus. these registers can therefore be reached both by accesses on the peripheral bus, and by accesses on the local bus. mapping these registers on the local bus allows cycle-deterministic toggling of gpio pins since the cpu and gpio are the only modules connected to this bus. also, since the local bus runs at cpu speed, one write or read operation can be pe rformed per clock cycle to the local bus- mapped gpio registers. 0xffff4800 twim1 two-wire master interface - twim1 0xffff4c00 twis0 two-wire slave interface - twis0 0xffff5000 twis1 two-wire slave interface - twis1 0xffff5400 pwma basic pulse width modulation controller - pwma 0xffff5800 tc0 timer/counter - tc0 0xffff5c00 tc1 timer/counter - tc1 0xffff6000 adcifb adc interface - adcifb 0xffff6400 acifb analog comparator interface - acifb 0xffff6800 cat capacitive touch module - cat 0xffff6c00 gloc glue logic controller - gloc 0xffff7000 aw awire - aw table 5-3. peripheral address mapping
38 32099a?avr32?06/09 at32uc3l the following gpio registers are mapped on the local bus: table 5-4. local bus mapped gpio registers port register mode local bus address access a output driver enable register (oder) write 0x40000040 write-only set 0x40000044 write-only clear 0x40000048 write-only toggle 0x4000004c write-only output value register (ovr) write 0x40000050 write-only set 0x40000054 write-only clear 0x40000058 write-only toggle 0x4000005c write-only pin value register (pvr) - 0x40000060 read-only b output driver enable register (oder) write 0x40000240 write-only set 0x40000244 write-only clear 0x40000248 write-only toggle 0x4000024c write-only output value register (ovr) write 0x40000250 write-only set 0x40000254 write-only clear 0x40000258 write-only toggle 0x4000025c write-only pin value register (pvr) - 0x40000260 read-only
39 32099a?avr32?06/09 at32uc3l 6. boot sequence this chapter summarizes the boot sequence of the at32uc3l. the behavior after power-up is controlled by the power manager. for specific details, refer to the power manager chapter. 6.1 starting of clocks after power-up, the device will be held in a reset state by the power-on reset circuitry for a short time to allow the power to stabilize throu ghout the device. after reset, the device will use the system rc oscillator (rcsys) as clock source. please refer to table 32-20 on page 795 for the frequency for this oscillotor. on system start-up, the dfll is disabled. all clocks to all modules are running. no clocks have a divided frequency; all parts of the system receive a clock with the same frequency as the sys- tem rc oscillator. 6.2 fetching of initial instructions after reset has been released, the avr32 uc cpu starts fetching instructions from the reset address, which is 0x80000000. this address points to the first address in the internal flash. the code read from the internal flash is free to configure the system to use for example the dfll, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 6.3 rc32k clock output at startup after power-up, the cloc k generated by t he 32khz rc oscillator (rc32k) will be output on i/o line pa20, even when the device is still re set by the power-on reset circuitry. this clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value. the clock will be available on i/o line pa20 un til one of the followin g conditions are true: ? pa20 is configured to use a gpio function other than f (scif-rc32out) ? pa20 is configured as a general purpose input/output (gpio) ? the bit frc32 in the power manager ppcr register is cleared (see power manager chapter) the maximum amplitude of the clock signal will be defined by vddin.
40 32099a?avr32?06/09 at32uc3l 7. flash controller (flashcdw) rev: 1.0.2.0 7.1 features ? controls on-chip flash memory ? supports 0 and 1 wait state bus access ? buffers reducing penalty of wait state in sequential code or loops ? allows interleaved burst reads for systems with one wait state, outputti ng one 32-bit word per clock cycle for sequential reads ? supports avr32 secure state ? 32-bit hsb interface for reads from flash and writes to page buffer ? 32-bit pb interface for issuing commands to and configuratio n of the controller ? flash memory is divided into 16 regions can be individual ly protected or unprotected ? additional protection of the boot loader pages ? supports reads and writes of general-purpose nvm bits ? supports reads and writes of additional nvm pages ? supports device protection through a security bit ? dedicated command for chip-erase, first erasing all on-chip volatile me mories before erasing flash and clearing security bit 7.2 overview the flash controller (flashcdw) interfaces the on-chip flash memory with the 32-bit inter- nal hsb bus. the controller manages the reading, writing, erasing, locking, and unlocking sequences. 7.3 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 7.3.1 power management if the cpu enters a sleep mode that disables clocks used by the flashcdw, the flash- cdw will stop functioning and re sume operation after the syste m wakes up from sleep mode. 7.3.2 clocks the flashcdw has two bus clocks conn ected: one high speed bus clock (clk_flashcdw_hsb) and one peripheral bu s clock (clk_flashcdw_pb). these clocks are generated by the power manager. both clocks are enabled at reset, and can be dis- abled by writing to the power manager. the user has to ensure that clk_flashcdw_hsb is not turned off before reading the flash or writing the pagebuffer and that clk_flashcdw_pb is not turned off before accessing the flashcdw configuration and control registers. failing to do so may deadlock the bus. 7.3.3 interrupts the flashcdw interrupt request lines are connected to the interrupt controller. using the flashcdw interrupts requires the interrupt controller to be progra mmed first.
41 32099a?avr32?06/09 at32uc3l 7.3.4 debug operation when an external debugger forces the cpu into debug mode, the flashcdw continues nor- mal operation. if the flashcdw is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 7.4 functional description 7.4.1 bus interfaces the flashcdw has two bus interfaces, one high speed bus (hsb) interface for reads from the flash memory and writes to the page buffer, and one peripheral bus (pb) interface for issu- ing commands and reading status from the controller. 7.4.2 memory organization the flash memory is divided into a set of page s. a page is the basic unit addressed when pro- gramming the flash. a page consists of severa l words. the pages are grouped into 16 regions of equal size. each of these regions can be locked by a dedicated fuse bit, protecting it from accidental modification. ? p pages ( flash_p ) ? 256 bytes in each page and in the page buffer ( flash_w ) ? pw bytes in total ( flash_pw ) ? f general-purpose fuse bits ( flash_f ), used as region lock bits and for other device- specific purposes ? 1 security fuse bit ? 1 user page 7.4.3 user page the user page is an additional page, outside the regular flash array, that can be used to store various data, such as calibration data and serial numbers. this page is not erased by regular chip erase. the user page can only be written and erased by a special set of commands. read accesses to the user page are performed just as any other read accesses to the flash. the address map of the user page is given in figure 7-1 on page 43 . 7.4.4 read operations the on-chip flash memory is typically used for st oring instructions to be executed by the cpu. the cpu will address instructio ns using the hsb bus, and the flashcdw will access the flash memory and return the addressed 32-bit word. in systems where the hsb clock period is slower than the access time of the flash memory, the flashcdw can operate in 0 wait state mode, and output one 32-bit word on the bus per clock cycle. if the clock frequency allows, the user should use 0 wait state mode, because this gives the highest performance as no stall cycles are encountered. the flashcdw can also operate in systems where the hsb bus clock period is faster than the access speed of the flash memory. wait state support and a read granularity of 64 bits ensure efficiency in such systems. performance for systems with high clock frequency is increased since the internal read word width of the flash memory is 64 bits. when a 32-bit word is to be addressed, the word itself
42 32099a?avr32?06/09 at32uc3l and also the other word in the same 64-bit location is read. the first word is output on the bus, and the other word is put into an internal buffer. if a read to a sequential address is to be per- formed in the next cycle, the buffered word is output on the bus, while the next 64-bit location is read from the flash memory. thus, latency in 1 wait state mode is hidden for sequential fetches. the programmer can select the wait states required by writing to the fws field in the flash control register (fcr). it is the responsibility of the programmer to select a number of wait states compatible with the clock frequency and timing characteristics of the flash memory. in 0ws mode, no wait states are encountered on any flash read operations. in 1 ws mode, one stall cycle is encountered on the first access in a single or burst transfer. in 1 ws mode, if the first access in a burst access is to an address that is not 64-bit aligned, an additional stall cycle is also encountered when reading the second word in the burst. all subsequent words in the burst are accessed without any stall cycles. the flash controller provides two sets of buffers that can be enabled in order to speed up instruction fetching. these buffers can be enabled by writing a one to the fcr.seqbuf and fcr.brbuf bits. the seqbuf bit enables buff ering hardware optimiz ing sequential instruc- tion fetches. the brbuf bit enables buffering hardware optimizing tight inner loops. these buffers are never used when the flash is in 0 wait state mode. usually, both these buffers should be enabled when operating in 1 wait state mode. some users requiring absolute cycle determinism may want to keep the buffers disabled. the flash controller address space is displayed in figure 7-1 . the memory space between address pw and the user page is reserved, and reading addresses in this space returns an undefined result. the user page is permanently mapped to an offset of 0x00800000 from the start address of the flash memory. table 7-1. user page addresses memory type start address, byte sized size main array 0 pw words = 4 pw bytes user 0x00800000 64 words = 256 bytes
43 32099a?avr32?06/09 at32uc3l figure 7-1. memory map for the flash memories 7.4.5 high speed read mode the flash provides a high speed read mode, o ffering slightly higher flash read speed at the cost of higher power consumption. two dedicated commands, high speed read mode enable (hsen) and high speed read mode disabl e (hsdis) control the speed mode. the high speed mode (hsmode) bit in the flash status register (fsr) shows which mode the flash is in. after reset, the high speed mode is disabled, and must be manually enabled if the user wants to. refer to the electrical characteristics chapter at the end of this datasheet for details on the maximum clock frequencies in norm al and high speed read mode. 0 pw reserved flash data array reserved user page flash with user page 0x0080 0000 all addresses are byte addresses flash base address offset from base address
44 32099a?avr32?06/09 at32uc3l figure 7-2. high speed mode 7.4.6 quick page read a dedicated command, quick page read (qpr), is provided to read all words in an addressed page. all bits in all words in this page are and?ed together, returning a 1-bit result. this result is placed in the quick page read result (qprr) bit in flash status register (fsr). the qpr command is useful to check that a page is in an erased state. the qpr instruction is much faster than performing the erased-page check using a regular software subroutine. 7.4.7 page buffer operations the flash memory has a write and erase granularity of one page; data is written and erased in chunks of one page. when programming a page, the user must first write the new data into the page buffer. the contents of the entire page buffer is copied into the desired page in flash memory when the user issues the write page command, refer to section 7.5.1 on page 47 . in order to program data into flash page y, write the desired data to locations y0 to y31 in the regular flash memory map. writ ing to an address a in the fl ash memory map will not update the flash memory, but will instead update location a%32 in the page buff er. the pagen field in the flash command (fcmd) register will at th e same time be updated with the value a/32. frequency frequency limit for 0 wait state operation normal high speed mode 1 wait state 0 wait state
45 32099a?avr32?06/09 at32uc3l figure 7-3. mapping from page buffer to flash internally, the flash memory stores data in 64-bit doublewords. therefore, the native data size of the page buffer is also a 64-bit doubleword. all locations shown in figure 7-3 are therefore doubleword locations. since the hsb bus only has a 32-bit data width, two 32-bit hsb trans- fers must be performed to write a 64-bit doubleword into the p age buffer. the flashcdw has logic to combine two 32-bit hsb transfers into a 64-bit data before writing this 64-bit data into the page buffer. this logic requires the word with the low address to be written to the hsb bus before the word with the high address. to exemplify, to write a 64-bit value to doubleword x0 residing in page x, first write a 32-bit word to the byte address pointing to address x0, thereafter write a word to the byte address pointing to address (x0+4). the page buffer is word-addressable and should only be written with aligned word transfers, never with byte or halfword transfers. the page buffer can not be read. the page buffer is also used for writes to the user page. page buffer write operations are performed with 4 wait states. any accesses attempted to the flashcdw on the hsb bus du ring these cycles will be automatically stalled. writing to the page buffer can only change page buffer bits from one to zero, i.e. writing 0xaaaaaaaa to a page buffer location that has the value 0x000000 00 will not change the page buffer value. the only way to change a bit from zero to one is to erase the entire page buffer with the clear page buffer command. z3 z2 z1 z0 z7 z6 z5 z4 z11 z10 z9 z8 z15 z14 z13 z12 z19 z18 z17 z16 z23 z22 z21 z20 z27 z26 z25 z24 z31 z30 z29 z28 y3 y2 y1 y0 y7 y6 y5 y4 y11 y10 y9 y8 y15 y14 y13 y12 y19 y18 y17 y16 y23 y22 y21 y20 y27 y26 y25 y24 y31 y30 y29 y28 x3 x2 x1 x0 x7 x6 x5 x4 x11 x10 x9 x8 x15 x14 x13 x12 x19 x18 x17 x16 x23 x22 x21 x20 x27 x26 x25 x24 x31 x30 x29 x28 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 19 18 17 16 23 22 21 20 27 26 25 24 31 30 29 28 page x page y page z page buffer 64-bit data flash all locations are doubleword locations
46 32099a?avr32?06/09 at32uc3l the page buffer is not automatically reset after a page write. the programmer should do this manually by issuing the clear page buffer flash command. this can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. 7.4.8 writing words to a page that is not completely erased this can be used for eeprom emul ation, i.e. writes wi th granularity of on e word instead of an entire page. note that ?one word? for the flaschdw is actually 64 bits. only words that are in a completely erased state (0xffffffffffffffff) can be changed. the procedure is as follows: 1. clear page buffer. 2. write to the page buffer the result of the logical bitwise and operation between the contents of the flash page and the new data to write. only bits that were in an erased state can be changed from the original page. 3. write page. 7.5 flash commands the flashcdw offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. see section 7.8.2 for a complete list of commands. to run a command, the cmd field in the flash command register (fcmd) has to be written with the command number. as soon as the fcmd register is written, the frdy bit in the flash status register (fsr) is automatically cleared. once the current command is complete, the fsr.frdy bit is automatically set. if an interrupt has been enabled by writing a one to fcr.frdy, the interrupt request line of the flash controller is activated. all flash commands except for quick page read (qpr) will gener ate an interrupt request upon completion if fcr.frdy is one. any hsb bus transfers attempting to read flash memory when the flashcdw is busy exe- cuting a flash command will be stalled, and a llowed to continue when the flash command is complete. after a command has been written to fcmd, the programming algorithm should wait until the command has been executed before attempting to read instructions or data from the flash or writing to the page buffer, as the flash will be busy. the waiting can be performed either by polling the flash status register (fsr) or by waiting for the flash ready interrupt. the com- mand written to fcmd is initiated on the first clock cycle where the hsb bus interface in flashcdw is idle. the user must make sure that the access pa ttern to the flashcdw hsb interface contains an idle cycle so that th e command is allowed to start. make sure that no bus masters such as dma controllers are performing endless burst transfers from the flash. also, make sure that the cpu does not perform endless burst transfers from flash. this is done by letting the cpu enter sleep mode after writing to fcmd, or by polling fsr for com- mand completion. this polling will result in an access pa ttern with idle hsb cycles. all the commands are protected by the same ke yword, which has to be written in the eight highest bits of the fcmd register. writing fcmd with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the proge bit is set in the flash status register (fsr). th is bit is automatically cleared by a read access to the fsr register.
47 32099a?avr32?06/09 at32uc3l writing a command to fcmd while another command is being executed has no effect on the flash memory; however, the proge bit is set in the flash status register (fsr). this bit is automatically cleared by a read access to the fsr register. if the current command writes or erases a page in a locked region, or a page protected by the bootprot fuses, the command has no effect on the flash memory; however, the locke bit is set in the fsr register. th is bit is automatically cleared by a read access to the fsr register. 7.5.1 write/erase page operation flash technology requires that an erase must be done before programming. the entire flash can be erased by an erase all command. alte rnatively, pages can be individually erased by the erase page command. the user page can be written and erased usin g the mechanisms descr ibed in this chapter. after programming, the page can be locked to prevent miscellaneous write or erase sequences. locking is performed on a per-region basis, so locking a region locks all pages inside the region. additional protection is provided for the lowermost address space of the flash. this address space is allocated for the boot loader, and is protected both by the lock bit(s) corresponding to this address space, and the bootprot[2:0] fuses. data to be written is stored in an internal buffer called the page buffer. the page buffer con- tains w words. the page buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. writing of 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption. data must be written to the page buffer before the programming command is written to the flash command register (fcmd). the sequence is as follows: ? reset the page buffer with the clear page buffer command. ? fill the page buffer with the desired content s as described in section 7.4.7 on page 44 . ? programming starts as soon as the programming key and the programming command are written to the flash command register. the pagen field in the flash command register (fcmd) must contain the address of the page to write. pagen is automatically updated when writing to the page buffer, but can also be written to directly. the frdy bit in the flash status register (fsr) is automatically cleared when the page write operation starts. ? when programming is completed, the frdy bit in the flash status register (fsr) is set. if an interrupt was enabled by writing fcr.frdy to one, an interrupt request is generated. two errors can be detected in the fsr register after a programming sequence: ? programming error: a bad keyword and/or an invalid command have been written in the fcmd register. ? lock error: can have two different causes: ? the page to be programmed belongs to a locked region. a command must be executed to unlock the corresponding region before programming can start. ? a bus master without secure status attempted to program a page requiring secure privileges. 7.5.2 erase all operation the entire memory is erased if the erase all command (ea) is written to the flash command register (fcmd). erase all erases all bits in th e flash array. the user page is not erased. all
48 32099a?avr32?06/09 at32uc3l flash memory locations, the general-purpose fuse bits, and the security bit are erased (reset to 0xff) after an erase all. the ea command also ensures that all volatile memories, such as register file and rams, are erased before the security bit is erased. erase all operation is allowed only if no regions are locked, and the bootprot fuses are configured with a bootprot region size of 0. th us, if at least one region is locked, the bit locke in fsr is set and the co mmand is cancelled. if the loc ke bit in fcr is one, an inter- rupt request is set generated. when the command is complete, the frdy bit in the flash status register (fsr) is set. if an interrupt has been enabled by writing fcr.frdy to one, an interrupt request is generated. two errors can be detected in the fsr register after issuing the command: ? programming error: a bad keyword and/or an invalid command have been written in the fcmd register. ? lock error: at least one lock region is protected, or bootprot is different from 0. the erase command has been aborted and no page has been erased. a ?unlock region containing given page? (up) command must be executed to unlock any locked regions. 7.5.3 region lock bits the flash memory has p pages, and these pages are grouped into 16 lock regions, each region containing p /16 pages. each region has a dedicated lock bit preventing writing and erasing pages in the region. after production, the device may have some regions locked. these locked regions are reserved for a boot or default application. locked regions can be unlocked to be erased and then programmed with another application or other data. to lock or unlock a region, the commands lock region containing page (lp) and unlock region containing page (up) are provided. writ ing one of these commands, together with the number of the page whose region should be locked/unlocked, performs the desired operation. one error can be detected in the fsr register after issuing the command: ? programming error: a bad keyword and/or an invalid command have been written in the fcmd register. the lock bits are implemented using the lowest 16 general-purpose fuse bits. this means that lock bits can also be set/cleared using the commands for writing/erasing general-purpose fuse bits, see section 7.6 . the general-purpose bit being in an erased (1) state means that the region is unlocked. the lowermost pages in the flash can additiona lly be protected by the bootprot fuses, see section 7.6 . 7.6 general-purpose fuse bits the flash memory has a number of general-purpose fuse bits that the application programmer can use freely. the fuse bits can be written and erased using dedicated commands, and read
49 32099a?avr32?06/09 at32uc3l through a dedicated peripheral bus address. some of the general-purpose fuse bits are reserved for special purposes, and shou ld not be used for other functions: table 7-2. general-purpose fuses with special functions general- purpose fuse number name usage 15:0 lock region lock bits. 16 epfl external privileged fetch lock. used to prevent the cpu from fetching instructions from external memories when in privileged mode. this bit can only be changed when the security bit is cleared. the address range corresponding to external memories is device-specific, and not known to the flash controller. this fuse bit is simply routed out of the cpu or bus system, the flash controller does not treat this fuse in any special way, except that it can not be altered when the security bit is set. if the security bit is set, only an external jtag or awire chip erase can clear epfl. no internal commands can alter epfl if the security bit is set. when the fuse is erased (i.e. "1"), the cpu can execute instructions fetched from external memories. when the fuse is programmed (i.e. "0"), instructions can not be executed from external memories. this fuse has no effect in de vices with no external memory interface (ebi). 19:17 bootprot used to select one of eight different bootloader sizes. pages included in the bootloader area can not be erased or programmed except by a jtag or awire chip erase. bootprot can only be changed when the security bit is cleared. if the security bit is set, only an external jtag or awire chip erase can clear bootprot, and thereby allow the pages protected by bootprot to be programmed. no internal commands can alter bootprot or the pages protected by bootprot if the security bit is set. 21:20 secure used to configure secure state and secure state debug capabilities. decoded into sse and ssde signals as shown in table 7-4 . refer to the avr32 architecture manual and the avr32uc technical reference manual for more details on sse and ssde. 22 uprot if programmed (i.e. ?0?), the jtag user protection feature is enabled. if this fuse is programmed some hsb addresses will be accessible by jtag access even if the flash security fuse is programmed. refer to the jtag documentation for more information on this functionality. this bit can only be changed when the security bit is cleared.
50 32099a?avr32?06/09 at32uc3l the bootprot fuses protects the following address space for the boot loader: the secure fuses have the following functionality: to erase or write a general-purpose fuse bit, the commands write general-purpose fuse bit (wgpb) and erase general-purpose fuse bit (e gpb) are provided. writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation. an entire general-purpose fuse byte can be written at a time by using the program gp fuse byte (pgpfb) instruction. a pgpfb to gp fuse byte 2 is not allowed if the flash is locked by the security bit. the pfb command is issued with a parameter in the pagen field: ? pagen[2:0] - byte to write ? pagen[10:3] - fuse value to write all general-purpose fuses can be erased by the erase all general-purpose fuses (eagp) command. an eagp command is not allowed if the flash is locked by the security bit. two errors can be detected in the fsr register after issuing these commands: ? programming error: a bad keyword and/or an invalid command have been written in the fcmd register. ? lock error: ? a write or erase of the bootprot or epfl or uprot fuse bits was attempted while the flash is locked by the security bit. ? a write or erase of the secure fuse bits was attempted when secure mode was enabled. table 7-3. boot loader area specified by bootprot bootprot pages protected by bootprot size of protected memory 7none 0 6 0-1 512 byte 50-3 1kbyte 40-7 2kbyte 3 0-15 4kbyte 2 0-31 8kbyte 10-63 16kbyte 0 0-127 32kbyte table 7-4. secure state configuration secure functionality sse ssde 00 secure state disabled 0 0 01 secure enabled, secure state debug enabled 1 1 10 secure enabled, secure state debug disabled 1 0 11 secure state disabled 0 0
51 32099a?avr32?06/09 at32uc3l the lock bits are implemented using the lowest 16 general-purpose fuse bits. this means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see section 7.5.3 . 7.7 security bit the security bit allows the entire chip to be locked from external jtag, awire, or other debug access for code security. the security bit can be written by a dedicated command, set secu- rity bit (ssb). once set, the only way to clear the security bit is through the jtag or awire chip erase command. once the security bit is set, the following fl ash controller commands will be unavailable and return a lock error if attempted: ? write general-purpose fuse bit (w gpb) to bootprot or epfl fuses ? erase general-purpose fuse bit (e gpb) to bootprot or epfl fuses ? program general-purpose fuse byte (pgpfb) of fuse byte 2 ? erase all general-purpose fuses (eagpf) one error can be detected in the fsr register after issuing the command: ? programming error: a bad keyword and/or an invalid command have been written in the fcmd register.
52 32099a?avr32?06/09 at32uc3l 7.8 user interface note: 1. the value of the lock bits depend on their programmed state. all other bits in fsr are 0. 2. all bits in fgprhi/lo are dependent on the programmed stae of the fuses they map to. any bits in these registers not mapped to a fuse read as 0. 3. the reset values for these registers are device specific. plea se refer to the module configuration section at the end of this chapter. table 7-5. flashcdw register memory map offset register register name access reset 0x00 flash control register fcr read/write 0x00000000 0x04 flash command register fcmd read/write 0x00000000 0x08 flash status register fsr read/write - (1) 0x0c flash parameter register fpr read-only - (3) 0x10 flash version register fvr read-only - (3) 0x14 flash general purpose fuse register hi fgpfrhi read-only - (2) 0x18 flash general purpose fuse register lo fgpfrlo read-only - (2)
53 32099a?avr32?06/09 at32uc3l 7.8.1 flash control register name: fcr access type: read/write offset :0x00 reset value: 0x00000000 ? brbuf: branch target instruction buffer enable 0: the branch target instru ction buffer is disabled. 1: the branch target instruction buffer is enabled. ? seqbuf: sequential instru ction fetch buffer enable 0: the sequential instruction fetch buffer is disabled. 1: the sequential instruction fetch buffer is enabled. ? fws: flash wait state 0: the flash is read with 0 wait states. 1: the flash is read with 1 wait state. ? proge: programming error interrupt enable 0: programming error does not generate an interrupt request. 1: programming error generates an interrupt request. ? locke: lock error interrupt enable 0: lock error does not generate an interrupt request. 1: lock error generates an interrupt request. ? frdy: flash ready interrupt enable 0: flash ready does not generate an interrupt request. 1: flash ready generates an interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -----brbufseqbuf- 76543210 - fws - - proge locke - frdy
54 32099a?avr32?06/09 at32uc3l 7.8.2 flash command register name: fcmd access type: read/write offset :0x04 reset value: 0x00000000 the fcmd can not be written if the flash is in the process of performing a flash command. doing so will cause the fcr write to be igno red, and the proge bit in fsr to be set. ? key: write protection key this field should be written with the value 0xa5 to enable the command defined by the bits of t he register. if the field is wri tten with a different value, the write is not performed and no action is started. this field always reads as 0. ?pagen: page number the pagen field is used to address a page or fuse bit for certai n operations. in order to simplify programming, the pagen field is automatically updated every time the page buffer is written to. for every page buffer write, the pagen field is updated with the page number of the address being written to. hardware automatically masks writes to the pagen field so that only bits representing valid page numbers can be writt en, all other bits in pagen are always 0. as an example, in a flash with 1024 pages (page 0 - page 1023), bits 15:10 will always be 0. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 pagen [15:8] 15 14 13 12 11 10 9 8 pagen [7:0] 76543210 -- cmd table 7-6. semantic of pagen field in different commands command pagen description no operation not used write page the number of the page to write clear page buffer not used lock region containing given page page number whose region should be locked unlock region containing given page page number whose region should be unlocked erase all not used write general-purpose fuse bit gpfuse # erase general-purpose fuse bit gpfuse # set security bit not used
55 32099a?avr32?06/09 at32uc3l ? cmd: command this field defines the flash command. issuing any unused command will cause the programming error bit in fsr to be set, and the corresponding interrupt to be requested if the proge bit in fcr is one. program gp fuse byte writed ata[7:0], byteaddress[2:0] erase all gp fuses not used quick page read page number write user page not used erase user page not used quick page read user page not used high speed mode enable not used high speed mode disable not used table 7-7. set of commands command value mnemonic no operation 0 nop write page 1 wp erase page 2 ep clear page buffer 3 cpb lock region containing given page 4 lp unlock region containing given page 5 up erase all 6 ea write general-purpose fuse bit 7 wgpb erase general-purpose fuse bit 8 egpb set security bit 9 ssb program gp fuse byte 10 pgpfb erase all gpfuses 11 eagpf quick page read 12 qpr write user page 13 wup erase user page 14 eup quick page read user page 15 qprup high speed mode enable 16 hsen high speed mode disable 17 hsdis reserved 16-31 table 7-6. semantic of pagen field in different commands command pagen description
56 32099a?avr32?06/09 at32uc3l 7.8.3 flash status register name: fsr access type: read/write offset :0x08 reset value: 0x00000000(*) ? lockx: lock region x lock status 0: the corresponding lock region is not locked. 1: the corresponding lock region is locked. ? hsmode: high-speed mode 0: high-speed mode disabled. 1: high-speed mode enabled. ? qprr: quick page read result 0: the result is zero, i.e. the page is not erased. 1: the result is one, i.e. the page is erased. ? security: security bit status 0: the security bit is inactive. 1: the security bit is active. ? proge: programming error status automatically cleared when fsr is read. 0: no invalid commands and no bad keywords were written in the flash command register fcmd. 1: an invalid command and/or a bad keyword was/we re written in the flash command register fcmd. ? locke: lock error status automatically cleared when fsr is read. 0: no programming of at least one locked lock region has happened since the last read of fsr. 1: programming of at least one locked lock region has happened since the last read of fsr. ? frdy: flash ready status 0: the flash controller is busy and the application must wait before running a new command. 1: the flash controller is ready to run a new command. 31 30 29 28 27 26 25 24 lock15 lock14 lock13 lock12 lock11 lock10 lock9 lock8 23 22 21 20 19 18 17 16 lock7 lock6 lock5 lock4 lock3 lock2 lock1 lock0 15 14 13 12 11 10 9 8 -------- 76543210 - hsmode qprr security proge locke - frdy
57 32099a?avr32?06/09 at32uc3l 7.8.4 flash parameter register name: fpr access type: read-only offset :0x0c reset value: - ? psz: page size the size of each flash page. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ---- psz 76543210 ---- fsz table 7-8. flash page size psz page size 032 byte 164 byte 2128 byte 3256 byte 4512 byte 5 1024 byte 6 2048 byte 7 4096 byte
58 32099a?avr32?06/09 at32uc3l ? fsz: flash size the size of the flash. not all device families will provide all flash sizes indicated in the table. table 7-9. flash size fszflash sizefszflash size 0 4 kbyte 8 192 kbyte 1 8 kbyte 9 256 kbyte 2 16 kbyte 10 384 kbyte 3 32 kbyte 11 512 kbyte 4 48 kbyte 12 768 kbyte 5 64 kbyte 13 1024 kbyte 6 96 kbyte 14 2048 kbyte 7 128 kbyte 15 reserved
59 32099a?avr32?06/09 at32uc3l 7.8.5 flash version register name: fvr access type: read-only offset :0x10 reset value: 0x00000000(*) ? variant: variant number reserved. no functi onality associated. ? version: version number version number of the module . no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 ---- version[11:8] 76543210 version[7:0]
60 32099a?avr32?06/09 at32uc3l 7.8.6 flash general purpose fuse register high name: fgpfrhi access type: read-only offset :0x14 reset value: - this register is only used in syst ems with more t han 32 gp fuses. ? gpfxx: general purpose fuse xx 0: the fuse has a written/programmed state. 1: the fuse has an erased state. 31 30 29 28 27 26 25 24 gpf63 gpf62 gpf61 gpf60 gpf59 gpf58 gpf57 gpf56 23 22 21 20 19 18 17 16 gpf55 gpf54 gpf53 gpf52 gpf51 gpf50 gpf49 gpf48 15 14 13 12 11 10 9 8 gpf47 gpf46 gpf45 gpf44 gpf43 gpf42 gpf41 gpf40 76543210 gpf39 gpf38 gpf37 gpf36 gpf35 gpf34 gpf33 gpf32
61 32099a?avr32?06/09 at32uc3l 7.8.7 flash general purpose fuse register low name: fgpfrlo access type: read-only offset :0x18 reset value: - ? gpfxx: general purpose fuse xx 0: the fuse has a written/programmed state. 1: the fuse has an erased state. 31 30 29 28 27 26 25 24 gpf31 gpf30 gpf29 gpf28 gpf27 gpf26 gpf25 gpf24 23 22 21 20 19 18 17 16 gpf23 gpf22 gpf21 gpf20 gpf19 gpf18 gpf17 gpf16 15 14 13 12 11 10 9 8 gpf15 gpf14 gpf13 gpf12 gpf11 gpf10 gpf09 gpf08 76543210 gpf07 gpf06 gpf05 gpf04 gpf03 gpf02 gpf01 gpf00
62 32099a?avr32?06/09 at32uc3l
63 32099a?avr32?06/09 at32uc3l 7.9 fuse settings the flash block contains 32 general purpose fuses. these 32 fuses can be found in the flash general purpose fuse register low (fgpfrlo). the flash general purpose fuse register high (fgpfrhi) is not used. some of these fuse s have defined meanings outside the flash con- troller and are described in this section. in addition to the general purpose fuses, parts of the flash user row can have a defined mean- ing outside the flash controller and are described in this section. the general purpose fuses are erased by a jtag or awire chip erase. 7.9.1 flash general purpose fuse register low (fgpfrlo) boden: brown out detector enable bodhyst: brown out de tector hysteresis 0: the brown out detector hysteresis is disabled 1: the brown out detector hysteresis is enabled bodlevel: brown out detector trigger level this controls the voltage trigger level for the brown out detector. refer to ?electrical characteris- tics? on page 786 . uprot, secure, bootprot, epfl, lock these are flash controller fuses and ar e described in the flashcdw section. 31 30 29 28 27 26 25 24 boden bodhyst bodlevel[5:1] 23 22 21 20 19 18 17 16 bodlevel[0] uprot secure bootprot epfl 15 14 13 12 11 10 9 8 lock[15:8] 7 6543210 lock[7:0] boden description 00 bod disabled 01 bod enabled, bod reset enabled 10 bod enabled, bod reset disabled 11 reserved
64 32099a?avr32?06/09 at32uc3l 7.9.1.1 default fuse value the devices are shipped with the fgpfrlo register value: 0xe077ffff: ? boden fuses set to 11. bod is disabled. ? bodhyst fuse set to 1. the bod hysteresis is enabled. ? bodlevel fuses set to 000000. this is the minimum voltage trigger level for bod. ? uprot fuse set to 1. ? secure fuse set to 11. ? bootprot fuses set to 011. the bootloader protected size is 8kbytes. ? epfl fuse set to 1. external privileged fetch is not locked. ? lock fuses set to 1111111111111111. no region locked. after the jtag or awire chip erase command, the fgpfr register value is 0xffffffff. 7.9.2 first word of the user row (address 0x80800000) wdtauto: watchdog timer auto enable at startup 0: the wdt is automatically enabled at startup. 1: the wdt is not automatically enabled at startup. please refer to the wdt chapter for detail about timeout settings when the wdt is automatically enabled. 7.9.2.1 default user row first word value the devices are shipped with the user row erased (all bits 1): ? wdtauto set to 1, wdt disabled. 31 30 29 28 27 26 25 24 - ------- 23 22 21 20 19 18 17 16 - ------- 15 14 13 12 11 10 9 8 - ------- 7 6543210 - ------wdtauto
65 32099a?avr32?06/09 at32uc3l 7.9.3 second word of the user row (address 0x80800004) ssadrr: secure state end address for the ram ssadrf: secure state end address for the flash 7.9.3.1 default user row second word value the devices are shipped with the user row erased (all bits 1). 7.10 module configuration the specific configuration for each flashcdw instance is listed in the following tables.the module bus clocks listed here are c onnected to the system bus cloc ks. please refer to the power manager chapter for details. 31 30 29 28 27 26 25 24 ssadrr[15:8] 23 22 21 20 19 18 17 16 ssadrr[7:0] 15 14 13 12 11 10 9 8 ssadrf[15:8] 7 6543210 ssadrf[7:0] table 7-10. module configuration feature at32uc3l064 at32uc3l032 at32uc3l016 flash size 64kbytes 32kbytes 16kbytes number of pages 256 128 64 page size 256 bytes 256 bytes 256 bytes table 7-11. module clock name module name clock name clock name flashcdw clk_flashcdw_hsb clk_flashcdw_pb table 7-12. register reset values register reset value fvr 0x00000102 fpr 0x00000305
66 32099a?avr32?06/09 at32uc3l 8. hsb bus matrix (hmatrix) rev: 1.3.0.3 8.1 features ? user interface on peripheral bus ? configurable number of masters (up to 16) ? configurable number of slaves (up to 16) ? one decoder for each master ? three different memory mappings for each master (internal and external boot, remap) ? one remap function for each master ? programmable arbitration for each slave ? round-robin ? fixed priority ? programmable default master for each slave ? no default master ? last accessed default master ? fixed default master ? one cycle latency for the first access of a burst ? zero cycle latency for default master ? one special function register for each slave (not dedicated) 8.2 overview the bus matrix implements a multi-layer bus structure, that enables parallel access paths between multiple high speed bus (hsb) masters and slaves in a system, thus increasing the overall bandwidth. the bus matrix interconnects up to 16 hsb masters to up to 16 hsb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix provides 16 special function registers (sfr) that allow the bus matrix to support application specific features. 8.3 product dependencies in order to configure this module by accessing the user registers, other parts of the system must be configured correctly, as described below. 8.3.1 clocks the clock for the hmatrix bus interface (clk_hmatrix) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. 8.4 functional description 8.4.1 special bus granting mechanism the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism reduc es latency at first access of a burst or single transfer. this bus granting mechanism sets a different default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master, and fixed default master.
67 32099a?avr32?06/09 at32uc3l to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2-bit defmstr_type field selects the default mast er type (no default, last access master, fixed default master), whereas the 4-bit fixed_defmstr field selects a fixed default master pro- vided that defmstr_type is set to fixed default master. please refer to the bus matrix user interface description. 8.4.1.1 no default master at the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster suits low-power mode. 8.4.1.2 last access master at the end of the current access, if no other re quest is pending, the slave remains connected to the last master that performed an access request. 8.4.1.3 fixed default master at the end of the current access, if no other r equest is pending, the slave connects to its fixed default master. unlike last access master, the fixed master does not change unless the user modifies it by a software action (field fixed_defmstr of the related scfg). 8.4.2 arbitration the bus matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. one arbiter per hsb slave is provided, thus ar bitrating each slave differently. the bus matrix provides the user with the possibility of choosing between 2 arbitration types for each slave: 1. round-robin arbitration (default) 2. fixed priority arbitration this is selected by the arbt field in the slave configuration registers (scfg). each algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration must be done, specific conditions apply. this is described in ?arbitration rules? . 8.4.2.1 arbitration rules each arbiter has the ability to arbitrate between two or more different master requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. this is described below. 4. slot cycle limit: when the slot cycle counte r has reached the limit value indicating that the current master access is too long and must be broken. this is described below.
68 32099a?avr32?06/09 at32uc3l ? undefined length burst arbitration in order to avoid long slave handling during unde fined length bursts (incr), the bus matrix pro- vides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. infinite: no predicted end of burst is gen erated and therefore i ncr burst transfer will never be broken. 2. one beat bursts: predicted end of burst is generated at each single transfer inside the incp transfer. 3. four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside incr transfer. 4. eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside incr transfer. 5. sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside incr transfer. this selection can be done through the ulbt field in the master configuration registers (mcfg). ? slot cycle limit arbitration the bus matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). at the beginning of the burst access, a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (scfg) and decreased at each clock cycle. when the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, halfword, or word transfer. 8.4.2.2 round-robin arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. if two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner. there are three round-robin algorithms implemented: 1. round-robin arbitration without default master 2. round-robin arbitration with last default master 3. round-robin arbitration with fixed default master ? round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency cycle for the first access of a burst. arbitration without default master can be used for masters that perform significant bursts. ? round-robin arbitration with last default master this is a biased round-robin algorithm used by bus matrix arbiters. it allows the bus matrix to remove the one latency cycle for the last master that accessed the slave. at the end of the cur-
69 32099a?avr32?06/09 at32uc3l rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the acce ss. other non privileged masters still get one latency cycle if they want to access the same slave. this technique can be used for masters that mainly perform sin- gle accesses. ? round-robin arbitration with fixed default master this is another biased round-robin algorithm. it a llows the bus matrix arbiters to remove the one latency cycle for the fixed default master per slav e. at the end of the current access, the slave remains connected to its fixed default master. every request attempted by this fixed default mas- ter will not cause any latency whereas other non privileged masters w ill still get one latency cycle. this technique can be used for masters that mainly perform single accesses. 8.4.2.3 fixed priority arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. if two or more master requests are active at the same time, the master with the highest priority number is serviced first. if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. for each slave, the priority of each master may be defined through the priority registers for slaves (pras and prbs). 8.4.3 slave and master assignation the index number assigned to bus matrix slaves and masters are described in the module con- figuration section at the end of this chapter.
70 32099a?avr32?06/09 at32uc3l 8.5 user interface table 8-1. hmatricx register memory map offset register name access reset value 0x0000 master configuration register 0 mcfg0 read/write 0x00000002 0x0004 master configuration register 1 mcfg1 read/write 0x00000002 0x0008 master configuration register 2 mcfg2 read/write 0x00000002 0x000c master configuration register 3 mcfg3 read/write 0x00000002 0x0010 master configuration register 4 mcfg4 read/write 0x00000002 0x0014 master configuration register 5 mcfg5 read/write 0x00000002 0x0018 master configuration register 6 mcfg6 read/write 0x00000002 0x001c master configuration register 7 mcfg7 read/write 0x00000002 0x0020 master configuration register 8 mcfg8 read/write 0x00000002 0x0024 master configuration register 9 mcfg9 read/write 0x00000002 0x0028 master configuration register 10 mcfg10 read/write 0x00000002 0x002c master configuration regi ster 11 mcfg11 read/write 0x00000002 0x0030 master configuration register 12 mcfg12 read/write 0x00000002 0x0034 master configuration register 13 mcfg13 read/write 0x00000002 0x0038 master configuration register 14 mcfg14 read/write 0x00000002 0x003c master configuration regi ster 15 mcfg15 read/write 0x00000002 0x0040 slave configuration register 0 scfg0 read/write 0x00000010 0x0044 slave configuration register 1 scfg1 read/write 0x00000010 0x0048 slave configuration register 2 scfg2 read/write 0x00000010 0x004c slave configuration register 3 scfg3 read/write 0x00000010 0x0050 slave configuration register 4 scfg4 read/write 0x00000010 0x0054 slave configuration register 5 scfg5 read/write 0x00000010 0x0058 slave configuration register 6 scfg6 read/write 0x00000010 0x005c slave configuration register 7 scfg7 read/write 0x00000010 0x0060 slave configuration register 8 scfg8 read/write 0x00000010 0x0064 slave configuration register 9 scfg9 read/write 0x00000010 0x0068 slave configuration register 10 scfg10 read/write 0x00000010 0x006c slave configuration register 11 scfg11 read/write 0x00000010 0x0070 slave configuration register 12 scfg12 read/write 0x00000010 0x0074 slave configuration register 13 scfg13 read/write 0x00000010 0x0078 slave configuration register 14 scfg14 read/write 0x00000010 0x007c slave configuration register 15 scfg15 read/write 0x00000010 0x0080 priority register a for slave 0 pras0 read/write 0x00000000 0x0084 priority register b for slave 0 prbs0 read/write 0x00000000 0x0088 priority register a for slave 1 pras1 read/write 0x00000000
71 32099a?avr32?06/09 at32uc3l 0x008c priority register b for slave 1 prbs1 read/write 0x00000000 0x0090 priority register a for slave 2 pras2 read/write 0x00000000 0x0094 priority register b for slave 2 prbs2 read/write 0x00000000 0x0098 priority register a for slave 3 pras3 read/write 0x00000000 0x009c priority register b for slave 3 prbs3 read/write 0x00000000 0x00a0 priority register a for slave 4 pras4 read/write 0x00000000 0x00a4 priority register b for slave 4 prbs4 read/write 0x00000000 0x00a8 priority register a for slave 5 pras5 read/write 0x00000000 0x00ac priority register b for slave 5 prbs5 read/write 0x00000000 0x00b0 priority register a for slave 6 pras6 read/write 0x00000000 0x00b4 priority register b for slave 6 prbs6 read/write 0x00000000 0x00b8 priority register a for slave 7 pras7 read/write 0x00000000 0x00bc priority register b for slave 7 prbs7 read/write 0x00000000 0x00c0 priority register a for slave 8 pras8 read/write 0x00000000 0x00c4 priority register b for slave 8 prbs8 read/write 0x00000000 0x00c8 priority register a for slave 9 pras9 read/write 0x00000000 0x00cc priority register b for slave 9 prbs9 read/write 0x00000000 0x00d0 priority register a for slave 10 pras10 read/write 0x00000000 0x00d4 priority register b for slave 10 prbs10 read/write 0x00000000 0x00d8 priority register a for slave 11 pras11 read/write 0x00000000 0x00dc priority register b for slave 11 prbs11 read/write 0x00000000 0x00e0 priority register a for slave 12 pras12 read/write 0x00000000 0x00e4 priority register b for slave 12 prbs12 read/write 0x00000000 0x00e8 priority register a for slave 13 pras13 read/write 0x00000000 0x00ec priority register b for slave 13 prbs13 read/write 0x00000000 0x00f0 priority register a for slave 14 pras14 read/write 0x00000000 0x00f4 priority register b for slave 14 prbs14 read/write 0x00000000 0x00f8 priority register a for slave 15 pras15 read/write 0x00000000 0x00fc priority register b for slave 15 prbs15 read/write 0x00000000 0x0110 special function register 0 sfr0 read/write ? 0x0114 special function register 1 sfr1 read/write ? 0x0118 special function register 2 sfr2 read/write ? 0x011c special function register 3 sfr3 read/write ? 0x0120 special function register 4 sfr4 read/write ? 0x0124 special function register 5 sfr5 read/write ? 0x0128 special function register 6 sfr6 read/write ? table 8-1. hmatricx register memory map (continued) offset register name access reset value
72 32099a?avr32?06/09 at32uc3l 0x012c special function register 7 sfr7 read/write ? 0x0130 special function register 8 sfr8 read/write ? 0x0134 special function register 9 sfr9 read/write ? 0x0138 special function register 10 sfr10 read/write ? 0x013c special function register 11 sfr11 read/write ? 0x0140 special function register 12 sfr12 read/write ? 0x0144 special function register 13 sfr13 read/write ? 0x0148 special function register 14 sfr14 read/write ? 0x014c special function register 15 sfr15 read/write ? table 8-1. hmatricx register memory map (continued) offset register name access reset value
73 32099a?avr32?06/09 at32uc3l 8.5.1 master configuration registers name: mcfg0...mcfg15 access type: read/write offset: 0x00 - 0x3c reset value: 0x00000002 ? ulbt: undefined length burst type 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? ulbt table 8-2. undefined length burst type ulbt undefined length burst type description 000 inifinite length burst no predicted end of burst is generated and theref ore incr bursts coming from this master cannot be broken. 001 single-access the undefined length burst is treated as a succession of single accesses, allowing re- arbitration at each beat of the incr burst. 010 4 beat burst the undefined length bu rst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. 011 8 beat burst the undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. 100 16 beat burst the undefined length burst is split in to a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end.
74 32099a?avr32?06/09 at32uc3l 8.5.2 slave configuration registers name: scfg0...scfg15 access type: read/write offset: 0x40 - 0x7c reset value: 0x00000010 ? arbt: arbitration type 0: round-robin arbitration 1: fixed priority arbitration ? fixed_defmstr: fixed default master this is the number of the default master for this slave. only used if defmstr_type is 2. sp ecifying the number of a master which is not connected to the selected slave is equivalent to sett ing defmstr_type to 0. ? defmstr_type: default master type 0: no default master at the end of the current slave access, if no other master r equest is pending, the slave is disconnected from all masters. this results in a one cycle latenc y for the first access of a burst transfer or for a single access. 1: last default master at the end of the current slave access, if no other master req uest is pending, the slave stays connected to the last master hav ing accessed it. this results in not having one cycle latency when the last master tries to access the slave again. 2: fixed default master at the end of the current slave access, if no other master request is pending, the slav e connects to the fixed master the numbe r that has been written in the fixed_defmstr field. this results in not having one cycle latency when the fixed master tries to access the slave again. ? slot_cycle: maximum number of allowed cycles for a burst when the slot_cycle limit is reached for a burst, it may be broken by another master trying to access this slave. this limit has been placed to avoid locking a very slow slave when very long bursts are used. this limit must not be very small. unreas onably small values break every burst and the bus matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for slot_cycle. 31 30 29 28 27 26 25 24 ???????arbt 23 22 21 20 19 18 17 16 ? ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle
75 32099a?avr32?06/09 at32uc3l 8.5.3 bus matrix priority registers a for slaves register name: pras0...pras15 access type: read/write offset: - reset value: 0x00000000 ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 m7pr m6pr 23 22 21 20 19 18 17 16 m5pr m4pr 15 14 13 12 11 10 9 8 m3pr m2pr 76543210 m1pr m0pr
76 32099a?avr32?06/09 at32uc3l 8.5.4 priority registers b for slaves name: prbs0...prbs15 access type: read/write offset: - reset value: 0x00000000 ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 m15pr m14pr 23 22 21 20 19 18 17 16 m13pr m12pr 15 14 13 12 11 10 9 8 m11pr m10pr 76543210 m9pr m8pr
77 32099a?avr32?06/09 at32uc3l 8.5.5 special function registers name: sfr0...sfr15 access type: read/write offset: 0x110 - 0x14c reset value: - ? sfr: special function register fields those registers are not a hmatrix spec ific register. the field of those will be defined where they are used. 31 30 29 28 27 26 25 24 sfr 23 22 21 20 19 18 17 16 sfr 15 14 13 12 11 10 9 8 sfr 76543210 sfr
78 32099a?avr32?06/09 at32uc3l 8.6 module configuration 8.6.1 bus matrix connections the bus matrix has the several masters and slaves. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. the master number in the table below can be used to index the hmatrix cont rol registers. for example, hmatrix mcfg0 register is associated with the cpu data master interface. each slave has its own arbiter, thus allowing a different arbitration per slave. the slave number in the table below can be used to index the hmatrix control registers. for example, scfg3 is associated with the internal sram slave interface. accesses to unused areas returns an error result to the master requesting such an access. table 8-3. high speed bus masters master 0 cpu data master 1 cpu instruction master 2 cpu sab master 3 pdca master 4 sau table 8-4. high speed bus slaves slave 0 internal flash slave 1 hsb-pb bridge 0 slave 2 hsb-pb bridge 1 slave 3 internal sram slave 4 sau
79 32099a?avr32?06/09 at32uc3l figure 8-1. hmatrix master / slave connections cpu data 0 cpu instruction 1 cpu sab 2 pdca 3 internal flash 0 hsb-pb bridge 0 1 hsb-pb bridge 1 2 internal sram 3 hmatrix slaves hmatrix masters sau 4 sau 4
80 32099a?avr32?06/09 at32uc3l 9. secure access unit (sau) rev 1.1.0.0 9.1 features ? remaps registers in memory regions protected by the mpu to regions not protected by the mpu ? programmable physical address for each channel ? two modes of operation: locked and open ? in locked mode, access to a channel must be preceded by an unlock action ? an unlocked channel remains op en only for a specific amount of time, if no access is performed during this time, the channel is relocked ? only one channel can be open at a time, op ening a channel while another one is open locks the first one ? access to a locked channel is denied, a bus error and optionally an interrupt is returned ? if a channel is relocked due to an unlock timeout, an interrupt can optionally be generated ? in open mode, all channels are permanently unlocked 9.2 overview in many systems, erroneous access to peripherals can lead to catastrophic failure. an exam- ple of such a peripheral is the pulse width modulator (pwm) used to control electric motors. the pwm outputs a pulse train that controls the motor. if the control registers of the pwm module are inadvertently updated with wrong values, the motor can start operating out of con- trol, possibly causing damage to the application and the surrounding environment. however, sometimes the pwm control registers must be updated with new values, for example when modifying the pulse train to accelerate the mo tor. a mechanism must be used to protect the pwm control registers from inadvertent access caused by for example: ? errors in the software code ? transient errors in the cpu caused by for ex ample electrical noise altering the execution path of the program to improve the security in a computer system, the avr32uc3 implements a memory protec- tion unit (mpu). the mpu can be set up to li mit the accesses that can be performed to specific memory addresses. the mpu divides t he memory space into regions, and assigns a set of access restrictions on each region. access restrictions can for example be read/write if the cpu is in supervisor mode, and read-only if the cpu is in application mode. the regions can be of different size, but each region is usually quite large, e.g. protecting 1 kilobyte of address space or more. furthermore, access to each region is often controlled by the execu- tion state of the cpu, i.e. supervisor or application mode. such a simple control mechanism is often too inflexible (too coarse-grained chunks) and with too much overhead (often requiring system calls to access protected memory locati ons) for simple or real-time systems such as embedded microcontrollers. usually, the secure access unit (sau) is used together with the mpu to provide the required security and integrity. the mpu is set up to protect regions of memory, while the sau is set up to provide a secure channel into specific memo ry locations that are protected by the mpu. these specific locations can be thought of as fine-grained overrides of the general coarse- grained protection provided by the mpu.
81 32099a?avr32?06/09 at32uc3l 9.3 block diagram figure 9-1 presents the sau integrated in an example system with a cpu, some memories, some peripherals, and a bus system. the sau is connected to both the peripheral bus (pb) and the high speed bus (hsb). configuration of the sau is done via the pb, while memory accesses are done via the hsb. the sau rece ives an access on its hsb slave interface, remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its hsb master interface to the remapped address. the thin arrows in figure 9-1 exemplifies control flow when using the sau. the cpu wants to read the rx buffer in the usart. the mpu has been configured to protect all registers in the usart from user mode access, while the sau has been configured to remap the rx buffer into a memory space that is not protected by the mpu. this unprotected memory space is mapped into the sau hsb slave space. when th e cpu reads the appropriate address in the sau, the sau will perform an access to the desired rx buffer register in the usart, and thereafter return the read results to the cpu. the return data flow will follow the opposite direction of the control flow arrows in figure 9-1 . figure 9-1. sau block diagram sau channel bus master mpu cpu bus slave usart pwm bus slave bus master bus slave flash bus slave ram bus bridge sau configuration interrupt request high speed bus sau peripheral bus
82 32099a?avr32?06/09 at32uc3l 9.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 9.4.1 power management if the cpu enters a sleep mode that disables clocks used by the sau, the sau will stop func- tioning and resume operation after the system wakes up from sleep mode. 9.4.2 clocks the sau has two bus clocks connected: one high speed bus clock (clk_sau_hsb) and one peripheral bus clock (clk_sau_pb). t hese clocks are generated by the power man- ager. both clocks are enabled at reset, and can be disabled by writing to the power manager. the user has to ensure that clk_sau_hsb is not turned off before accessing the sau. like- wise, the user must ensure that no bus access is pending in the sau before disabling clk_sau_hsb. failing to do so ma y deadlock the high speed bus. 9.4.3 interrupt the sau interrupt request line is connected to th e interrupt controller. using the sau interrupt requires the interrupt controller to be programmed first. 9.4.4 debug operation when an external debugger forces the cpu into debug mode, the sau continues normal operation. if the sau is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 9.5 functional description 9.5.1 enabling the sau the sau is enabled by writing a one to the enable (en) bit in the control register (cr). this will set the sau enabled (en) bit in the status register (sr). 9.5.2 configuring the sau channels the sau has a set of channels, mapped in the hsb memory space. these channels can be configured by a remap target register (rtr), located at the same memory address. when the sau is in normal mode, the sau channel is addressed, and when the sau is in setup mode, the rtr can be addressed. before the sau can be used, the channels must be configured and enabled. to configure a channel, the corresponding rtr must be programmed with the remap target address. to do this, make sure the sau is in setup mode by writing a one to the setup mode enable (sen) bit in cr. this makes sure that a write to the rtr address accesses the rtr, not the sau chan- nel. thereafter, the rtr is written with the address to remap to, typically the address of a specific pb register. when all channels have been configured, return to normal mode by writ- ing a one to the setup mode disable (sdi s) in cr. the channels can now be enabled by writing ones to the corresponding bits in the channel enable registers (cerh/l). the sau is only able to remap addresses above 0xfffc0000.
83 32099a?avr32?06/09 at32uc3l 9.5.2.1 protecting sau configuration registers in order to prevent the sau configuration re gisters to be changed by malicious or runaway code, they should be protected by the mpu as soon as they have been configured. maximum security is provided in the system if program memory does not contain any code to unprotect the configuration registers in the mpu. this guarantees that runaway code can not acciden- tally unprotect and thereafter change the sau configuration registers. 9.5.3 lock mechanism the sau can be configured to use two different access mechanisms: open and locked. in open mode, sau channels can be accessed freely after they have been configured and enabled. in order to prevent accidental accesses to remapped addresses, it is possible to con- figure the sau in locked mode. writing a one to the open mode bit in the config register (config.open) will enable open mode. writin g a zero to config.open will enable locked mode. when using locked mode, the lock mechanism mu st be configured by writing a user defined key value to the unlock key (ukey) field in the configuration register (config). the num- ber of clk_sau_hsb cycles the channel remains unlocked must be written to the unlock number of clock cycles (ucyc) field in config. access control to the sau channels is enabled by means of the unlock register (ur), which resides in the same address space as the sau channels. before a channel can be accessed, the unlock key value must be written to ur.key, and the channel number to ur.channel. access to the channel is then permitted for the next config.ucyc clock cycles, or until a successful access to the unlocked channel has been made. only one channel can be unlocked at a time. if an y other channel is unlocked at the time of writing ur, this channel will be automatically lo cked before the channel addressed by the ur write is unlocked. an attempted access to a locked channel will be aborted, and the channel access unsuc- cessful bit (sr.cau) will be set. any pending errors bits in sr must be cleared be fore it is possible to access ur. the follow- ing sr bits are defined as error bits : exp, cau, urread, urkey, ures, mberror, rtradr. if any of these bits are set while writing to ur, the write is aborted and the unlock register error status (ures) bit in sr is set. 9.5.4 normal operation the following sequence must be used in order to access a sau channel in normal operation (cr.sen=0): 1. if not in open mode, write the unlock key to ur.key and the channel number to ur.channel. 2. perform the read or write operation to the sau channel. if not in open mode, this must be done within config.ucyc clock cycles of unlocking the channel. the sau will use its hsb master interface to remap th e access to the target address pointed to by the corresponding rtr. 3. to confirm that the access was successful, wait for the idle transfer status bit (sr.idle) to indicate the operation is completed. then check sr for possible error conditions. the sau can be configured to generate interrupt requests or a bus error exception if the access failed.
84 32099a?avr32?06/09 at32uc3l 9.5.4.1 operation example figure 9-2 shows a typical memory map, consisting of some memories, some simple peripher- als, and a sau with multiple channels and an unlock register (ur). imagine that the mpu has been set up to disallow all accesses from the cpu to the grey modules. thus the cpu has no way of accessing for example the transmit holding register in the uart, present on address x on the bus. note that the sau rtrs are not protected by the mpu, thus the rtrs can be accessed. if for example rtr0 is configured to point to address x, an access to rtr0 will be remapped by the sau to address x acco rding to the algorith m presented above. by programming the sau rtrs, specific addresse s in modules that have generally been pro- tected by the mpu can be performed. figure 9-2. example memory map for a system with sau 9.5.5 interrupts the sau can generate an interrupt request to si gnal different events. all events that can gen- erate an interrupt request have dedicated bits in the status register (sr). an interrupt request will be generated if the corresponding bit in the interrupt mask register (imr) is set. bits in imr are set by writing a one to the corresponding bit in the interrupt enable register (ier), and cleared by writing a one to the corresponding bit in the interrupt disable register (idr). the interrupt request remains active until the co rresponding bit in sr is cleared by writing a one to the corresponding bit in the interrupt clear register (icr). the following sr bits are used for si gnalling the result of sau accesses: ? rtr address error (rtradr) is set if an ille gal address is written to the rtrs. only addresses in the range 0xfffc0000-0xffffffff are allowed. ? master interface bus error (mberror) is set if any of the conditions listed in section 9.5.7 occurred. transmit holding baudrate control receive holding channel 1 rtr0 rtr1 address x address z uart sau config sau channel ur rtr62 ...
85 32099a?avr32?06/09 at32uc3l ? unlock register error status (ures) is set if an attempt was made to unlock a channel by writing to the unlock regist er while one or more error bits in sr were set (see section 9.5.6 ). the unlock operation was aborted. ? unlock register key error (urkey) is set if th e unlock register was attempted written with an invalid key. ? unlock register read (urread) is set if the unlock register was attempted read. ? channel access unsuccessful (cau) is set if the channel access was unsuccessful. ? channel access successful (cas) is set if the channel access was successful. ? channel unlock expired (exp) is set if the channel lock expired, with no channel being accessed after the channel was unlocked. 9.5.6 error bits if error bits are set when attempting to un lock a channel, sr.ures will be set. the following sr bits are considered error bits: ? exp ?cau ? urread ? urkey ?ures ? mberror ?rtradr 9.5.7 bus error responses by writing a one to the bus error response e nable bit (cr.berren), serious access errors will be configured to return a bu s error to the cpu. this will cause the cpu to execute its bus error data fetch exception routine. the conditions that can generate a bus error response are: ? reading the unlock register ? trying to access a locked channel ? the sau hsb master receiving a bus error response from its addressed slave 9.5.8 disabling the sau to disable the sau, the user must first ensure that no sau bus operations are pending. this can be done by checking that the status.idle bit is set. the sau may then be disabled by writing a one to the disable (dis) bit in cr.
86 32099a?avr32?06/09 at32uc3l 9.6 user interface the following addresses are used by sau channel configuration r egisters. all offsets are relative to the sau?s pb base address. note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. the following addresses are used by sau channel registers. a ll offsets are relative to the sau?s hsb base address. the number of channels implemented is device specific, refer to the module configuration section at the end of this chapter. table 9-1. sau configuration re gister memory map offset register register name access reset 0x00 control register cr write-only 0x00000000 0x04 configuration register config write-only 0x00000000 0x08 channel enable register high cerh read/write 0x00000000 0x0c channel enable register low cerl read/write 0x00000000 0x10 status register sr read-only 0x00000000 0x14 interrupt enable register ier write-only 0x00000000 0x18 interrupt disable register idr write-only 0x00000000 0x1c interrupt mask register imr read-only 0x00000000 0x20 interrupt clear register icr write-only 0x00000000 0x24 parameter register parameter read-only - (1) 0x28 version register version read-only - (1) table 9-2. sau channel register memory map offset register register name access reset 0x00 remap target register 0 rtr0 read/write n/a 0x04 remap target register 1 rtr1 read/write n/a 0x08 remap target register 2 rtr2 read/write n/a ... ... ... ... ... 0x04*n remap target register n rtrn read/write n/a 0xfc unlock register ur write-only n/a
87 32099a?avr32?06/09 at32uc3l 9.6.1 control register name: cr access type: write-only offset: 0x00 reset value: 0x00000000 ? berrdis: bus error response disable writing a zero to this bit has no effect. writing a one to this bit disables bus error response from the sau. ? berren: bus error response enable writing a zero to this bit has no effect. writing a one to this bit enables bus error response from the sau. ? sdis: setup mode disable writing a zero to this bit has no effect. writing a one to this bit exits setup mode. ? sen: setup mode enable writing a zero to this bit has no effect. writing a one to this bit enters setup mode. ? dis: sau disable writing a zero to this bit has no effect. writing a one to this bit disables the sau. ? en: sau enable writing a zero to this bit has no effect. writing a one to this bit enables the sau. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - berrdis berren sdis sen dis en
88 32099a?avr32?06/09 at32uc3l 9.6.2 configuration register name: config access type: write-only offset: 0x04 reset value: 0x00000000 ? ucyc: unlock number of clock cycles once a channel has been unlocked, it remains unlocked for this amount of clk_sau_hsb clock cycles or until one access to a channel has been made. ? ukey: unlock key the value in this register must be written into ur.key to unlock a channel. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ucyc 76543210 ukey
89 32099a?avr32?06/09 at32uc3l 9.6.3 channel enable register high name: cerh access type: read/write offset: 0x08 reset value: 0x00000000 ? cerh[n]: channel enable register high 0: channel (n+32) is not enabled. 1: channel (n+32) is enabled. 31 30 29 28 27 26 25 24 cerh[24:30] 23 22 21 20 19 18 17 16 cerh[23:16] 15 14 13 12 11 10 9 8 cerh[15:8] 76543210 cerh[7:0]
90 32099a?avr32?06/09 at32uc3l 9.6.4 channel enable register low name: cerl access type: read/write offset: 0x0c reset value: 0x00000000 ? cerl[n]: channel enable register low 0: channel n is not enabled. 1: channel n is enabled. 31 30 29 28 27 26 25 24 cerl[31:24] 23 22 21 20 19 18 17 16 cerl[23:16] 15 14 13 12 11 10 9 8 cerl[15:8] 76543210 cerl[7:0]
91 32099a?avr32?06/09 at32uc3l 9.6.5 status register name: sr access type: read-only offset: 0x10 reset value: 0x00000000 ? sen: sau setup mode enable this bit is cleared when the sau exits setup mode. this bit is set when th e sau enters setup mode. ? en: sau enabled this bit is cleared when the sau is disabled. this bit is set when the sau is enabled. ? rtradr: rtr address error this bit is cleared when the corresponding bit in icr is written to one. this bit is set if, in the configuration phase, an rtr was wr itten with an illegal address, i.e. the upper 16 bits in the addre ss were different from 0xfffc, 0xfffd, 0xfffe or 0xffff. ? mberror: master interface bus error this bit is cleared when the corresponding bit in icr is written to one. this bit is set if a channel access generated a transfer on the master interface that received a bus error response from the addressed slave. ? ures: unlock register error status this bit is cleared when the corresponding bit in icr is written to one. this bit is set if an attempt was made to unlock a channel by writing to the unlock register while one or more error bits were set in sr. the unlock operation was aborted. ? urkey: unlock register key error this bit is cleared when the corresponding bit in icr is written to one. this bit is set if the unlock register was attempted written with an invalid key. ? urread: unlock register read this bit is cleared when the corresponding bit in icr is written to one. this bit is set if the unlock register was read. ? cau: channel access unsuccessful this bit is cleared when the corresponding bit in icr is written to one. this bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------senen 76543210 rtradr mberror ures urkey urread cau cas exp
92 32099a?avr32?06/09 at32uc3l ? cas: channel access successful this bit is cleared when the corresponding bit in icr is written to one. this bit is set if channel access successful, i.e. one access was made after the channel was unlocked. ? exp: channel unlock expired this bit is cleared when the corresponding bit in icr is written to one. this bit is set if channel unlock has expired, i.e. no access being made after the channel was unlocked.
93 32099a?avr32?06/09 at32uc3l 9.6.6 interrupt enable register name: ier access type: write-only offset: 0x14 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rtradr mberror ures urkey urread cau cas exp
94 32099a?avr32?06/09 at32uc3l 9.6.7 interrupt disable register name: idr access type: write-only offset: 0x18 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rtradr mberror ures urkey urread cau cas exp
95 32099a?avr32?06/09 at32uc3l 9.6.8 interrupt mask register name: imr access type: read-only offset: 0x1c reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rtradr mberror ures urkey urread cau cas exp
96 32099a?avr32?06/09 at32uc3l 9.6.9 interrupt clear register name: icr access type: write-only offset: 0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and any corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rtradr mberror ures urkey urread cau cas exp
97 32099a?avr32?06/09 at32uc3l 9.6.10 parameter register name: parameter access type: read-only offset: 0x24 reset value: - ? channels: number of channels implemented 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - channels
98 32099a?avr32?06/09 at32uc3l 9.6.11 version register name: version access type: write-only offset: 0x28 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
99 32099a?avr32?06/09 at32uc3l 9.6.12 remap target register n name: rtrn access type: read/write offset: n*4 reset value: 0x00000000 ? rtr: remap target address for channel n rtr[31:16] must have one of the following values, any other value will result in undefined behavior: 0xfffc 0xfffd 0xfffe 0xffff rtr[1:0] must be written to 0, any othe r value will result in undefined behavior. 31 30 29 28 27 26 25 24 rtr[31:24] 23 22 21 20 19 18 17 16 rtr[23:16] 15 14 13 12 11 10 9 8 rtr[15:8] 76543210 rtr[7:0]
100 32099a?avr32?06/09 at32uc3l 9.6.13 unlock register name: ur access type : write-only offset: 0xfc reset value: 0x00000000 ?key the correct key must be written in order to unlock a channel. the key value written must correspond to the key value defined in config.ukey. ? channel number of the channel to unlock. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 key 76543210 - - channel
101 32099a?avr32?06/09 at32uc3l
102 32099a?avr32?06/09 at32uc3l
103 32099a?avr32?06/09 at32uc3l 9.7 module configuration the specific configuratio n for each sau instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 9-3. module configuration feature sau sau channels 16 table 9-4. module clock name module name clock name sau clk_sau_hsb sau clk_sau_pb table 9-5. register reset values register reset value version 0x00000110 parameter 0x00000010
104 32099a?avr32?06/09 at32uc3l 10. peripheral dma controller (pdca) rev: 1.2.2.0 10.1 features ? multiple channels ? generates transfers to/from peripherals such as usartand spi ? two address pointers/counters per ch annel allowing double buffering ? performance monitors to measure average and maximum transfer latency ? optional synchronizing of data transfers with extenal peripheral events ? ring buffer functionality 10.2 overview the peripheral dma controller (pdca) transfers data between on-chip peripheral modules such as usart, spi and memories (those memories ma y be on- and off-chip memories). using the pdca avoids cpu intervention for data transfers, improving the performance of the microcon- troller. the pdca can transfer data from memory to a peripheral or from a peripheral to memory. the pdca consists of multiple dma channels. each channel has: ? a peripheral select register ? a 32-bit memory pointer ? a 16-bit transfer counter ? a 32-bit memory pointer reload value ? a 16-bit transfer counter reload value the pdca communicates with the peripheral modules over a set of handshake interfaces. the peripheral signals the pdca when it is ready to receive or transmit data. the pdca acknowl- edges the request when the transmission has started. when a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be generated.
105 32099a?avr32?06/09 at32uc3l 10.3 block diagram figure 10-1. pdca block diagram 10.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 power management if the cpu enters a sleep mode that disables the pdca clocks, the pdca will stop functioning and resume operation after the system wakes up from sleep mode. 10.4.2 clocks the pdca has two bus clocks connected: one high speed bus clock (clk_pdca_hsb) and one peripheral bus clock (clk_pdca_pb). thes e clocks are generated by the power man- ager. both clocks are enabled at reset, and can be disabled by wr iting to the power manager. it is recommended to disable the pdca before disa bling the clocks, to avoid freezing the pdca in an undefined state. 10.4.3 interrupts the pdca interrupt request lines are connected to the interrupt controller. using the pdca interrupts requires the interrupt controller to be programmed first. hsb to pb bridge peripheral dma controller (pdca) peripheral 0 high speed bus matrix handshake interfaces peripheral bus irq hsb hsb interrupt controller peripheral 1 peripheral 2 peripheral (n-1) ...
106 32099a?avr32?06/09 at32uc3l 10.4.4 peripheral events the pdca peripheral events are connected via the peripheral event system. refer to the peripheral event system chapter for details. 10.5 functional description 10.5.1 basic operation the pdca consists of multiple independent pdca channels, each capable of handling dma requests in parallel. each pdca channels contains a set of configuration registers which must be configured to start a dma transfer. in this section the steps necessary to configure one pdca channel is outlined. the peripheral to transfer data to or from must be configured correctly in the peripheral select register (psr). this is performed by writing the peripheral identity (pid) value for the corre- sponding peripheral to the pid field in the ps r register. the pid also encodes the transfer direction, i.e. memory to peripheral or peripheral to memory. see section 10.5.6 . the transfer size must be written to the transfer size field in the mode register (mr.size). the size must match the data size produced or consumed by the selected peripheral. see section 10.5.7 . the memory address to transfer to or from, depending on the psr, must be written to the mem- ory address register (mar). for each transfer the memory address is increased by either a one, two or four, depending on the size set in mr. see section 10.5.2 . the number of data items to transfer is written to the tcr register. if the pdca channel is enabled, a transfer will start imm ediately after writing a non-zero value to tc r or the reload ver- sion of tcr, tcrr. after each transfer the tcr value is decreased by one. both mar and tcr can be read while the pdca channel is active to monitor the dma progress. see section 10.5.3 . the channel must be enabled for a transfer to start. a channel is enable by writing a one to the en bit in the control register (cr). 10.5.2 memory pointer each channel has a 32-bit memory address regi ster (mar). this register holds the memory address for the next transfer to be performed. the register is automatically updated after each transfer. the address will be increa sed by either one, two or four depending on the size of the dma transfer (byte, halfword or word). the mar can be read at any time during transfer. 10.5.3 transfer counter each channel has a 16-bit transfer counter register (tcr). this register must be programmed with the number of transfers to be performed. the tcr register should contain the number of data items to be transferred independently of the transfer size. the tcr can be read at any time during transfer to see the number of remaining transfers. 10.5.4 reload registers both the mar and the tcr have a reload regist er, respectively memory address reload regis- ter (marr) and transfer counter reload register (tcrr). these registers provide the possibility for the pdca to work on two memory buffer s for each channel. when one buffer has completed, mar and tcr will be re loaded with the values in marr and tcrr. the reload logic is always enabled and will trigge r if the tcr reaches zero while tcrr holds a non-zero value.
107 32099a?avr32?06/09 at32uc3l if tcr is zero when writing to tcrr, the tcr and mar are automatically updated with the value written in tcrr and marr. 10.5.5 ring buffer when ring buffer mode is enabled the tcrr and marr regi sters will not be cleared when tcr and mar registers reload. th is allows the pdca to read or write to the same memory region over and over again until the transfer is actively stopped by the user. ring buffer mode is enabled by writing a one to the ring buffer bit in the mode register (mr.ring). 10.5.6 peripheral selection the peripheral select register (psr) decides which peripheral should be connected to the pdca channel. a peripheral is selected by writing the corresponding peripheral identity (pid) to the pid field in the pst register . writing the pid will both select the direction of the transfer (memory to peripheral or peripheral to memory ), which handshake interface to use, and the address of the peripheral holding register. refer to the peripheral identity (pid) table in the mod- ule configuration section for the peripheral pid values. 10.5.7 transfer size the transfer size can be set individually for each channel to be either byte, halfword or word (8- bit, 16-bit or 32-bit respectively). transfer size is set by writing the desired value to the transfer size field in the mode register (mr.size). when the pdca moves data between peripherals and memory, data is automatically sized and aligned. when memory is accessed, the size specified in mr.size and system alignment is used. when a peripheral register is accessed t he data to be transferred is converted to a word where bit n in the data corresponds to bit n in the peripheral register. if the transfer size is byte or halfword, bits greater than 8 and16 respectively are set to zero. refer to the module configuration section for information regarding what peripheral registers are used for the differen peripherals and then to the peripheral specific chapter for information about the size option available for the different registers. 10.5.8 enabling and disabling each dma channel is enabled by writing a one to the transfer enable bit in the control register (cr.ten) and disabled by writing a one to the transfer disable bit (cr.tdis). the current sta- tus can be read from the status register (sr). while the pdca channel is enabled all dma re quest will be handled as long the tcr and tcrr is not zero. 10.5.9 interrupts interrupts can be enabled by writing a one to the corresponding bit in the interrupt enable regis- ter (ier) and disabled by writing a one to the corresponding bit in the interrupt disable register (idr). the interrupt mask register (imr) can be read to see whether an interrupt is enabled or not. the current status of an interrupt source can be read through the interrupt status register (isr). the pdca has three interrupt sources: ? reload counter zero - the tcrr register is zero. ? transfer finished - both the tcr and tcrr registers are zero. ? transfer error - an error has occurred in accessing memory.
108 32099a?avr32?06/09 at32uc3l 10.5.10 priority if more than one pdca channel is requesting transfer at a given time, the pdca channels are prioritized by their channel number. channels wi th lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 10.5.11 error handling if the memory address register (mar) is set to point to an invalid location in memory, an error will occur when the pdca tries to perform a transfer. when an error occurs, the transfer error bit in the interrup t status register (isr.terr) will be se t and the dma channel that caused the error will be stopped. in order to restart the channel, the user must program the memory address register to a valid address and then write a one to the error clear bit in the control register (cr.eclr). if the transfer error interrupt is enabled , an interrupt request will be gener- ated when an transfer error occurs. 10.5.12 peripheral event trigger peripheral events can be used to trigger pdca channel transfers. peripheral event synchroniza- tions are enabled by writing a one to the event trigger bit in the mode register (mr.etrig). when set, all dma requests will be blocked until an peripheral event is received. for each peripheral event received, only one data item is transferred. if no dma requests are pending when a peripheral event is received, the pdca w ill start a transfer as so on as a peripheral event is detected. if multiple events arrive while the pdca channel is busy transferring data, an over- flow condition will be signaled in the peripheral event system. refer to the peripheral event system chapter for more information. 10.6 performance monitors two performance monitors allow the user to m easure the activity and stall cycles for pdca transfers. to monitor a pdca channel, the corresponding channel number must be written to one of the monnch fields in the performance control register (pcontrol) and a one must be written to the corresponding chnen bit in the same register. due to performance monitor hardware resource sharing, the two monitor channels should not be programmed to monitor the same pdca channel. this may result in undefined perfor- mance monitor behavior. 10.6.1 measuring mechanisms three different parameters can be measured by each channel: ? the number of data transfer cycles since last channel reset, both for read and write ? the number of stall cycles since last channel reset, both for read and write ? the maximum latency since last channel reset, both for read and write these measurements can be extracted by soft ware and used to generate indicators for bus latency, bus load, and maximum bus latency. each of the counters has a fixed width, and may therefore overflow. when an overflow is encountered in either the performance channel data read/write cycle registers (prdatan and pwdatan) or the performance channel read/write stall cycles registers (prstalln and pwstalln) of a channel, all registers in the channel are reset. this behavior is altered if the channel overflow freeze bit is one in the performance control register (pcontrol.chnovf). if this bit is one, the channel registers are fr ozen when either data or stall reaches its maxi- mum value. this simplifies one-shot readout of the counter values.
109 32099a?avr32?06/09 at32uc3l the registers can also be manually reset by writing a one to the channel reset bit in the pcon- trol register (pcontrol.chnres). the performance channel read/write latency registers (prlatn and pwlatn) are saturating when their maximum count value is reached. the prlatn and pwlatn registers are rese t only by writing a one to the chnres in pcontrol. a counter must manually be enabled by writing a one to the channel enable bit in the perfor- mance control register (pcontrol.chnen).
110 32099a?avr32?06/09 at32uc3l 10.7 user interface 10.7.1 memory map overview 10.7.2 channel memory map 10.7.3 performance monitor memory map table 10-1. pdca register memory map address range contents 0x000 - 0x03f dma channel 0 configuration registers 0x040 - 0x07f dma channel 1 configuration registers ... ... (0x000 - 0x03f)+m*0x040 dma channel m configuration registers 0x800-0x830 performance monitor registers 0x834 version register table 10-2. pdca channel configuration registers offset register register name access reset 0x000 + n*0x040 memory address register mar read/write 0x00000000 0x004 + n*0x040 peripheral select register psr read/write - (1) 0x008 + n*0x040 transfer counter register tcr read/write 0x00000000 0x00c + n*0x040 memory address reload register marr read/write 0x00000000 0x010 + n*0x040 transfer counter reload register tcrr read/write 0x00000000 0x014 + n*0x040 control register cr write-only 0x00000000 0x018 + n*0x040 mode register mr read/write 0x00000000 0x01c + n*0x040 status register sr read-only 0x00000000 0x020 + n*0x040 interrupt enable register ier write-only 0x00000000 0x024 + n*0x040 interrupt disable register idr write-only 0x00000000 0x028 + n*0x040 interrupt mask register imr read-only 0x00000000 0x02c + n*0x040 interrupt status register isr read-only 0x00000000 table 10-3. pdca performance monitor registers offset register register name access reset 0x800 performance control register pcontrol read/write 0x00000000 0x804 channel0 read data cycles prdata0 read-only 0x00000000 0x808 channel0 read stall cycles prstall0 read-only 0x00000000 0x80c channel0 read max latency prlat0 read-only 0x00000000 0x810 channel0 write data cycles pwdata0 read-only 0x00000000 0x814 channel0 write stall cycles pwstall0 read-only 0x00000000 0x818 channel0 write max latency pwlat0 read-only 0x00000000
111 32099a?avr32?06/09 at32uc3l 10.7.4 version register memory map note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. 0x81c channel1 read data cycles prdata1 read-only 0x00000000 0x820 channel1 read stall cycles prstall1 read-only 0x00000000 0x824 channel1 read max latency prlat1 read-only 0x00000000 0x828 channel1 write data cycles pwdata1 read-only 0x00000000 0x82c channel1 write stall cycles pwstall1 read-only 0x00000000 0x830 channel1 write max latency pwlat1 read-only 0x00000000 table 10-4. pdca version register memory map offset register register name access reset 0x834 version register version read-only - (1) table 10-3. pdca performance monitor registers offset register register name access reset
112 32099a?avr32?06/09 at32uc3l 10.7.5 memory address register name: mar access type: read/write offset: 0x000 + n*0x040 reset value: 0x00000000 ? maddr: memory address address of memory buffer. maddr should be programmed to poin t to the start of the memory buffer when configuring the pdca. during transfer, maddr will point to the next memory location to be read/written. 31 30 29 28 27 26 25 24 maddr[31:24] 23 22 21 20 19 18 17 16 maddr[23:16] 15 14 13 12 11 10 9 8 maddr[15:8] 76543210 maddr[7:0]
113 32099a?avr32?06/09 at32uc3l 10.7.6 peripheral select register name: psr access type: read/write offset: 0x004 + n*0x040 reset value: - ? pid: peripheral identifier the peripheral identifier selects which peripheral should be con nected to the dma channel. writ ing a pid will select both which handshake interface to use, the direction of the transfer and also the address of the receive/transfer holding register for the peripheral. see the module configuration section of pdca for detai ls. the width of the pid field is device specific and depende nt on the number of peripheral modules in the device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 pid
114 32099a?avr32?06/09 at32uc3l 10.7.7 transfer counter register name: tcr access type: read/write offset: 0x008 + n*0x040 reset value: 0x00000000 ? tcv: transfer counter value number of data items to be transferred by the pdca. tcv must be programmed with the total number of transfers to be made. during transfer, tcv contains the number of remaining transfers to be done. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 tcv[15:8] 76543210 tcv[7:0]
115 32099a?avr32?06/09 at32uc3l 10.7.8 memory address reload register name: marr access type: read/write offset: 0x00c + n*0x040 reset value: 0x00000000 ? marv: memory address reload value reload value for the mar register. this value will be loaded in to mar when tcr reaches zero if the tcrr register has a non- zero value. 31 30 29 28 27 26 25 24 marv[31:24] 23 22 21 20 19 18 17 16 marv[23:16] 15 14 13 12 11 10 9 8 marv[15:8] 76543210 marv[7:0]
116 32099a?avr32?06/09 at32uc3l 10.7.9 transfer counter reload register name: tcrr access type: read/write offset: 0x010 + n*0x040 reset value: 0x00000000 ? tcrv: transfer counter reload value reload value for the tcr register. when tcr reaches zero, it will be reloaded with tcrv if tcrv has a positive value. if tcrv is zero, no more transfers will be performed for the chann el. when tcr is reloaded, the tcrr register is cleared. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 tcrv[15:8] 76543210 tcrv[7:0]
117 32099a?avr32?06/09 at32uc3l 10.7.10 control register name: cr access type: write-only offset: 0x014 + n*0x040 reset value: 0x00000000 ? eclr: transfer error clear writing a zero to this bit has no effect. writing a one to this bit will clear the transfer error bit in the status register (sr.terr). clearing the sr.terr bit will all ow the channel to transmit data. the memory address must first be set to point to a valid location. ? tdis: transfer disable writing a zero to this bit has no effect. writing a one to this bit will disable transfer for the dma channel. ? ten: transfer enable writing a zero to this bit has no effect. writing a one to this bit will enable transfer for the dma channel. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------eclr 76543210 ------tdisten
118 32099a?avr32?06/09 at32uc3l 10.7.11 mode register name: mr access type: read/write offset: 0x018 + n*0x040 reset value: 0x00000000 ? ring: ring buffer 0:the ring buffer functionality is disabled. 1:the ring buffer functionality is enabled. when enabled, the reload registers, marr and tcrr will not be cleared after reload. ? etrig: event trigger 0:start transfer when the peripheral selected in periph eral select register (psr) requests a transfer. 1:start transfer only when or after a peripheral event is received. ? size: size of transfer 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ---- ring etrig size table 10-5. size of transfer size size of transfer 0 byte 1 halfword 2word 3 reserved
119 32099a?avr32?06/09 at32uc3l 10.7.12 status register name: sr access type: read-only offset: 0x01c + n*0x040 reset value: 0x00000000 ? ten: transfer enabled this bit is cleared when the tdis bit in cr is written to one. this bit is set when the ten bit in cr is written to one. 0: transfer is disabled for the dma channel. 1: transfer is enabled for the dma channel. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------ten
120 32099a?avr32?06/09 at32uc3l 10.7.13 interrupt enable register name: ier access type: write-only offset: 0x020 + n*0x040 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - terr trc rcz
121 32099a?avr32?06/09 at32uc3l 10.7.14 interrupt disable register name: idr access type: write-only offset: 0x024 + n*0x040 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - terr trc rcz
122 32099a?avr32?06/09 at32uc3l 10.7.15 interrupt mask register name: imr access type: read-only offset: 0x028 + n*0x040 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - terr trc rcz
123 32099a?avr32?06/09 at32uc3l 10.7.16 interrupt status register name: isr access type: read-only offset: 0x02c + n*0x040 reset value: 0x00000000 ? terr: transfer error this bit is cleared when no transfer errors ha ve occurred since the last write to cr.eclr. this bit is set when one or more transfer errors has occurred since reset or the last write to cr.eclr. ? trc: transfer complete this bit is cleared when the tcr and/or the tcrr holds a non-zero value. this bit is set when both the tcr and the tcrr are zero. ? rcz: reload counter zero this bit is cleared when the tcrr holds a non-zero value. this bit is set when tcrr is zero. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - terr trc rcz
124 32099a?avr32?06/09 at32uc3l 10.7.17 performance control register name: pcontrol access type: read/write offset: 0x800 reset value: 0x00000000 ? mon1ch: performance monitor channel 1 ? mon0ch: performance monitor channel 0 the pdca channel number to monitor with counter n due to performance monitor hardware resour ce sharing, the two performance monitor channels should not be programmed to monitor the same pdca channel. this may result in undefined monitor behavior. ? ch1res: performance channel 1 counter reset writing a zero to this bit has no effect. writing a one to this bit will reset the counter in performance channel 1. this bit always reads as zero. ? ch0res: performance channel 0 counter reset writing a zero to this bit has no effect. writing a one to this bit will reset the counter in performance channel 0. this bit always reads as zero. ? ch1of: performance channel 1 overflow freeze 0: the performance channel registers are reset if data or stall overflows. 1: all performance channel registers are frozen just before data or stall overflows. ? ch1of: performance channel 0 overflow freeze 0: the performance channel registers are reset if data or stall overflows. 1: all performance channel registers are frozen just before data or stall overflows. ? ch1en: performance channel 1 enable 0: performance channel 1 is disabled. 1: performance channel 1 is enabled. ? ch0en: performance channel 0 enable 0: performance channel 0 is disabled. 1: performance channel 0 is enabled. 31 30 29 28 27 26 25 24 -- mon1ch 23 22 21 20 19 18 17 16 -- mon0ch 15 14 13 12 11 10 9 8 ------ch1resch0res 76543210 - - ch1of ch0of - - ch1en ch0en
125 32099a?avr32?06/09 at32uc3l 10.7.18 performance channel 0 read data cycles name: prdata0 access type: read-only offset: 0x804 reset value: 0x00000000 ? data: data cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 data[31:24] 23 22 21 20 19 18 17 16 data[23:16] 15 14 13 12 11 10 9 8 data[15:8] 76543210 data[7:0]
126 32099a?avr32?06/09 at32uc3l 10.7.19 performance channel 0 read stall cycles name: prstall0 access type: read-only offset: 0x808 reset value: 0x00000000 ? stall: stall cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 stall[31:24] 23 22 21 20 19 18 17 16 stall[23:16] 15 14 13 12 11 10 9 8 stall[15:8] 76543210 stall[7:0]
127 32099a?avr32?06/09 at32uc3l 10.7.20 performance channel 0 read max latency name: prlat0 access type: read/write offset : 0x80c reset value: 0x00000000 ? lat: maximum transfer initiation cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock this counter is saturating. the register is reset only when pcontrol.ch0res is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 lat[15:8] 76543210 lat[7:0]
128 32099a?avr32?06/09 at32uc3l 10.7.21 performance channel 0 write data cycles name: pwdata0 access type: read-only offset: 0x810 reset value: 0x00000000 ? data: data cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 data[31:24] 23 22 21 20 19 18 17 16 data[23:16] 15 14 13 12 11 10 9 8 data[15:8] 76543210 data[7:0]
129 32099a?avr32?06/09 at32uc3l 10.7.22 performance channel 0 write stall cycles name: pwstall0 access type: read-only offset: 0x814 reset value: 0x00000000 ? stall: stall cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 stall[31:24] 23 22 21 20 19 18 17 16 stall[23:16] 15 14 13 12 11 10 9 8 stall[15:8] 76543210 stall[7:0]
130 32099a?avr32?06/09 at32uc3l 10.7.23 performance channel 0 write max latency name: pwlat0 access type: read/write offset : 0x818 reset value: 0x00000000 ? lat: maximum transfer initiation cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock this counter is saturating. the register is reset only when pcontrol.ch0res is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 lat[15:8] 76543210 lat[7:0]
131 32099a?avr32?06/09 at32uc3l 10.7.24 performance channel 1 read data cycles name: prdata1 access type: read-only offset: 0x81c reset value: 0x00000000 ? data: data cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 data[31:24] 23 22 21 20 19 18 17 16 data[23:16] 15 14 13 12 11 10 9 8 data[15:8] 76543210 data[7:0]
132 32099a?avr32?06/09 at32uc3l 10.7.25 performance channel 1 read stall cycles name: prstall1 access type: read-only offset: 0x820 reset value: 0x00000000 ? stall: stall cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 stall[31:24] 23 22 21 20 19 18 17 16 stall[23:16] 15 14 13 12 11 10 9 8 stall[15:8] 76543210 stall[7:0]
133 32099a?avr32?06/09 at32uc3l 10.7.26 performance channel 1 read max latency name: platr1 access type: read/write offset : 0x824 reset value: 0x00000000 ? lat: maximum transfer initiation cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock this counter is saturating. the register is reset only when pcontrol.ch1res is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 lat[15:8] 76543210 lat[7:0]
134 32099a?avr32?06/09 at32uc3l 10.7.27 performance channel 1 write data cycles name: pwdata1 access type: read-only offset: 0x828 reset value: 0x00000000 ? data: data cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 data[31:24] 23 22 21 20 19 18 17 16 data[23:16] 15 14 13 12 11 10 9 8 data[15:8] 76543210 data[7:0]
135 32099a?avr32?06/09 at32uc3l 10.7.28 performance channel 1 write stall cycles name: pwstall1 access type: read-only offset: 0x82c reset value: 0x00000000 ? stall: stall cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock 31 30 29 28 27 26 25 24 stall[31:24] 23 22 21 20 19 18 17 16 stall[23:16] 15 14 13 12 11 10 9 8 stall[15:8] 76543210 stall[7:0]
136 32099a?avr32?06/09 at32uc3l 10.7.29 performance channel 1 write max latency name: pwlat1 access type: read/write offset : 0x830 reset value: 0x00000000 ? lat: maximum transfer initiation cycles counted since last reset clock cycles are counted us ing the clk_pdca_hsb clock this counter is saturating. the register is reset only when pcontrol.ch1res is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 lat[15:8] 76543210 lat[7:0]
137 32099a?avr32?06/09 at32uc3l 10.7.30 pdca version register name: version access type: read-only offset: 0x834 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
138 32099a?avr32?06/09 at32uc3l 10.8 module configuration the specific configuration for each pdca instance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. the table below defines the valid peripheral ident ifiers (pids). the dire ction is specified as observed from the memory, so rx means transfers from peripheral to memory and tx means from memory to peripheral. table 10-6. pdca configuration feature pdca number of channels 12 table 10-7. module clock name module name pb clock name hsb clock name pdca clk_pdca_pb clk_pdca_hsb table 10-8. register reset values register reset value psr ch 0 0 psr ch 1 1 psr ch 2 2 psr ch 3 3 psr ch 4 4 psr ch 5 5 psr ch 6 6 psr ch 7 7 psr ch 8 8 psr ch 9 9 psr ch 10 10 psr ch 11 11 version 122 table 10-9. peripheral identity values pid direction peripheral in stance peripheral register 0 rx usart0 thr 1 rx usart1 thr 2 rx usart2 thr 3 rx usart3 thr 4 rx spi tdr 5rxtwim0 thr
139 32099a?avr32?06/09 at32uc3l 6rxtwim1 thr 7rxtwis0 thr 8rxtwis1 thr 9 rx adcifb lcdr 10 rx aw thr 11 rx cat mblen 12 tx usart0 rhr 13 tx usart1 rhr 14 tx usart2 rhr 15 tx usart3 rhr 16 tx spi rdr 17 tx twim0 rhr 18 tx twim1 rhr 19 tx twis0 rhr 20 tx twis1 rhr 21 tx aw rhr 22 tx cat acount table 10-9. peripheral identity values pid direction peripheral in stance peripheral register
140 32099a?avr32?06/09 at32uc3l 11. peripheral event system rev: 1.0.0.0 11.1 features ? direct peripheral to peri pheral communication system ? allows peripherals to receive, react to, and send peripheral events without cpu intervention ? cycle deterministic event communication ? asynchronous interrupts allow advanced peri pheral operation in low power sleep modes 11.2 overview several peripheral modules can be configured to emit or respond to signals known as peripheral events. the exact condition to trigger a peripheral event, or the action taken upon receiving a peripheral event, is specific to each module. pe ripherals that respond to peripheral events are called peripheral event users and peripherals that emit peripheral events are called peripheral event generators. a single module can be both a peripheral event generator and user. the peripheral event generators and users are interconnected by a network known as the peripheral event system. this allows low latency peripheral-to-peripheral signaling without cpu intervention, and without cons uming system resources such as bus or ram bandwidth. this offloads the cpu and system resources compared to a traditional interrupt-based software driven system. 11.3 peripheral event sy stem block diagram figure 11-1. peripheral event system block diagram 11.4 functional description 11.4.1 configuration the peripheral event system in the at32uc 3l has a fixed mapping of peripheral events between generators and users, as described in table 11-1 . thus, the user does not need to con- peripheral event system generator generator user generator/ user
141 32099a?avr32?06/09 at32uc3l figure the interconnection between the modules, although each peripheral event can be enabled or disabled at the generator or user side as described in the peripheral chapter for each module. note: there are six pin-change interrupts in the at32uc3l, where pin-change interrupt 3 corresponds to pa24-31. these pins are non-existing on the at32uc3l, and thus this pin-change interrupt can never be triggered. pin change peripheral events are mapped in the same manner as pin-change interrupts, and thus the pin-change peripheral event 3 can never be triggered. the tc[1].a0.cap- ture can still be reached by selecting the peripheral function in the i/o controller. 11.4.2 peripheral event connections each generated peripheral event is connected to one or more users. if a peripheral event is con- nected to multiple users, the peripheral event can trigger actions in multiple modules. a peripheral event user can likewise be connected to one or more peripheral event generators. if a peripheral event user is connected to multiple generators, the peripheral events are or?ed together to a single peripheral event. this means that peripheral events from either one of the generators will result in a pe ripheral event to the user. to configure a peripheral event, the peripheral event must be enabled at both the generator and user side. even if a generator is connected to multiple users, only the users with the peripheral event enabled will trigger on the peripheral event. 11.4.3 low power operation as the peripheral events do not require cpu intervention, they are available in idle mode. they are also available in deeper sleep modes if both the generator and user remain clocked in that mode. table 11-1. peripheral event generators and users interconnection generator user asynchronous gpio.pin_change[0] tc[0].a0.capture n gpio.pin_change[1] tc[0].a1.capture n gpio.pin_change[2] tc[0].a2.capture n gpio.pin_change[3] tc[1].a0.capture n gpio.pin_change[4] tc[1].a1.capture n gpio.pin_change[5] tc[1].a2.capture n ast.event acifb.trig y ast.event adcifb.trig y ast.event cat.capsense y acifb.compare[15:0] pwma.adjust[15:0] n acifb cat n pwma.channel_0 acifb.trig n pwma.channel_0 adcifb.trig n
142 32099a?avr32?06/09 at32uc3l certain events are known as asynchronous peripheral events, as identified in table 11-1 on page 141 . these can be issued even when the system clock is stopped, and revive unclocked user peripherals. the clock will be restarted for this m odule only, without wa king the system from sleep mode. the clock remains active only as long as required by the triggered function, before being switched off again, and the system remain s in the original sleep mode. the cpu and sys- tem will only be woken up if the user peripheral generates an interrupt as a result of the operation. this concept is known as sleepwalking ? and is described in further detail in the power manager chapter. note that asynchronous peripheral events may be associated with a delay due to the need to restart the system cl ock source if this has been stopped in the sleep mode. 11.5 application example this application example shows how the peripheral event system can be used to program the adc interface to perform adc conversions at selected intervals. conversions of the active analog channels are st arted with a software or a hardware trigger. one of the possible hardware triggers is a peripheral event trigger, allowing the peripheral event system to synchronize conversion with some configured peripheral event source. from table 11-1 on page 141 , it can be read that this peripheral event source can be either an ast periph- eral event, or an event from the pwm controller. the ast can generate periodic peripheral events at selected intervals, among other types of peripheral events. the peripheral event sys- tem can then be used to set up the adc inte rface to sample an analog signal at regular intervals. the user must enable peripheral events in the ast and in the adc interface to accomplish this. the periodic peripheral event in the ast is enabl ed by writing a one to the corresponding bit in the ast event enable register (eve). to select the peripheral event trigger for the adc inter- face, the user must write the value 0x7 to the trigger mode (trgmod) field in the adc interface trig ger register (trgr). when the peripheral ev ents are enabled, the ast will gener- ate peripheral events at the selected intervals, and the peripheral event system will route the peripheral events to the adc interface, which will perform adc conversions at the selected intervals. figure 11-2. application example since the ast peripheral event is asynchronous , the description above will also work in sleep modes where the adc clock is stopped. in this case, the adc clock (and clock source, if needed) will be restarted during the adc conversion. after the conversion, the adc clock and clock source will return to the sleep state, unless the adc generates an interrupt, which in turn will wake up the system. using asynchronous inte rrupts thus allows adc operation in much lower power states than would otherwise be possible. peripheral event system ast adc interface periodic peripheral event
143 32099a?avr32?06/09 at32uc3l 12. interrupt controller (intc) rev: 1.0.0.4 12.1 features ? autovectored low latency interrupt service with programmable priority ? 4 priority levels for regular, maskable interrupts ? one non-maskable interrupt ? up to 64 groups of interrupts with up to 32 interrupt requests in each group 12.2 overview the intc collects interrupt requests from the peripherals, prioritizes them, and delivers an inter- rupt request and an autovector to the cpu. the avr32 architecture supports 4 priority levels for regular, maskable interrupts, and a non-maskable interrupt (nmi). the intc supports up to 64 groups of interrupts. each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. each group has an interrupt priority register (ipr) and an interrupt request register (irr). the iprs are used to assign a priority level and an autovector to each group, and the irrs are used to identify the active interrupt request within each group. if a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding irr is not needed. the intc also provides one interrupt cause register (icr) per priority level. these registers identify the group that has a pending interrupt of the corresponding priority level. if several groups have a pending interrupt of the same level, the group with the lowest number takes priority. 12.3 block diagram figure 12-1 gives an overview of the intc. the grey boxes represent registers that can be accessed via the user interface. the interrupt requests from the peripherals (ireqn) and the nmi are input on the left side of the figure. signals to and from the cpu are on the right side of the figure.
144 32099a?avr32?06/09 at32uc3l figure 12-1. intc block diagram 12.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 12.4.1 power management if the cpu enters a sleep mode that disables cl ocks used by the intc, the intc will stop func- tioning and resume operation after the system wakes up from sleep mode. 12.4.2 clocks the clock for the intc bus interface (clk_intc) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. 12.4.3 debug operation when an external debugger forces the cpu into debug mode, the intc continues normal operation. 12.5 functional description all of the incoming interrupt requests (ireqs) are sampled into the corresponding interrupt request register (irr). the irrs must be accessed to identify which ireq within a group that is active. if several ireqs within the same group are active, the interrupt service routine must prioritize between them. all of the input lines in each group are logically ored together to form the grpreqn lines, indicating if there is a pending interrupt in the corresponding group. the request masking hardware maps each of the grpreq lines to a priority level from int0 to int3 by associating each grou p with the interrupt level (int level) field in the corresponding interrupt priority register (ipr). the grpreq inputs are then masked by the mask bits from the cpu status register. any interrupt group that has a pending interrupt of a priority level that is not masked by the cpu status register, gets its corresponding valreq line asserted. request masking or ireq0 ireq1 ireq2 ireq31 grpreq0 masks sreg masks i[3-0]m gm intlevel autovector prioritizer cpu interrupt controller or grpreqn nmireq or ireq32 ireq33 ireq34 ireq63 grpreq1 irr registers ipr registers icr registers int_level, offset int_level, offset int_level, offset ipr0 ipr1 iprn irr0 irr1 irrn valreq0 valreq1 valreqn . . . . . . . . .
145 32099a?avr32?06/09 at32uc3l masking of the interrupt requests is done based on five interrupt mask bits of the cpu status register, namely interrupt level 3 mask (i3m) to interrupt level 0 mask (i0m), and global inter- rupt mask (gm). an interrupt request is masked if either the gm or the corresponding interrupt level mask bit is set. the prioritizer hardware uses th e valreq lines and the intlevel fi eld in the iprs to select the pending interrupt of the highest priority. if an nm i interrupt request is pending, it automatically gets the highest priority of any pending interrupt. if several interrupt groups of the highest pend- ing interrupt level have pending interrupts, the interrupt group with the highest number is selected. the intlevel and handler autovector offset (autovector) of the selected interrupt are transmitted to the cpu for interrupt handling an d context switching. the cpu does not need to know which interrupt is requesting handling, but only the level and the offset of the handler address. the irr registers contain the interrupt request lines of the groups and can be read via user interface registers for checking which interrupts of the group are actually active. 12.5.1 non-maskable interrupts a nmi request has priority over all other interrupt requests. nmi has a dedicated exception vec- tor address defined by the avr32 archit ecture, so autovector is undefined when intlevel indicates that an nmi is pending. 12.5.2 cpu response when the cpu receives an interr upt request it checks if any othe r exceptions are pending. if no exceptions of higher priority are pending, interr upt handling is initiated. when initiating interrupt handling, the corresponding interrupt mask bit is se t automatically for this and lower levels in sta- tus register. e.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits i3m, i2m, i1m, and i0m are set in status register. if an interrupt of level 1 is approved, the masking bits i1m and i0m are set in status register. the handler address is calculated by adding autovector to the cpu system register exc eption vector base address (evba). the cpu will then jump to the calculated address and start executing th e interrupt handler. setting the interrupt mask bits prevents the interrupts from the same and lower levels to be passed through the interrupt controller. setting of the same level mask bit prevents also multiple requests of the same interrupt to happen. it is the responsibility of the ha ndler software to clear the interrupt request that caused the inter- rupt before returning from the interrupt handler. if the conditions that caused the interrupt are not cleared, the interrupt request remains active. 12.5.3 clearing an interrupt request clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding nmireq/ireq signal. the recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operat ion from the same register. this causes a pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
146 32099a?avr32?06/09 at32uc3l 12.6 user interface table 12-1. intc register memory map offset register register name access reset 0x000 interrupt priority register 0 ipr0 read/write 0x00000000 0x004 interrupt priority register 1 ipr1 read/write 0x00000000 ... ... ... ... ... 0x0fc interrupt priority register 63 ipr63 read/write 0x00000000 0x100 interrupt request register 0 irr0 read-only n/a 0x104 interrupt request register 1 irr1 read-only n/a ... ... ... ... ... 0x1fc interrupt request regi ster 63 irr63 read-only n/a 0x200 interrupt cause register 3 icr3 read-only n/a 0x204 interrupt cause register 2 icr2 read-only n/a 0x208 interrupt cause register 1 icr1 read-only n/a 0x20c interrupt cause register 0 icr0 read-only n/a
147 32099a?avr32?06/09 at32uc3l 12.6.1 interrupt priority registers register name : ipr0...ipr63 access type: read/write offset: 0x000 - 0x0fc reset value: 0x00000000 ? intlevel: interrupt level indicates the evba-relative offs et of the interrup t handler of the co rresponding group: 00: int0 01: int1 10: int2 11: int3 ? autovector: autovector address handler offset is used to give the address of the interrupt handle r. the least significant bit should be written to zero to giv e halfword alignment. 31 30 29 28 27 26 25 24 intlevel[1:0] ------ 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - autovector[13:8] 76543210 autovector[7:0]
148 32099a?avr32?06/09 at32uc3l 12.6.2 interrupt request registers name : irr0...irr63 access type: read-only offset: 0x0ff - 0x1fc reset value: n/a ? irr: interrupt request line this bit is cleared when no interrupt request is pending on this input request line. this bit is set when an interrupt request is pending on this input request line. the are 64 irrs, one for each group. each irr has 32 bits, one for each possible interrupt request, for a total of 2048 possibl e input lines. the irrs are read by the software interrupt handler in order to determine which interrupt request is pending. the irrs are sampled continuously, and are read-only. 31 30 29 28 27 26 25 24 irr[32*x+31] irr[32*x+30] irr[32*x+ 29] irr[32*x+28] irr[32* x+27] irr[32*x+26] irr[32*x+25] irr[32*x+24] 23 22 21 20 19 18 17 16 irr[32*x+23] irr[32*x+22] irr[32*x+ 21] irr[32*x+20] irr[32* x+19] irr[32*x+18] irr[32*x+17] irr[32*x+16] 15 14 13 12 11 10 9 8 irr[32*x+15] irr[32*x+14] irr[32*x+ 13] irr[32*x+12] irr[32*x+ 11] irr[32*x+10] irr[32*x+9] irr[32*x+8] 76543210 irr[32*x+7] irr[32*x+6] irr[32*x+5] irr[32*x+4] irr[32*x+3] irr[32*x+2] irr[32*x+1] irr[32*x+0]
149 32099a?avr32?06/09 at32uc3l 12.6.3 interrupt cause registers register name : icr0...icr3 access type: read-only offset: 0x200 - 0x20c reset value: n/a ? cause: interrupt group causing interrupt of priority n icrn identifies the group with the highest pr iority that has a pending interrupt of le vel n. this value is only defined when at least one interrupt of level n is pending. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -- cause
150 32099a?avr32?06/09 at32uc3l 12.7 module configuration the specific configuration for each intc instance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. 12.7.1 interrupt request signal map the interrupt controller supports up to 64 groups of interrupt requests. each group can have up to 32 interrupt request signals. all interrupt signals in the same group share the same autovector address and priority level. the table below shows how the interrupt re quest signals are connected to the intc. table 12-2. intc clock name module name clock name intc clk_intc table 12-3. interrupt request signal map group line module signal 0 0 avr32 uc3 core sysblock compare 1 0 avr32 uc3 core ocd dcemu_dirty 1 avr32 uc3 core ocd dccpu_read 2 0 flash controller flashcdw 3 0 secure access unit sau 4 0 peripheral dma controller pdca 0 1 peripheral dma controller pdca 1 2 peripheral dma controller pdca 2 3 peripheral dma controller pdca 3 5 0 peripheral dma controller pdca 4 1 peripheral dma controller pdca 5 2 peripheral dma controller pdca 6 3 peripheral dma controller pdca 7 6 0 peripheral dma controller pdca 8 1 peripheral dma controller pdca 9 2 peripheral dma controller pdca 10 3 peripheral dma controller pdca 11 7 0 power manager pm 8 0 system control interface scif 9 0 asynchronous timer ast alarm
151 32099a?avr32?06/09 at32uc3l 10 0 asynchronous timer ast per 1 asynchronous timer ast ovf 2 asynchronous timer ast ready 3 asynchronous timer ast clkready 11 0 external interrupt controller eic 1 1 external interrupt controller eic 2 2 external interrupt controller eic 3 3 external interrupt controller eic 4 12 0 external interrupt controller eic 5 13 0 frequency meter freqm 14 0 general purpose input/ou tput controller gpio 0 1 general purpose input/ou tput controller gpio 1 2 general purpose input/ou tput controller gpio 2 3 general purpose input/ou tput controller gpio 3 4 general purpose input/ou tput controller gpio 4 5 general purpose input/ou tput controller gpio 5 15 0 universal synchronous/asynchronous receiver/transmitter usart0 16 0 universal synchronous/asynchronous receiver/transmitter usart1 17 0 universal synchronous/asynchronous receiver/transmitter usart2 18 0 universal synchronous/asynchronous receiver/transmitter usart3 19 0 serial peripheral interface spi 20 0 two-wire master interface twim0 21 0 two-wire master interface twim1 22 0 two-wire slave interface twis0 23 0 two-wire slave interface twis1 24 0 basic pulse width modulation controller pwma 25 0 timer/counter tc00 1 timer/counter tc01 2 timer/counter tc02 26 0 timer/counter tc10 1 timer/counter tc11 2 timer/counter tc12 27 0 adc interface adcifb table 12-3. interrupt request signal map
152 32099a?avr32?06/09 at32uc3l 28 0 analog comparator interface acifb 29 0 capacitive touch module cat 30 0 awire aw table 12-3. interrupt request signal map
153 32099a?avr32?06/09 at32uc3l 13. power manager (pm) rev: 4.1.1.0 13.1 features ? generates clocks and resets for digital logic ? on-the-fly frequency change of cpu, hsb and pbx clocks ? sleep modes allow simple disabling of logic clocks and clock sources ? module-level clock gating through maskable peripheral clocks ? wake-up from internal or external interrupts ? automatic identificat ion of reset sources ? support advanced sh utdown sleep mode 13.2 overview the power manager (pm) provides synchronous clocks used to clock the main digital logic in the device, namely the cpu, and the modules and peripherals connected to the high speed bus (hsb) and the peripe ral buses (pbx). the pm also contains advanced power-saving feat ures, allowing the user to optimize the power consumption for an application. the synchronous clocks are divided into a number of clock domains, one for the cpu and hsb and one for each pbx. the clocks can run at different speeds, so the user can save power by running pe ripherals at a relatively low clock, while main- taining a high cpu performance. additionally, the clocks can be independently changed on-the- fly, without halting any peripherals. this enables the user to adjust the speed of the cpu and memories to the dynamic load of the applicati on, without disturbing or re-configuring active peripherals. each module also has a separate clock, enabling t he user to switch off the clock for inactive modules, to save further pow er. additionally, clocks and os cillators can be automatically switched off during idle period s by using the sleep instruction on the cpu. the system will return to normal operation on occurrence of interrupts. to get maximum power savings, a special sleep mode, called shutdown is available, where power on all internal logic (cpu, peripherals) and most of the i/o lines is removed, reducing leakage. only a small amount of logic, incl uding 32khz crystal osci llator and ast is left powered. the power manager also contains a reset contro ller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software.
154 32099a?avr32?06/09 at32uc3l 13.3 block diagram figure 13-1. pm block diagram 13.4 i/o lines description 13.5 product dependencies 13.5.1 interrupt the pm interrupt line is connected to one of the internal sources of the interrupt controller. using the pm interrupt requires the interrupt controller to be programmed first. 13.5.2 clock implementation in at32uc3l, the hsb shares the source clock with the cpu. this means that writing to the hsbsel register has no effect. this register will always read the same value as cpusel. 13.5.3 power considerations the shutdown mode is only available for the ? 3.3v supply mode, with 1.8v regulated i/o lines ? power configuration. table 13-1. i/o lines description name description type active level reset_n reset input low sleep controller synchronous clock generator reset controller main clock sources sleep instruction power-on detector resets synchronous clocks cpu, hsb, pbx interrupts external reset pad reset sources
155 32099a?avr32?06/09 at32uc3l 13.6 functional description 13.6.1 synchronous clocks the system rc oscillatro (rcsys) or a set of other clock sources provide the source for the main clock, which is the common root for the synchronous clocks for the cpu/hsb and pbx modules. for details about the other main clock sources, please refer to the register description of the main clock control register (mcctrl). the main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as f cpu f pbx, . the synchronous clock s ource can be changed on- the fly, responding to varying load in the application. the clock domains can be shut down in sleep mode, as described in section 13.6.3 . additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules. figure 13-2. synchronous clock generation 13.6.1.1 selecting the main clock source the common main clock can be connected to rcsys or a set of other cl ock sources. for details about the other main clock sources, please refer to the register description of the main clock control register (mcctrl). by default, the main clock will be connected to rcsys. the user can connect the main clock to an other source by writing the mcsel field in the mcctrl regis- ter. this must only be done after that unit has been enabled, otherwise a deadlock will occur. care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain. 13.6.1.2 selecting synchronous clock division ratio the main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. by default, the synchronous clocks run on the undivided main clock. the user can select a pres- caler division for the cpu clock by writing cpud iv in cpusel register to 1 and cpusel in cpusel register to the value, resulting in a cpu clock frequency: f cpu = f main / 2 (cpusel+1) mask prescaler main clock sources mcsel 0 1 cpusel cpudiv main clock sleep controller cpumask cpu clocks hsb clocks pbx clocks sleep instruction
156 32099a?avr32?06/09 at32uc3l similarly, the clock for the pbx can be divided by writing their respective registers. to ensure correct operation, frequencies must be selected so that f cpu f pbx . also, frequencies must never exceed the specified maximum frequency for each clock domain. cpusel and pbxsel can be written without halting or disabling peripheral modules. writing cpusel and pbxsel allows a new clock setting to be written to all synchronous clocks at the same time. it is possible to keep one or more clocks unchanged by only writing to one of the reg- isters. this way, it is possible to, e.g., scale cpu and hsb speed according to the required performance, while keeping the pbx frequency constant. 13.6.1.3 clock ready flag there is a slight delay from cpusel and pbxsel is written and the new clock setting becomes effective. during this interval, the clock ready (ckrdy) flag in isr will read as 0. if ckrdy in the ier register is written to 1, the power manager interrupt can be triggered when the new clock setting is effective. cksel must not be re -written while ckrdy is 0, or the system may become unstable or hang. 13.6.2 peripheral clock masking by default, the clock for all modules are enabled, regardless of which modules are actually being used. it is possible to disable the clock for a module in the cpu, hsb or pbx clock domain by writing the corresponding bit in the clock mask register (cpu/hsb/pbx) to 0. when a module is not clocked, it will cease operati on, and its registers cannot be re ad or written. the module can be re-enabled later by writing the corresponding mask bit to 1. a module may be connected to several clock domains, in which case it will have several mask bits. table 13-9 on page 169 contains a list of implemented maskable clocks. 13.6.2.1 cautionary note note that clocks should only be switched off if it is certain that the module will not be used. switching off the clock for the flash controller will cause a problem if the cpu needs to read from the flash. switching off the clock to the power manager (pm), which contains the mask registers, or the correspond ing pbx bridge, will make it impossible to write the ma sk registers again. in this case, they can only be re-enabled by a system reset. 13.6.3 sleep modes in normal operation, all clock domains are active, allowing software execution and peripheral operation. when the cpu is idle, it is possible to switch off the cpu clock and optionally other clock domains to save power. this is activate d by the sleep instruction, which takes the sleep mode index number as argument. 13.6.3.1 entering and exiting sleep modes the sleep instruction will halt the cpu and all modules belonging to t he stopped clock domains. the modules will be halted regardless of th e bit settings of the mask registers. clock sources can also be switched off to save power. some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. the cpu and affected modules are restarted when the sleep mode is exited. this occurs when an interrupt triggers. note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked.
157 32099a?avr32?06/09 at32uc3l 13.6.3.2 supported sleep modes the following sleep modes are supported. these are detailed in table 13-2 on page 157 . ? idle: the cpu is stopped, the rest of the chip is operating. wake-up sources are any interrupts. ? frozen: the cpu and hsb modules are stopped, peripherals are operating. wake-up sources are any interrupts from pb modules. ? standby: all synchronous clocks are stopped, but the clock sources are running, allowing quick wake-up to normal mode. wake-up sources are ast, wdt, external interrupts, external reset or any asynchronous interrupts from pb modules. ? stop: as standby, but oscillators, and other clock sources are stopped. 32 khz (if enabled), rc oscillators, ast and wdt will still operate. wa ke-up sources are the same as for standby mode. ? deepstop: all synchronous clocks and clock so urces are stopped. 32 khz oscillator can run if enabled. rc oscillator still operates. bandgap voltage refere nce and bod is turned off. wake-up sources are the same as for standby mode. ? static: all clock sources, including rc oscilla tor are stopped. 32 khz oscillator can run if enabled. bandgap voltage reference bod detector is turned off. wake-up sources are ast, external interrupts, external reset or any asynchronous interrupts from pb modules. ? shutdown: all clock sources, including rc os cillator are stopp ed. 32 khz oscillator can run if enabled. bandgap voltage reference bod detector is turned off. voltage regulator is turned off. wake-up sources are external reset or external wake-up pin. this mode can only be used in the ? 3.3v supply mode, with 1.8v regulated i/o lines ? configuration (described in power considerations chapter). see section 13.6.4 for more details. the power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 13.6.3.3 sleepwalking ? in all sleep modes where the pbx clocks are stopped, except for shutdown mode, the chip can wake partially up if a pbx module asynchronously discovers that it needs its clock. only the requested clocks and clock sources needed will be started, and all other clocks will be masked to zero. e.g. if the main clock source is osc0 , only osc0 will be started even if other clock sources were enabled in normal mode. also generic clocks can be started in a similar way. the state where only requested clocks are running is referred to as sleepwalking. table 13-2. sleep modes index sleep mode cpu hsb pba,b gclk clock sources osc32 rcsys bod & bandgap voltage regulator 0 idle stop run run run run run on full power 1 frozen stop stop run run run run on full power 2 standby stop stop stop run run run on full power 3 stop stop stop stop stop run run on low power 4 deepstop stop stop stop stop run run off low power 5 static stop stop stop stop run stop off low power 6 shutdown stop stop stop stop run stop off off
158 32099a?avr32?06/09 at32uc3l the time spent to start the requested clock is mostly limited by the startup time of the given clock source. this allows pbx modules to handle incoming requests, while still keeping the power con- sumption at a minimum. when the chip is sleepwalking any asynchronous interrupt can wake up the chip at any time without stopping the requested pbx clock. the request to start the clock can come from the module itse lf or through the event system, please refer to the even t system and module chapte rs for details. all requests to start clocks can be masked by writing to the peripheral power control register (ppcr), all requests are enabled at reset. 13.6.3.4 precautions when entering sleep mode modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the mo dule operation. this prevents erra tic behavior when entering or exiting sleep mode. please refer to the re levant module documentation for recommended actions. communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. this means that bus transactions are not allowed between clock domains affected by the sleep mode. the system may hang if th e bus clocks are stopped in the middle of a bus transaction. the cpu is automatically stopped in a safe state to ensure that all cpu bus operations are com- plete when the sleep mode goes into effect. thus, when entering idle mode, no further action is necessary. when entering a sleep mode (except idle mode), all hsb masters must be stopped before entering the sleep mode. also, if there is a chance that any pb write operations are incomplete, the cpu should perform a read operation from any register on the pb bus before executing the sleep instruction. this will stall the cpu while waiting for any pend ing pb operations to complete. the shutdown sleep mode requires extra care. please refer to section 13.6.4 . 13.6.4 shutdown sleep mode 13.6.4.1 description the shutdown sleep mode is available only when the chip is used in the ? 3.3v supply mode, with 1.8v regulated i/o lines ? configuration (see power consider ations chapter). in this config- uration, the voltage regu lator supplies both vddcore and vddio power supplies. when the device enters shutdown mode, the regulator is turned off and only the following logic is kept powered by vddin: ? 2nd 32khz crystal oscillato r (available on pa13/pa20) ? ast core logic (internal counter and alarm detection logic) ? i/o lines pa11,pa13,pa20,pa21,pb04,pb05,pb10 ? reset_n line
159 32099a?avr32?06/09 at32uc3l the table gives the possible usage of the i/o li nes that stay powered during the shutdown sleep mode. if no special func tion are used, then the i/o lines will keep its settings before entering the sleep mode 13.6.4.2 entering shutdown sleep mode before entering the shutdown sleep mode, a few actions are required: ? all modules should normally be disabled before entering shutdown sleep mode (see section 13.6.3.4 ) ? the por33 (see system control interface ?scif? chapter) must be disabled to save power and masked to avoid any spurious reset when the power is back. the following pseudo-code shows how to performs this operation: // turn on rc32 oscillator (if not already on) set bit ?en? in scif.rc32cr register to 1 // disable por33 set bit ?por33en? in scif.vregcr register to 0 wait for bit ?por33en? is read as 0 // mask por33 set bit ?por33mask? in scif.vregcr register to 1 wait for bit ?por33mask? is read as 1 // turn off rc32 oscillator - save some power set bit ?en? in scif.rc32cr register to 0 // go to sleep sleep avr32_pm_smode_shutdown note: the unlocking of scif registers is not shown in the example above. as soon as the shutdown sleep mode is entered, all cpu and peripherals are reset to ensure a consistent state. table 13-3. i/o lines usage during shutdown mode pin possible usage during shutdown sleep mode pa11 wake_n signal (active low wake-up) pa13 xin32_2 (2nd 32khz crystal oscillator) pa20 xout32_2 pa 2 1 pb04 pb05 pb10 reset_n reset pin
160 32099a?avr32?06/09 at32uc3l 13.6.4.3 leaving shutdown sleep mode exiting the shutdown sleep mode can be done using the events described in table 13-4 on page 160 . when a wake-up event occurs, the regulator is turned-on again and the device will wait for vddcore power to be valid again before starting again. the bit sleep is then set in the rcause register. this allows software ru nning on the device to distinguish between the first power-up and a wake-up from shutdown mode. 13.6.5 divided pb clocks the clock generator in the powe r manager provides di vided pbx clocks for use by peripherals that require a prescaled pbx clock. this is described in the documentation for the relevant modules. the divided clocks are directly maskable, and are stopped in sleep modes where the pbx clocks are stopped. 13.6.6 reset controller the reset controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. the device contains a power-on detector, which keeps the system reset until power is stable. this eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. it is also possible to reset the device by asse rting the reset_n pin. th is pin has an internal pull-up, and does not need to be driven externally when negated. table 13-5 on page 161 lists these and other reset sources supported by the reset controller. table 13-4. events that can wake-up the device from shutdown mode source how pa11 (wake_n) pulling-down pa11 will wake-up the device reset_n pulling-down reset_n pin will wake-up the device the device is kept under re set until reset_n is tied high again ast 32khz crystal oscillator must be set-up to use alternate pinout (xin32_2 and xout 32_2) see scif chapter ast must be configured to use the clock from the 32khz crystal oscillator ast must be configured to allow alarm,periodic or overflow wake-up
161 32099a?avr32?06/09 at32uc3l figure 13-3. reset controller block diagram in addition to the listed reset types, the jtag & awire can keep parts of the device statically reset. see jtag and awire documentation for details. table 13-5. reset description when a reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. only the power on reset (por ) will force a reset of the whole chip. reset source description power-on reset supply voltage below the power-on reset detector threshold voltage external reset reset_n pin asserted brownout reset supply voltage on vddcore below the brownout reset detector threshold voltage sm33 reset supply voltage on vddcore below the brownout reset detector threshold voltage watchdog timer see watchdog timer documentation. ocd see on-chip debug documentation jtag reset controller reset_n power-on detector ocd watchdog reset rc_rcause cpu, hsb, pbx ocd, ast, wdt, clock generator brownout detector awire sm33 detector
162 32099a?avr32?06/09 at32uc3l table 2-6 on page 11 lists parts of the device that are reset, depending on the reset source. the cause of the last reset can be read from the rcause register. this register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken. 13.6.6.1 power-on detector the power-on detector monitors the vddcore supply pin and generates a reset when the device is powered on. the reset is active until the supply voltage from the linear regulator is above the power-on threshold leve l. the reset will be re -activated if the vo ltage drops below the power-on threshold level. see electrical characteristics for parametric details. 13.6.6.2 external reset the external reset detector monitors the state of the reset_n pin. by default, a low level on this pin will generate a reset. 13.6.7 clock failure detector this mechanism allo ws switching the main cl ock to the safe rcsys clock, when the main clock source is considered off. this may happen when a external crystal is selected as the clock source of the main clock but the cyrstal is not mounted on the board. the mechanism is to detect, during a rcsys period, at least one ri sing edge of the main clock. if no rising edge is seen the clock is considered failed. example: * rcsys = 115khz => failure detected if the main clock is < 115 khz table 13-6. effect of the different reset events power-on reset external reset watchdog reset bod reset sm33 reset ocd reset jtag reset cpu/hsb/pbx (excluding power manager) y y y yyyy 32 khz oscillator y n n n n n n ast control register y n n n n n n watchdog control register y y n y y y y voltage calibration register y n n n n n n rc oscillator calibration register y n n n n n n sm33 control register y y y y y y y bod control register y y y n y y y bandgap control register y y y n y y y clock control registers y y y y y y y osc control registers y y y y y y y dfll control registers y y y y y y y ocd system and ocd registers y y n y y n y
163 32099a?avr32?06/09 at32uc3l as soon as the dete ctor is enabled, the clock failure dete ctor will monitor the divided main clock. note that the detector does not monitor if the rcsys is the source of the main clock, or if the main clock is temporarily not available (startup-tim e after a wake-up, switching timing etc.), or in sleep mode where the main cl ock is driven by the rcsys (sto p and deepstop mode). when a clock failure is detected, the ma in clock automatically switches to the rcsys clock and the cfd interrupt is generated if enabled. the mcctrl register that select s the source clock of the main clock is changed by hardware to indicate that the main clock comes from rcsys. 13.6.8 interrupts the pm has a number of interrupts: ? ae: access error, set if a lock protected register is written without first beeing unlocked. ? ckrdy: clock ready, set when new cksel setings are effective. ? cfd: clock failure detected, set if the system detects that the main clock is not running.
164 32099a?avr32?06/09 at32uc3l 13.7 user interface note: 1. the reset value is device specific. please refer to th e module configuration section at the end of this chapter. 2. latest reset source. 3. latest wake source. table 13-7. pm register memory map offset register register name access reset 0x000 main clock control mcctrl read/write 0x00000000 0x004 cpu clock select cpusel read/write 0x00000000 0x008 hsb clock select hsbsel read-only 0x00000000 0x00c pba clock select pbasel read/write 0x00000000 0x010 pbb clock select pbbsel read/write 0x00000000 0x014 - 0x01c reserved 0x020 cpu mask cpumask read/write 0x00000003 0x024 hsb mask hsbmask read/write 0x0000007f 0x028 pba mask pbamask read/write 0x00007fff 0x02c pbb mask pbbmask read/write 0x0000003f 0x030- 0x03c reserved 0x040 pba divided mask pbadi vmask read/write 0x000000ff 0x044 - 0x050 reserved 0x054 clock failure detector control cfdctrl read/write 0x00000000 0x058 unlock register unlock write-only 0x00000000 0x05c - 0x0bc reserved 0x0c0 pm interrupt enable register ier write-only 0x00000000 0x0c4 pm interrupt disable register idr write-only 0x00000000 0x0c8 pm interrupt mask register imr read-only 0x00000000 0x0cc pm interrupt status register isr read-only 0x00000000 0x0d0 pm interrupt clear register icr write-only 0x00000000 0x0d4 status register sr read-only 0x00000000 0x0d8 - 0x15c reserved 0x160 peripheral power control register ppcr read/write 0x00000002 0x164 - 0x17c reserved 0x180 reset cause register rcause read-only - (2) 0x184 wake cause register wcause read-only - (3) 0x188 asyncronous wake enable awen read/write 0x00000000 0x18c - 0x3f4 reserved 0x3f8 configuration register config read-only 0x00000043 0x3fc version register version read-only - (1)
165 32099a?avr32?06/09 at32uc3l 13.7.1 main clock control name: mcctrl access type: read/write offset: 0x000 reset value: 0x00000000 ? mcsel: main clock select note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ----- mcsel table 13-8. main clocks in at32uc3l. mcsel[2:0] main clock source 0 system rc oscillator (rcsys) 1 oscillator0 (osc0) 2dfll 3 120 mhz rc oscillator (rc120m)
166 32099a?avr32?06/09 at32uc3l 13.7.2 cpu clock select name: cpusel access type: read/write offset: 0x004 reset value: 0x00000000 ? cpudiv, cpusel: cpu di vision and clock select cpudiv = 0: cpu clock equals main clock. cpudiv = 1: cpu clock equals main clock divided by 2 (cpusel+1) . note that if cpudiv is written to 0, cpusel should also be written to 0 to ensure correct operation. also note that writing this register clears poscsr.ckrdy. the register mu st not be re-written until ckrdy goes high. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 cpudiv - - - - cpusel
167 32099a?avr32?06/09 at32uc3l 13.7.3 hsb clock select name: hsbsel access type: read offset: 0x008 reset value: 0x00000000 this register is read-only and it s content is alwa ys equal to cpusel 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 hsbdiv - - - - hsbsel
168 32099a?avr32?06/09 at32uc3l 13.7.4 pbx clock select name: pbxsel access type: read/write offset: 0x008-0x00c reset value: 0x00000000 ? pbdiv, pbsel: pbx division and clock select pbdiv = 0: pbx clock equals main clock. pbdiv = 1: pbx clock equals main clock divided by 2 (pbsel+1) . note that if pbdiv is written to 0, pbsel should also be written to 0 to ensure correct operation. also note that writing this register clears sr.ckrdy. the register must not be re-written until sr.ckrdy goes high. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 pbdiv - - - - pbsel
169 32099a?avr32?06/09 at32uc3l 13.7.5 clock mask name: cpumask/hsbmask/pbamask/pbbmask access type: read/write offset: 0x020-0x02c reset value: - ? mask: clock mask if bit n is cleared, the clock for module n is stopped. if bit n is set, the clock for module n is enabled according to the cur rent power mode. the number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in table 13-9 . 31 30 29 28 27 26 25 24 mask[31:24] 23 22 21 20 19 18 17 16 mask[23:16] 15 14 13 12 11 10 9 8 mask[15:8] 76543210 mask[7:0] table 13-9. maskable module clocks in at32uc3l. bit cpumask hsbmask pbamask pbbmask 0 ocd pdca pdca flashcdw 1 - flashcdw intc hmatrix 2- sau pm sau 3 - pbb bridge scif - 4 - pba bridge ast - 5 - peripheral event system wdt - 6- - eic - 7- - freqm - 8- - gpio - 9 - - usart0 - 10 - - usart1 - 11 - - usart2 -
170 32099a?avr32?06/09 at32uc3l note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 12 - - usart3 - 13 - - spi - 14 - - twim0 - 15 - - twim1 - 16 - - twis0 - 17 - - twis1 - 18 - - pwma - 19 - - tc0 - 20 - - tc1 - 21 - - adcifb - 22 - - acifb - 23 - - cat - 24 - - gloc - 25 - - aw - 31:25---- table 13-9. maskable module clocks in at32uc3l. bit cpumask hsbmask pbamask pbbmask
171 32099a?avr32?06/09 at32uc3l 13.7.6 divided clock mask name: pbadivmask access type: read/write offset: 0x040 reset value: 0x000000ff ? mask: clock mask if bit n is cleared, the clock divided by 2 (mask+1) is stopped. if bit n is set, the clock divided by 2 (mask+1) is enabled according to the current power mode. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - ------ 15 14 13 12 11 10 9 8 -------- 76543210 - mask[6:0]
172 32099a?avr32?06/09 at32uc3l 13.7.7 clock failure detector control register name: cfdctrl access type: read/write offset: 0x054 reset value: 0x00000000 ? sfv: store final value 0: the register is read/write 1: the register is read-only, to protect against further accidental writes. ? ocpen: over clock protection enable 0: over clock protection is disabled 1: over clock protection is enabled ? cfden: clock failure detection enable 0: clock failure detector is disabled 1: clock failure detector is enabled note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details. 31 30 29 28 27 26 25 24 sfv------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------ocpencfden
173 32099a?avr32?06/09 at32uc3l 13.7.8 pm unlock register name: unlock access type: write-only offset: 0x058 reset value: 0x00000000 to unlock a write protected register, first write to the unlock register with the address of the register to unlock in the addr field and 0xaa in the key field. then, in the next pb access write to the register specified in the addr field. ?key: unlock key write this bit field to 0xaa to enable unlock. ? addr: unlock address write the address of the register to unlock to this field. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------ addr[9:8] 76543210 addr[7:0]
174 32099a?avr32?06/09 at32uc3l 13.7.9 interrupt enable register name: ier access type: write-only offset: 0x0c0 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
175 32099a?avr32?06/09 at32uc3l 13.7.10 interrupt disable register name: idr access type: write-only offset: 0x0c4 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
176 32099a?avr32?06/09 at32uc3l 13.7.11 interrupt mask register name: imr access type: read-only offset: 0x0c8 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
177 32099a?avr32?06/09 at32uc3l 13.7.12 interrupt status register name: isr access type: read-only offset: 0x0cc reset value: 0x00000000 0: the corresponding interrupt is cleared. 1: the corresponding interrupt is pending. this bit is cleared when the corresponding bit in icr is written to one. this bit is set when the corresponding interrupt occurs. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
178 32099a?avr32?06/09 at32uc3l 13.7.13 interrupt clear register name: icr access type: write-only offset: 0x0d0 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in isr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
179 32099a?avr32?06/09 at32uc3l 13.7.14 status register name: sr access type: read-only offset: 0x0d4 reset value: 0x00000000 ? ae: access error 0: no access error has occured. 1: a write to lock protected regist er without unlocking it has occured. ? ckrdy: clock ready 0: the cksel register has been written, and the new clock setting is not yet effective. 1: the synchronous clocks have frequencies as indicated in the cksel register. ? ocp: over clock 0: main clock is running at a legal frequency. 1: illegal frequency detected on main clock. main clock is now running on rc osc. ? cfd: clock failure detected 0: main clock is running corretly. 1: failure on main clock detected. main clock is now running on rc osc. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - ckrdy - - - - -
180 32099a?avr32?06/09 at32uc3l 13.7.15 peripheral power control register name : ppcr access type: read/write offset: 0x004 reset value: 0x00000000 ? rsttm : reset test mode 0: external reset not in test mode 1: external reset in test mode ? frc32 : force rc32 out 0: rc32 signal is not forced as output 1: rc32 signal is forced as output ? rstpun: reset pullup, active low 0: pull-up for external reset on 1: pull-up for external reset off 31 30 29 28 27 26 25 24 ppc[31:24] 23 22 21 20 19 18 17 16 ppc[23:16] 15 14 13 12 11 10 9 8 ppc[15:8] 76543210 ppc[7:0] table 13-10. peripheral power control bit name 0rstpun 1frc32 2rsttm 3 catrcmask 4 acifbcrcmask 5 adcifbrcmask 6 astrcmask 7 twis0rcmask 8 twis1rcmask 31:9 -
181 32099a?avr32?06/09 at32uc3l ? catrcmask : cat request clock mask 0: cat request clock is disabled 1: cat request clock is enabled ? acifbrcmask : acifb request clock mask 0: acifb request clock is disabled 1: acifb request clock is enabled ? adcifbrcmask : adcifb request clock mask 0: adcifb request clock is disabled 1: adcifb request clock is enabled ? astrcmask : ast request clock mask 0: ast request clock is disabled 1: ast request clock is enabled ? twis0rcmask : twis0 request clock mask 0: twis0 request clock is disabled 1: twis0 request clock is enabled ? twis1rcmask : twis1 request clock mask 0: twis1 request clock is disabled 1: twis1 request clock is enabled note that this register is protected by a lock. to write to this register the unlock register has to be written first. please r ef- ere to the unlock register description for details.
182 32099a?avr32?06/09 at32uc3l 13.7.16 reset cause name: rcause access type: read-only offset: 0x180 reset value: latest reset source ? bod33: brown-out 3.3v reset the cpu was reset due to the supply voltage being lower than the supply monitor 3.3v (sm33) threshold level. ? awirehard: awire hard reset the cpu was reset by the awire (reserved for test) ? awire: awire reset the cpu was reset by tthe awire ? jtaghard: jtag hard reset the chip was reset by the jtag system reset. ? ocdrst: ocd reset the cpu was reset because the res strobe in the ocd development control register has been written to one. ? sleep: sleep reset the cpu was reset because it woke up from shutdown sleep mode. ? jtag: jtag reset the chip was reset by the jtag system reset. ? wdt: watchdog reset the cpu was reset because of a watchdog time-out. ? ext: external reset pin the cpu was reset due to t he reset pin being asserted. ? bod: brown-out reset the cpu was reset due to the core supply voltage being lower than the brown-out threshold level. ? por power-on reset the cpu was reset due to the core supply voltage being lower than the power-on threshold level. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - bod33 awirehard awire jtaghard ocdrst 76543210 - sleep - jtag wdt ext bod por
183 32099a?avr32?06/09 at32uc3l 13.7.17 wake cause register name: wcause access type: read-only offset: 0x184 reset value: lateset wake source a bit in this register is set on wake up caused by the peripheral referred to in table 13-11 on page 183 . 31 30 29 28 27 26 25 24 wcause[31:24] 23 22 21 20 19 18 17 16 wcause[23:16] 15 14 13 12 11 10 9 8 wcause[15:8] 76543210 wcause[7:0] table 13-11. wake cause bit wake cause 0cat 1acifb 2 adcifb 3twi slave 0 4twi slave 1 5- 6- 7- 8- 9- 10 - 11 - 12 - 13 - 14 - 15 -
184 32099a?avr32?06/09 at32uc3l 16 eic 17 ast 31:18 - table 13-11. wake cause bit wake cause
185 32099a?avr32?06/09 at32uc3l 13.7.18 asynchronous wake up enable register name :awen access type: read/write offset: 0x188 reset value: 0x00000000 each bit in this register corresponds to an asynchronous wake up, according to table 13-12 on page 185 . 0: the correcponding wake up is disabled. 1: the corresponding wake up is enabled 31 30 29 28 27 26 25 24 awen[31:24] 23 22 21 20 19 18 17 16 awen[23:16] 15 14 13 12 11 10 9 8 awen[15:8] 76543210 awen[7:0] table 13-12. asynchronous wake up bit asynchronous wake up 0catwen 1acifbwen 2 adcifbwen 3twis0wen 4twis1wen 31:5 -
186 32099a?avr32?06/09 at32uc3l 13.7.19 configuration register name: config access type: read-only offset: 0x3f8 reset value: - this register shows the configuration of the pm. ? hsbpevc:hsb pevc clock implemented 0: hsbpevc not implemented. 1: hsbpevc implemented. ? ocp: over clock protection implemented 0: ocp not implemented. 1: ocp implemented. ? pbd: pbd implemented 0: pbd not implemented. 1: pbd implemented. ? pbc: pbc implemented 0: pbc not implemented. 1: pbc implemented. ? pbb: pbb implemented 0: pbb not implemented. 1: pbb implemented. ? pba: pba implemented 0: pba not implemented. 1: pba implemented. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 hsbpevc ocp - - pbd pbc pbb pba
187 32099a?avr32?06/09 at32uc3l 13.7.20 version register name: version access type: read-only offset: 0x3fc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
188 32099a?avr32?06/09 at32uc3l 13.8 module configuration the specific configuration for each pm instance is listed in the following tables.the module bus clocks listed here are connected to the system bus clocks. please refer to the ?synchronous clocks?, ?peripheral clock masking? and ?s leep modes? sections for details. table 13-13. power manager clock name module name clock name pm clk_pm table 13-14. register reset values register reset value version 0x00000411
189 32099a?avr32?06/09 at32uc3l 14. system control interface (scif) rev: 1.0.2.0 14.1 features ? controls integrated oscillators and digital frequency locked loop (dfll) ? supports crystal osc illator 3-16mhz (osc0) ? supports digital frequency locked loop 20-150mhz (dfll) ? supports 32khz ultra-low power oscillator (osc32k) ? supports 32khz rc oscillator (rc32k) ? integrated low-powe r rc oscillator (rcsys) ? generic clocks (gclk) with wide frequency range provided ? controls bandgap voltage reference through control and calibration registers ? controls brown-out detectors (bod) and supply monitors ? controls voltage regulator (vreg) behavior and calibration ? controls temperature sensor ? controls supply monito r 33 (sm33) operating modes and calibration ? controls 120mhz integrated rc oscillator (rc120m) ? four 32 bit general purpose backup registers 14.2 overview the system control interface (scif) controls the oscillato rs, dfll, generic clocks, bods, temperature sensor, vreg, and backup registers. 14.3 i/o lines description 14.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 14.4.1 i/o lines the scif provides a number of generic clock outputs, which can be connected to output pins, multiplexed with gpio lines. the programmer must first program the gpio controller to assign these pins to their peripheral function. if the i/o pins of the scif are not used by the application, they can be used for ot her purposes by the gpio controller. oscillator pins are also multiplexed table 14-1. i/o lines description pin name pin description type rc32out rc32 output at startup output xin0 crystal 0 input analog/digital xin32 crystal 32 input (primary location) analog/digital xin32_2 crystal 32 input (sec ondary location) analog/digital xout0 crystal 0 output analog xout32 crystal 32 output (primary location) analog xout32_2 crystal 32 output (secondary location) analog gclk4-gclk0 generic clock output output
190 32099a?avr32?06/09 at32uc3l with gpio. when osc illators are used, the related pins are controlled directly by the scif, over- riding gpio settings. 14.4.2 interrupt the scif interrupt request line is connected to the interrupt controller. using the scif interrupt requires the interrupt controller to be programmed first. 14.4.3 debug operation the scif module does not interact with debug operations. 14.4.4 clocks the scif controls all oscillators on the part. those oscillators can then be used as sources for for generic clocks (handled by the scif) and for the cpu and peripherals. (in this case, selec- tion of source is done by the power manager.) 14.5 functional description 14.5.1 oscillator (osc0) operation the main oscillator (osc0) is de signed to be used wit h an external 3 to 16mhz crystal and two biasing capacitors, as shown in figure 14-1 . the oscillator can be used for the main clock in the device, as described in the powe r manager chapte r. the oscillator can be used as source for the generic clocks, as described in ?generic clocks? on page 196 . the oscillator is disabled by de fault after reset. wh en the oscillator is disabled, the xin and xout pins can be used as general purpose i/os. when the oscillator is configured to use an external clock, the clock must be applied to t he xin pin while the xout pin can be used as a general purpose i/o. the oscillator can be enabled by writing to the oscen bits in oscctrl0. operation mode (external clock or crysta l) is chosen by writing to the mode field in oscctrl0. the oscillator is automatically switched off in certain sleep modes to reduce power consumption, as described in the power manager chapter. after a hard reset, or when waking up from a sleep mode that disa bled the oscillator, the oscilla- tor may need a certain amount of time to stabilize on the corr ect frequency. this start-up time can be set in the oscctrl0 register. the scif masks the oscilla tor outputs during the st art-up time, to ensure that no unstable clocks propagate to the digital logic. the osc0rdy bits in pclksr are automatically set and cleared according to the status of the oscillators. a zero to one transition on these bits can also be con- figured to generate an interrupt, as described in section 14.6.1 .
191 32099a?avr32?06/09 at32uc3l figure 14-1. oscillator connections. 14.5.2 32khz oscillator (osc32k) operation he 32khz oscillator operates as described for the osc illator above. the 32khz oscillator is used as source clock for the asynch ronous timer and the watchdog ti mer. the 32khz oscillator can be used as source for the generic clocks, as described in ?generic clocks? on page 196 . the oscillator is disabled by default, but can be enabled by writing osc32en in oscctrl32. the oscillator is an ultra-low power design and remains enabled in all sleep modes. while the 32khz oscillator is disabled, the xin3 2 and xout32 pins are available as general purpose i/os. when the oscillator is configured to work with an external clock (mode field in oscctrl32 register), the external clock must be connected to xin32 while the xout32 pin can be used as a general purpose i/o. the startup time of the 32khz oscillator can be set in the oscctrl32, after which osc32rdy in pclksr is set. an interrupt can be generated on a zero to one transition of osc32rdy. as a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 khz oscillator will keep running across resets, except power-on-reset. the 32khz oscillator also has a 1khz output. this is enabled by wr iting to en1k bit in oscctrl32 register. if the 32khz output clock is not needed when 1k is enabled, this can be disabled by writing zero to en32k in oscctrl32 register. en32k is set to one after reset. the 32khz oscillator has two possible set of pins. to select between them write to the pinsel bit in oscctrl32 register. the 32khz oscillator is not controlled by the sl eep controller, and will run in all sleep modes if enabled. 14.5.3 dfll operation the device contains one digital frequency locked loop (dfll). this is disabled by default, but can be enabled to provide a high frequency sour ce clock for synchronous and generic clocks. the dfll has a very short startup time and supports high frequency multiplication without the jit- ter associated with a pll. features: ? internal oscillator with no external components. xin xout c 2 c 1
192 32099a?avr32?06/09 at32uc3l ? 20-150mhz frequency ? short start-up time ? can operate standalone as high frequency programmable oscillator in open loop mode ? can operate as accurate frequency multiplier against a known frequency in closed loop mode. ? optional spread-spectrum clock generation. ? very high frequency multiplication supported - can generate all frequencies from 32khz. the dfll provides a high frequency clock with short startup time. the dfll can operate in both open loop mode and closed loop mode. in closed loop mode a low frequency clock with high accuracy can be used as reference clock to get high accuracy on the output frequency. to prevent unexpected writes due to software bugs, write access to the configuration registers are protected by a locking mechanism, for details please refer to the unlock register description. figure 14-2. dfllif block diagram 14.5.3.1 open loop operation when operating in open loop mode the output frequency of the dfll is set by the values written to the coarse and the fine fields in the df ll0conf register. take care when setting the value of the coarse and the fine fields, the output frequency must not exceed the maximum frequency of the device after the division in the clock generator. to set the dfllif in open loop mode set first write one to the en bit and then write zero to the mode bit in the dfll0conf register. it is possible to change the value of coarse and fine fields, and thereby the output frequency of the dfll, while the dfll is enabled. vco coarse fine 8 9 c l k _ d f l l mul 32 clk_ref frequency tuner dac dflllockc dflllocklostc dflllockf dflllocklostf dflloverflow dfllunderflow stepsize 6
193 32099a?avr32?06/09 at32uc3l 14.5.3.2 closed loop operation in closed loop mode the accuracy of the output frequency is limited by the accuracy of the refer- ence clock. set mode and en to one in dfll0conf register to enable the dfll in closed loop mode. the output fr equency of the dfll will be given by: the coarse and fine fields in dfll0conf regi ster are read-only in closed loop mode, and are controlled by the dfll to meet user specif ied frequency. the values in the coarse regis- ter when the closed loop mode is enabled is used by the frequency tuner as a starting point for the coarse value. setting the coarse to a val ue believed to be the correct will reduce the time needed to get a lock on the coarse value. to set up the dfllif first enable the dfll by writing one to en bit in dfll0conf register. then enable and select a reference clock (clk_dfllif_ref). clk_dfllif_ref is a gener ic clock, please refer to generic clocks chapter for details. then set the maximum step size allowed in finding the coarse and fine values by setting the cstep and fstep bits in dfll0step register. a small step size will ensure low overshoot on the output frequency, but will typically be slower. a high value might give a big overshoot, but will typically give faster locking. dfll0step.cstep and dfll0step.fstep should not be set higher than 50% of the maximum value of dfll0conf.coarse and dfll0conf.fine respec tively. setting the max step size to 50% of the max value will give a binary search. then set the value of fmul in dfll0mul register, care must be taken when choosing fmul so the output frequency does not exceed the maxi- mum frequency of the device. the locking of the frequency in closed loop mode is divided into three stages. in the coarse stage the control logic quickly finds the correct value for the coarse field in dfll0conf reg- ister and thereby setting the output frequency to a value close to the correct frequency. the dfll0lockc interrupt is issued when this is done. in the fine stage the control logic tunes the value in the fine field in the dfll0conf register so the output frequency very close to the desired frequency. the dfll0lockf interrupt is issued when this is done. in the accurate stage the dfll frequency tuning mechanism uses dithering on the fine bits to obtain an accu- rate output frequency. when the accurate frequency is obtained the dfll0locka interrupt is issued. the accurate stage will only be executed if dither bit in dfll0conf register is set to one. if dither is set to zero dfll0locka will never occur. if dithering is enabled, the fre- quency of the dithering is decided by a generic clock (clk_dfllif_dither). this clock has to be set up correctly before enabling dithering. please refer to the generic clocks chapter for details. the flow for finding the correct settings is shown in figure 14-3 on page 194 . when dithering is enable t he accuracy of the average outpu t frequency of the dfll will be higher. however, the fr equency will be alternatin g between two frequencies. if a fixed frequency is required, the dithering should not be enabled. the frequency tuner will automatically compensate for drift in the output frequency of the vco without losing either of the locks. if the fine re gister overflows or underflows, which should nor- mally not happen, but could occur due to larg e drift in temperature and voltage, all locks will be lost, and the coarse and fine values will be recalibrated as described earlier. when spread spectrum is enabled and the amplitude is high, an overflow/underflow is more likely to occur. if the reference clock stops, th e dfll0rcs interrupt will be asse rted. note that the detection of the clock stop will take long time . the dfll will enter open loop mode if it detects that the refer- ence clock has stopped. f vco fmul 2 16 ---------------- - f ref =
194 32099a?avr32?06/09 at32uc3l the ratio between the reference clock and the vco clock is measured automatically by the dfl- lif. the difference between this ratio and dfll0mul is stored in the multiplication ratio difference field (ratiodiff) in the dfll0ratio register. to get the result on the same form as dfll0mul, the error must be calculated as follows: where is the number of reference clock cycl es the dfllif is using for calculating the ratio. the dfll0ratio register is only updated every time the synchr onization (sync) bit in dfll0sync is written to one; refer to dfll0sync register description for details. figure 14-3. dfll closed loop state diagram figure 14-4. dfll locking in closed loop 14.5.3.3 enabling the dfll before configuring the dfll, only the en bit in the dfll0conf register should be written to one. writes to other bits in dfll0conf will be ignored. the dfll is now ready for configuration. error ratiodiff 2 numref --------------------------------- = 2 numref measure vco frequency calculate new coarse value dflllockc 0 calculate new fine value dflllockf 0 1 dflllocka 1 calculate new dithering dutycycle 0 compen- sate for drift 1 dither 1 compen- sate for drift 0 f o f t lockc t coarse t fine lockf f overflow f coarse f fine locka t accurate
195 32099a?avr32?06/09 at32uc3l 14.5.3.4 spread spectrum generator (ssg) when the dfll is used as the main clock source for the chip, the emi ra diated from the chip will be synchronous to the vco frequency. to provide better em c capabilities the dfll can provide a clock with the energy spread in the frequency domain. this is done by adding or subtracting values from the fine value. enable the ssg by writing one to en bit field in the dfll0ssg register. a generic clock sets the rate at which the ssg changes the frequency of the dfll clock to gen- erate a spread spectrum (clk_dfllif_dither). this is the same clock used by the dithering mechanism. the frequency of this clock should be higher than clk_dfllif_ref to ensure that the dfllif can lock. please refer to the generic clocks section for details. optionally, the clock ticks can be qualified by a pseudorandom binary sequence (prbs) if the prbs bit in the dfll0ssg register is set. this reduces the modulation effect of clk_dfllif_dither frequency onto f vco . the amplitude of the frequency variation can be selected by setting the amplitude field in dfll0ssg register. if the amplitude is set to zero the ssg will toggle on the lsb of the fine value, setting amplitude to one the ssg will add the sequence {1,- 1, 0} to the fine value on every source clock cycle. the step size of the ssg is se t in the stepsize bit field in th e dfll0ssg regist er. setting the stepsize to zero or one will result in a step size equal to one. if the step size is set to n the out- put value from the ssg will be incremented/decremented by n on every tick of the source clock. figure 14-5. spread spectrum generator block diagram. the spread spectrum generator can operate both in open and closed loop mode. 14.5.3.5 start-up the dfll has very short start-up time. when waking up from a sleep mode where the dfll has been turned off, and the dfll clock was the main clock befo re going to sleep, the dfll will be re-enabled and start running with the same configuration as before going to sleep even if the ref- erence clock is not available. the locks will be lost. when the re ference clock has restarted, the coarse lock will be set quickly since the coarse value starts close to the correct value. the fine lock will be set as soon as the output clock is running at the correct frequency. 14.5.3.6 internal synchronization due to multiple clock domains in the dfllif, values in configuration registers need to be syn- chronized to other clock domains. thus, before writing to a dfllif configuration register check pseudorandom binary sequence spread spectrum generator fine 9 to dac gclk amplitude, stepsize
196 32099a?avr32?06/09 at32uc3l that the dfll0rdy bit in pclksr register is high before writing. a write to a configuration reg- ister while dfll0rdy is low will be ignored. 14.5.4 generic clocks timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. the scif contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies. each generic clock module runs from either clock source listed in the table on table 14-9 on page 234 . the selected source can optionally be divided by any even integer up to 512. each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the sleep controller in the power manager. figure 14-6. generic clock generation 14.5.4.1 enabling a generic clock a generic clock is enabled by writing the cen bi t in gcctrl to one. each generic clock can individually select a clock source by setting the oscsel bits. the source clock can optionally be divided by writing diven to one and the division factor to div, resulting in the output frequency: f gclk = f src / (2*(div+1)) 14.5.4.2 disabling a generic clock the generic clock can be disabled by writing cen to zero or entering a sleep mode that disables the pb clocks. in either case, the generic clock will be switched off on the first falling edge after the disabling event, to en sure that no glitches o ccur. if cen is written to zero, the bit will still read as one until the next falling edge occurs, and the cl ock is actually switched off. when writing cen to zero, the other bits in gcctrl should not be changed until cen reads as zero, to avoid glitches on the generic clock. when the clock is disabled, both the prescaler and output are reset. divider oscsel generic clock div 0 1 diven mask cen sleep controller
197 32099a?avr32?06/09 at32uc3l 14.5.4.3 changing clock frequency when changing generic clock frequency by writing gcctrl, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. this prevents glitches during the transition. 14.5.4.4 generic clock implementation in at32uc3l, there are six generic clocks. these are allocated to different functions as shown in table 14-2 . note that only gclk4-0 are routed out. note: 1. gclk5 is not routed out. 14.5.5 brown out detection (bod) the brown-out detector (bod) monitors the vddcore supply pin and compares the supply voltage to the brown-out detection level, as set in bod.level. the bod is disabled by default, but can be enabled either by software or by flash fuses. the brown-out detector can either gen- erate an interrupt or a reset when the supply voltage is below the brown-out detection level. in any case, the bod output is available in bit pclksr.bodet bit. note that any change to the bo d.level field of the bod regist er should be done with the bod deactivated to avoid spurious re set or interrupt. when turned-o n, the bod output will be masked during one half of a rcosc clock cycle and tw o main clocks cycles to avoid false results see electrical characterist ics for parametric details. although it is not reco mmended to override default factory settings, it is still possible to override these default values by writing to those register s. to prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the unlock register description. 14.5.6 bandgap the flash memory, the brown-out detector (bod) and the temperature sensor need a stable voltage reference to operate. this reference voltage is provided by an internal bandgap voltage reference. this reference is automatically turned on at startup and turned off during deepstop and static sleep modes to save power. the bandgap voltage reference is calibrated through the bgcr.calib field. this field is loaded after a power on reset with default values stored in factory-programmed flash fuses. table 14-2. generic clock allocation clock number function 0 dfllif main reference and gclk0 pin (clk_dfllif_ref) 1 dfllif dithering and ssg reference and gclk1 pin (clk_dfllif_dither) 2 ast and gclk2 pin 3 pwma and gclk3 pin 4 cat, acifb and gclk4 pin 5 (1) gloc
198 32099a?avr32?06/09 at32uc3l it is not recommended to override default factory settings as it may prevent correct operation of the flash and bod. to prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the unlock register description 14.5.7 voltage regulator (vreg) the embedded voltage regulator can be used to provide the vddcore voltage from the vddin. it is controlled by the vregcr register. th e voltage regulator is turned on by default at startup but can be turned off by software if an external power is provided on the vddcore the voltage regulator has its own voltage reference that is calibrated through the vregcr.calib field. this fiel d is loaded after a power on reset with default values stored in factory-programmed flash fuses. although it is not reco mmended to override default factory settings, it is still possible to override these default values by writing to those register s. to prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the unlock register description. the voltage regulator interface also includes control bits for the por33 (power-on reset 3.3v) detector that monitors the vddin voltage during power-up. the por33 is on by default but can be turned off by software to reduce power consumption. the 3.3v supply monitor can then be used to monitor the vddin power supply (see page 198 ). the rc32k oscillator must be tu rned on to disabled the por 33. once the por33 had ben dis- abled, the rc32k oscillator can be turned off again. note that if the por33 is re-enabled later, it will generate a reset. 14.5.8 system rc oscillator (rcsys) the system rc oscillator (rcsys) has a 3 cycles star tup time, and is always available except in static mode. the system rc oscilla tor operates at a nominal freq uency of 115 khz, and is cali- brated using the rccr.calib calibration field. after a power on reset, the rccr.calib field is loaded with a factory defined value stored in the flash fuses. although it is not reco mmended to override default factory settings, it is still possible to override these default values by writing to the rccr.ca lib field. to prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the unlock register description. 14.5.9 3.3 v supply monitor (sm33) the 3.3v supply monitor (sm33) is a specific vo ltage detector for the vd din voltage. it will indi- cate if the vddin voltage is above the minimum required input voltage for the voltage regulator (typically 1.75v). the user can choose to generat e either a reset or an interrupt when the vddin voltage drops below this limit. in order to reduce power consumption, the sm33 can operate in ?sampling mode?. in sampling mode, the sm33 is periodically turned on for a small time (just enough for making the measure- ment) then it is turned off for a longer time. by default, the sm33 operates in ?sampling? mode during deepstop and static mode and in continuous mode for other sleep modes. sampling mode can also be forced during sleep modes other than deepstop and static and during normal operation.
199 32099a?avr32?06/09 at32uc3l the user can select the period of the checks in ?sampling? mode through the sm33.samp- freq. the sampling mode uses the 32khz rc oscillator (rc32k) as a clock. the 32khz rc oscillator is turned on automati cally with sampling mode is used the por33 can be turned off by software to reduce power consumption, please refer to the volt- age regulator section for details. the sm33 can then be used to monitor the vddin power supply. 14.5.10 temperature sensor the temperature sensor is connected to the adc channel 7. it is enabled by writing one to the en bit in the tsens register. temperature sensor does not have calibration register please refer to the electrical characteristics chapter for temperature/voltage curves. 14.5.11 120mhz rc oscillator (rc120m) the 120mhz rc oscillator can be used for the main clock in the device, as described in the power manager chapter. the oscillator can be used as s ource for the generic clocks, as described in ?generic clocks? on page 196 . the clock is enabled by writing one to en bit in rc120mcr register and disabled by writing zero to the en bit. the oscillator is automatically sw itched off in certain sleep mode s to reduce po wer consumption, as described in the power manager chapter. 14.5.12 backup registers four 32-bit registers with are available to keep values when the chip is in shutdown mode. those registers will keep th eir content even when the vddc ore, vddin and vddio powers are removed. the backup registers can be accessed by reading and writing br0, br1, br2 and br3 registers. after writing to one of the backup registers the user must wait until the backup register interface ready (brifardy) bit in the pclksr register is set before writing to another backup register. writes to the backup register while brifardy is zero will be discarded. the brifardy can also trigger an interrupt if the corresponding bit is set in the imr register. after powering up the device the backup regi ster interface valid (brifavalid) bit in the pclksr register is cleared, indicating that the contents of the backup registers has not been written and contains the reset value. after writing one of the backup registers the brifavalid bit is set. during writes to the backup registers (when brif ardy is zero) brifavalid will be zero. if a reset occurs when the brifardy is zero, brifavalid will be cleared after the reset, indicating that the contents of the backup regist ers are not valid. if brifardy was one when the reset occurred, brifavalid w ill be one and the contents are the same as before the reset. the user must ensure that brifavalid and brifardy is both set before reading the backup register values. 14.5.13 32khz rc oscillator (rc32k) the 32khz rc oscillator (rc32k) is enabled by default after reset, and output on pb04. the clock is available on the pad until the bit pm.ppcr.rc32out has been cleared in the power manager or a differ ent peripheral functi on has been chos en on port pb04 (p ort pb04 will start with peripheral function ?f? by default).
200 32099a?avr32?06/09 at32uc3l the rc32k can be used as source for the generic clocks, as described in ?generic clocks? on page 196 . the clock is enabled by writing one to en bit in rc32kcr register and disabled by writing zero to the en bit. the oscillator is also aut omatically turned on when the sampling mode is requested for th e sm33. in this case, clearing the en bit will not stop the rc32k until the sam- pling mode is no longer requested. 14.5.14 interrupts the scif has 14 separate interrupt sources: ? ae - access error: ? set when a protected scif register was accessed without first being correctly unlocked. ? brifardy - backup register interface ready. ? set on 0 to 1 transition on the pclksr.brifardy bit is detected. ? dfll0rcs - dfll reference clock stopped: ? set on 0 to 1 transition on the pclksr.dfllrcs bit is detected. ? dfll0rdy - dfll ready: ? set on 0 to 1 transition on the pclksr.dfllrdy bit is detected. ? dfll0locklosta - dfll lock lost on accurate value: ? set on 0 to 1 transition on the pclksr.dflllocklosta bit is detected. ? dfll0locklostf - dfll lock lost on fine value: ? set on 0 to 1 transition on the pclksr.dflllocklostf bit is detected. ? dfll0locklostc - dfll lock lost on coarse value: ? set on 0 to 1 transition on the pclksr.dflllocklostc bit is detected. ? dfll0locka - dfll locked on accurate value: ? set on 0 to 1 transition on the pclksr.dflllocka bit is detected. ? dfll0lockf - dfll locked on fine value: ? set on 0 to 1 transition on the pclksr.dflllockf bit is detected. ? dfll0lockc - dfll locked on coarse value: ? set on 0 to 1 transition on the pclksr.dflllockc bit is detected. ? boddet - brown out detection: ? set on 0 to 1 transition on the pclksr.boddet bit is detected. ? sm33det - supply monitor 3.3v detector: ? set on 0 to 1 transition on the pclksr.sm33det bit is detected. ? vregok - voltage regulator ok: ? set on 0 to 1 transition on the pclksr.vregok bit is detected. ? oscrdy - oscready: ? set on 0 to 1 transition on the pclksr.oscrdy bit is detected. ? osc32rdy - 32khz oscillator ready: ? set on 0 to 1 transition on the pclksr.osc32rdy bit is detected. the interrupt sources will generate a interrupt request if the corresponding bit in the interrupt mask register (imr) is set. bits in imr are set by writing a one to the corresponding bit in the
201 32099a?avr32?06/09 at32uc3l interrupt enable register (ier), and cleared by writing a one to the corresponding bit in the interrupt disable register (idr). the interrupt request remains active until the corresponding bit in the interrupt status register (isr) is cleared by writing a one to the corresponding bit in the interrupt clear register (icr).
202 32099a?avr32?06/09 at32uc3l 14.6 user interface table 14-3. scif register memory map offset register register name access reset 0x0000 interrupt enable register ier write-only 0x00000000 0x0004 interrupt disable register idr write-only 0x00000000 0x0008 interrupt mask register imr read-only 0x00000000 0x000c interrupt status register isr read-only 0x00000000 0x0010 interrupt clear register icr write-only 0x00000000 0x0014 power and clocks status register pclksr read-only 0x00000000 0x0018 unlock register unlock write-only 0x00000000 0x001c oscillator control register oscctrl0 read/write 0x00000000 0x0020 oscillator 32 control register oscctrl32 read/write 0x00000004 0x0024 dfll config register dfll0conf read/write 0x00000000 0x0028 dfll multiplier regist er dfll0mul write-only 0x00000000 0x002c dfll step register dfll0step write-only 0x00000000 0x0030 dfll spread spectrum generator control register dfll0ssg write-only 0x00000000 0x0034 dfll ratio register dfll0ratio read-only 0x00000000 0x0038 dfll synchronization register dfll0sync write-only 0x00000000 0x003c bod level register bod read/write 0x00000000 0x0040 bandgap calibration register bgcr read/write 0x00000000 0x0044 voltage regulator calibration register vregcr read/write 0x00000000 0x0048 system rc oscillator calibrat ion register rccr read/write 0x00000000 0x004c supply monitor 33 calibration register sm33 read/write 0x00000000 0x0050 temperature sensor calibrati on register tsens read/write 0x00000000 0x0058 120mhz rc oscillator contro l register rc120mcr read/write 0x00000000 0x005c-0x0068 backup registers br read/write 0x00000000 0x006c 32khz rc oscillator control register rc32kcr read/write 0x00000000 0x0070-0x0080 generic clock control gcctrl read/write 0x00000000 0x03c8 oscillator 0 version register osc0version read-only - (1) 0x03cc 32 khz oscillator version register osc32version read-only - (1) 0x03d0 dfll version register dfllifversion read-only - (1) 0x03d4 bod version register bodifaversion read-only - (1) 0x03d8 voltage regulator version register vregifbversion read-only - (1) 0x03dc system rc oscillator version register rcoscifaversion read-only - (1) 0x03e0 3.3v supply monitor version register sm33ifaversion read-only - (1) 0x03e4 temperature sensor version register tsensifaversion read-only - (1)
203 32099a?avr32?06/09 at32uc3l note: 1. the reset value is device specific. please refer to th e module configuration section at the end of this chapter. 0x03ec 120mhz rc oscillator version register rc120mifaversion read-only - (1) 0x03f0 backup register interface version register brifaversion read-only - (1) 0x03f4 32khz rc oscillator version register rc32kifaversion read-only - (1) 0x03f8 generic clock version register gclkversion read-only - (1) 0x03fc scif version register version read-only - (1) table 14-3. scif register memory map offset register register name access reset
204 32099a?avr32?06/09 at32uc3l 14.6.1 interrupt enable register name: ier access type: write-only offset: 0x0000 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
205 32099a?avr32?06/09 at32uc3l 14.6.2 interrupt disable register name: idr access type: write-only offset: 0x0004 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
206 32099a?avr32?06/09 at32uc3l 14.6.3 interrupt mask register name: imr access type: read-only offset: 0x0008 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
207 32099a?avr32?06/09 at32uc3l 14.6.4 interrupt status register name: isr access type: read-only offset: 0x000c reset value: 0x00000000 0: the corresponding interrupt is cleared. 1: the corresponding interrupt is pending. this bit is cleared when the corresponding bit in icr is written to one. this bit is set when the corresponding interrupt occurs. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
208 32099a?avr32?06/09 at32uc3l 14.6.5 interrupt clear register name: icr access type: write-only offset: 0x0010 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in isr. 31 30 29 28 27 26 25 24 ae------- 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
209 32099a?avr32?06/09 at32uc3l 14.6.6 power and clocks status register name: pclksr access type: read-only offset: 0x0014 reset value: 0x00000000 ? brifavalid: backup register interface valid 0: the values in the backup registers are not valid. 1: the values in the backup registers are valid. ? brifardy: backup register interface ready 0: the backup register interface is busy updating th e backup registers. writes to brn will be discarded. 1: the backup register interface is ready to accept new writes to the backup registers. ? dfllrcs: dfll0 reference clock stopped 0: the dfll0 reference clock is running, or has never been enabled. 1: the dfll0 reference clock has stopped. ? dfll0rdy: dfll0 synchronization ready 0: read or write to dfll0 registers is invalid 1: read or write to dfll0 registers is valid ? dflllocklosta: dfll lock lost on accurate value 0: dfll has not lost its accurate lock or has never been enabled. 1: dfll has lost its accurate lock, either by disabling the dfll or due to faulty operation. ? dflllocklostf: dfll lock lost on fine value 0: dfll has not lost its fine lock or has never been enabled. 1: dfll has lost its fine lock, either by disabling the dfll or due to faulty operation. ? dflllocklostc: dfll lock lost on coarse value 0: dfll has not lost its coarse lock or has never been enabled. 1: dfll has lost its coarse lock, either by disabling the dfll or due to faulty operation. ? dflllocka: dfll locked on accurate value 0: dfll is unlocked on accurate value. 1: dfll is locked on accurate value, and is ready to be selected as clock source with an accurate output clock. ? dflllockf: dfll locked on fine value 31 30 29 28 27 26 25 24 -brifavalid------ 23 22 21 20 19 18 17 16 -------brifardy 15 14 13 12 11 10 9 8 dfll0rcs dfll0rdy dfll0lock losta dfll0lock lostf dfll0lock lostc dfll0lock a dfll0lock f dfll0lock c 76543210 boddet sm33det vregok - - - osc0rdy osc32rdy
210 32099a?avr32?06/09 at32uc3l 0: dfll is unlocked on fine value. 1: dfll is locked on fine value, and is ready to be select ed as clock source with a highly accurate output clock. ? dflllockc: dfll locked on coarse value 0: dfll is unlocked on coarse value. 1: dfll is locked on fine value, and is ready to be select ed as clock source with medi um accuracy on the output clock. ? boddet: brown out detection 0: no bod event. 1: bod has detected that power suppl y is going below bod reference value. ? sm33det: supply monitor 3.3v detector 0: sm33 not enabled or the supply voltage is above the sm33 threshold. 1: sm33 enabled and the supply voltage is below the sm33 threshold. ? vregok: voltage regulator ok 0: voltage regulator not enabled or not ready. 1: voltage regulator has reached its output threshold value after being enabled. ? osc0rdy: osc0 ready 0: oscillator not enabled or not ready. 1: oscillator is stable and ready to be used as clock source. ? osc32rdy: 32 khz oscillator ready 0: oscillator 32 not enabled or not ready. 1: oscillator 32 is stable and ready to be used as clock source.
211 32099a?avr32?06/09 at32uc3l 14.6.7 unlock register name: unlock access type: write-only offset: 0x0018 reset value: 0x00000000 to unlock a write protected register, first write to the unlock r egister with the address of the re gister to unlock in the addr field and 0xaa in the key field. then, in the next pb ac cess write to the register specified in the addr field. ? key: unlock key write this bit field to 0xaa to enable unlock. ? addr: unlock address write the address of the register to unlock to this field. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------ addr[9:8] 76543210 addr[7:0]
212 32099a?avr32?06/09 at32uc3l 14.6.8 oscillator control register name: oscctrl0 access type: read/write offset: 0x001c reset value: 0x00000000 ?oscen 0: disable the oscillator. 1: enable the oscillator ? startup: oscillator startup time select startup time for the oscillator. ? agc: automatic gain control for test purposes ? gain: gain set the gain for the oscillator ? mode: oscillator mode 0: external clock connected on xin, xout can be used as an i/o (no crystal) 1: crystal is connected to xin/xout 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------oscen 15 14 13 12 11 10 9 8 ----- startup 76543210 ----agc gain mode table 14-4. startup time for o scillators 0 and 1 startup number of system rc oscillator clock cycle approximative equivalent time (rcsys = 115 khz) 00 0 1 64 560 us 2128 1.1ms 32048 18ms 44096 36ms 58192 71ms 6 16384 142 ms 7 reserved reserved
213 32099a?avr32?06/09 at32uc3l note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details.
214 32099a?avr32?06/09 at32uc3l 14.6.9 32khz oscillator control register name: oscctrl32 access type: read/write offset: 0x0020 reset value: 0x00000004 note: this register is only reset by power-on reset ? reserved this bit should always be written to zero. ? startup: oscillator startup time select startup time for 32 khz oscillator 31 30 29 28 27 26 25 24 reserved ------- 23 22 21 20 19 18 17 16 ----- startup 15 14 13 12 11 10 9 8 ----- mode 76543210 ----en1ken32kpinselosc32en table 14-5. startup time for 32 khz oscillator startup number of rc oscillator clock cycle approximative equivalent time (rcosc = 115 khz) 00 0 1128 1.1ms 2 8192 72.3 ms 3 16384 143 ms 4 65536 570 ms 5 131072 1.1 s 6 262144 2.3 s 7 524288 4.6 s
215 32099a?avr32?06/09 at32uc3l ? mode: oscillator mode ? en1k: enable the 1 khz output 0: 1 khz output is disabled 1: 1 khz output is enabled ? en32k: enable the 32 khz output 0: 32 khz output is disabled 1: 32 khz output is enabled ? pinsel: select pins used for 32 khz crystal oscillator 0: default pins 1: alternate pins: xin32_2 pin is used instead of xin32 pin, xout32_2 pin is used instead of xout32 ? osc32en: enable the 32 khz oscillator 0: 32 khz oscillator is disabled 1: 32 khz oscillator is enabled table 14-6. operation mode for 32 khz oscillator mode description 0 external clock connected to xin32, xout32 can be used as i/o (no crystal) 1 crystal mode. crystal is connected to xin32/xout32. 2reserved 3reserved 4 crystal and high current mode. cryst al is connected to xin32/xout32. 5reserved 6reserved 7reserved
216 32099a?avr32?06/09 at32uc3l 14.6.10 dfll0 configuration register name: dfll0conf access type: read/write offset: 0x0024 reset value: 0x00000000 ? coarse: coarse calibration register value set the value of the coarse calibration register. if in closed loop mode, this field is read-only. ? fine: fine calibration register value set the value of the fine calibration register. if in closed loop mode, this field is read-only. ? dither: enable dithering 0: the fine lsb input to the vco is constant 1: the fine lsb input to the vco is dithered to achieve fractional approximation to the correct multiplication ratio ? mode: mode selection 0: dfll in open loop operation. 1: dfll in closed loop operation. ? en: enable 0: dfll is disabled. 1: dfll is enabled. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 coarse 23 22 21 20 19 18 17 16 -------fine 15 14 13 12 11 10 9 8 fine 76543210 -----dithermodeen
217 32099a?avr32?06/09 at32uc3l 14.6.11 dfll0 multiplier register name: dfll0mul access type: read/write offset: 0x0028 reset value: 0x00000000 ? dfllmul: dfll multiply factor this field determines the ratio of the dfll output frequency to the source clock freque ncy. the 16 most significant bits are us ed as the integer part, while the 16 least signifi cant bits are used as the fractional part. in open loop mode, writing to this register has no effect. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 dfllmul[31:24] 23 22 21 20 19 18 17 16 dfllmul[23:16] 15 14 13 12 11 10 9 8 dfllmul[15:8] 76543210 dfllmul[7:0]
218 32099a?avr32?06/09 at32uc3l 14.6.12 dfll0 maximum step register name: dfll0step access type: read-only offset: 0x002c reset value: 0x00000000 ? fstep: fine maximum step this indicated the maximum step size during fine adjustment in closed-loop mode. when adjusting to a new frequency, the expected overshoot of that freq uency depends on this step size. ? cstep: coarse maximum step this indicated the maximum step size during coarse adjustment in closed-loop mode. when adjusting to a new frequency, the expected overshoot of that freq uency depends on this step size. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 -------fstep[8] 23 22 21 20 19 18 17 16 fstep[7:0] 15 14 13 12 11 10 9 8 -------- 76543210 cstep[7:0]
219 32099a?avr32?06/09 at32uc3l 14.6.13 dfll0 spread spectrum generator control register name: dfll0ssg access type: read/write offset: 0x0030 reset value: 0x00000000 ? stepsize: ssg step size. sets the step size of the spread spectrum. if set to zero or one, the value added to the fine bits will be incremented/decremented with one on every positive edge of the input clock. if set to n , the value added to the fine bits will be incremented/decremented with n on every positive edge of the input clock. ? amplitude: ssg amplitude. sets the amplitude of the spread spectrum. if set to zero, only the lsb of the fine bits will be affected. if set to one, the sequence {1, 0, -1, 0} will be added to fine bits, etc. ? prbs: pseudo random bit sequence 0: each spread spectrum frequency is applied at constant intervals 1: each spread spectrum frequency is applied at pseudo-random intervals ? en: enable 0: ssg is disabled. 1: ssg is enabled. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 recal 23 22 21 20 19 18 17 16 - - - stepsize 15 14 13 12 11 10 9 8 - - - amplitude 76543210 ------prbsen
220 32099a?avr32?06/09 at32uc3l 14.6.14 dfll0 ratio register name: dfll0ratio access type: read-only offset: 0x0034 reset value: 0x00000000 ? ratiodiff: multiplica tion ratio difference in closed-loop mode, these fields indicate the error of the ratio between the vco frequency and the reference clock frequency: error = ratiodiff >> numref ? numref: numerical reference 31 30 29 28 27 26 25 24 ratiodiff[15:8] 23 22 21 20 19 18 17 16 ratiodiff[7:0] 15 14 13 12 11 10 9 8 - ------- 76543210 - -- numref[4:0]
221 32099a?avr32?06/09 at32uc3l 14.6.15 dfll0 synchronization register name: dfll0sync access type: write-only offset: 0x0038 reset value: 0x00000000 ? sync: synchronization to be able to read the current value of dfll0conf or dfll0ratio in closed-loop mode, this bit should be written to one. the updated value is available in dfll0conf and dfll0ratio when pclksr.dfll0rdy goes high. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------sync
222 32099a?avr32?06/09 at32uc3l 14.6.16 bod control register name: bod access type: read/write offset: 0x003c reset value: 0x00000000 ? sfv: store final value 0: the register is read/write 1: the register is read-only, to protect against further accidental writes. ? fcd: bod fuse calibration done set to 1 when the ctrl, hyst and level field has been updated by the flash fuse s after power-on re set or flash fuses update. if one, the ctrl, hyst and level values will not be updated again by flash fuses. can be cleared to allow subsequent over writing of the value by flash fuses. ? ctrl: bod control ? hyst: bod hysteresis 0: no hysteresis 1: hysteresis on. ? level: bod level this field sets the triggering threshold of the bod. se e electrical characteristics for actual voltage levels. note that any change to the level field of the bod register should be done with the bod deactivated to avoid spurious reset or interrupt. 31 30 29 28 27 26 25 24 sfv------- 23 22 21 20 19 18 17 16 -------fcd 15 14 13 12 11 10 9 8 ------ ctrl 76543210 - hyst level table 14-7. operation mode for bod ctrl description 0 bod is off 1 bod is enabled and can reset the chip 2 bod is enabled and but cannot reset the chip. only interrupt will be sent to interrupt controller, if enabled in the imr register. 3reserved
223 32099a?avr32?06/09 at32uc3l note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details.
224 32099a?avr32?06/09 at32uc3l 14.6.17 bandgap calibration register name: bgcr access type: read/write offset: 0x0040 reset value: 0x00000000 ? sfv: store final value 0: the register is read/write 1: the register is read-only, to protect against further accidental writes. ? fcd: flash calibration done set to 1 when the calib field has been updated by the fl ash fuses after power-on reset or when the flash fuses are reprogrammed. the calib field will not be updated again by the flash fuses until a new power-on reset or the fcd field is written to zero. ? calib: calibration value calibration value for bandgap. see electrical characteristics for voltage values. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 sfv------- 23 22 21 20 19 18 17 16 -------fcd 15 14 13 12 11 10 9 8 -------- 7654321 0 ----- calib
225 32099a?avr32?06/09 at32uc3l 14.6.18 voltage regulator calibration register name: vregcr access type: read/write offset: 0x0044 reset value: 0x00000000 ? sfv: store final value 0: the register is read/write 1: the register is read-only, to protect against further accidental writes. ? intpd: internal pulldown this bit is used for test purposes only. 0: the voltage regulator output is not pulled to ground 1: the voltage regulator output has a pulldown to ground ? por33mask: power-on r eset 3.3v output mask 0: power-on reset 3.3v is not masked 1: power-on reset 3.3v is masked ? por33status: power-on reset 3.3v status 0: power-on reset 3.3v is currently disabled 1: power-on reset 3.3v is currently enabled this bit is a read-only bit. writing to this bit has no effect. ? por33en: power-on reset 3.3v enable 0: disable the 3.3v por detector 1: enable the 3.3v por detector ? deepdis: disable regulator deep mode 0: regulator will enter deep mode in low-power sleep modes for lower power consumption 1: regulator will stay in full-power mode in all sleep modes for shorter start-up time ? fcd: flash calibration done set to 1 when the calib field has been updated by the fl ash fuses after power-on reset or when the flash fuses are reprogrammed. the calib field will not be updated again by the flash fuses until a new power-on reset or the fcd field is written to zero. ? calib: calibration value calibration value for voltage regulator. see electrical characteristics for voltage values. ? on: voltage regulator on status 31 30 29 28 27 26 25 24 sfvintpd------ 23 22 21 20 19 18 17 16 - - - por33mask por33stat us por33en deepdis fcd 15 14 13 12 11 10 9 8 ---- calib 76543210 on vregok en - - selvdd
226 32099a?avr32?06/09 at32uc3l 0: the voltage regulator is currently turned off 1: the voltage regulator is currently turned on this bit is a read-only bit. writing to this bit has no effect. ? vregok: voltage regulator ok status 0: the voltage regulator is disabled or ha s not yet reached a stable output voltage 1: the voltage regulator has reached the output voltage threshold level after being enabled this bit is a read-only bit. writing to this bit has no effect ? en: enable the voltage regulator 0: the voltage regulator is disabled 1: the voltage regulator is enabled note : this bit is set to one after a power on reset ? selvdd: select vdd output voltage of the voltage regulator. see el ectrical characteristics for voltage values. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details.
227 32099a?avr32?06/09 at32uc3l 14.6.19 rc oscillator calibration register name: rccr access type: read/write offset: 0x0048 reset value: 0x00000000 ? fcd: flash calibration done set to 1 when calib fields has been updated by the flash fuse s after power-on reset, or after flash fuses are reprogrammed. the calib value will not be updated again by the flash fuses unti l a new power-on reset or the fcd field is written to zero. ? calib: calibration value calibration value for the rc oscillator. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------fcd 15 14 13 12 11 10 9 8 ------ calib[9:8] 76543210 calib[7:0]
228 32099a?avr32?06/09 at32uc3l 14.6.20 supply monitor 33 calibration register name: sm33 access type: read/write offset: 0x004c reset value: 0x00000000 ? sampfreq: sampling frequency selects the sampling mode frequency of the 3.3v supply monitor. in sampling mode, the sm33 performs a measurement every 2 (sampfreq+5) cycles of the internal 32khz rc oscillator. ? onsm: supply monitor on indicator 0: the supply monitor is off. 1: the supply monitor is on. this bit is read-only. writing to this bit has no effect. ? sfv: store final value 0: the register is read/write 1: the register is read-only, to protect against further accidental writes. ? fcd: flash calibration done set to 1 when calib fields has been updated by the flash fuse s after power-on reset, or after flash fuses are reprogrammed. the calib value will not be updated again by the flash fuses unti l a new power-on reset or the fcd field is written to zero. ? calib: calibration value calibration value for the sm33. ? fs: force sampling mode 0: sampling mode is enabled in deepstop and static mode only. 1: sampling mode is always enabled. ? ctrl: supply monitor control 31 30 29 28 27 26 25 24 ---- sampfreq 23 22 21 20 19 18 17 16 -----onsmsfvfcd 15 14 13 12 11 10 9 8 ---- calib 76543210 fs - - - ctrl
229 32099a?avr32?06/09 at32uc3l selects the operating mode for the sm33 note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. table 14-8. operation mode for sm33 ctrl description 0 sm33 is off 1 sm33 is enabled and can reset the chip 2 sm33 is enabled and but cannot reset the chip. only interrupt will be sent to interrupt controller, if enabled in the imr register. 3 sm33 is off
230 32099a?avr32?06/09 at32uc3l 14.6.21 temperature sensor calibration register name: tsens access type: read/write offset: 0x0050 reset value: 0x00000000 ? en: temperature sensor enable 0: temperature sensor is disabled 1: temperature sensor is enabled note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --- --en
231 32099a?avr32?06/09 at32uc3l 14.6.22 120mhz rc oscillator configuration register name: rc120m access type: read/write offset: 0x0058 reset value: 0x00000000 ? en: rc120m enable 0: clock is stopped. 1: clock is running. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------en
232 32099a?avr32?06/09 at32uc3l 14.6.23 backup register n name: brn access type: read/write offset: 0x005c-0x0068 reset value: 0x00000000 this is a set of general purpose read-write registers. data stor ed in these registers is retained when the device is shut off. before writing to these registers the user must ensure that brifardy in the pclksr register is not set. note that this registers are protected by a lock. to write to these registers the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 data[31:24] 23 22 21 20 19 18 17 16 data[23:16] 15 14 13 12 11 10 9 8 data[15:8] 76543210 data[7:0]
233 32099a?avr32?06/09 at32uc3l 14.6.24 32khz rc oscillator configuration register name: rc32kcr access type: read/write offset: 0x006c reset value: 0x00000000 ? en: rc32k enable 0: clock is stopped. 1: clock is running. note that this register is protected by a lock. to write to this register the unlock register has to be written first. please refer to the unlock register description for details. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------en
234 32099a?avr32?06/09 at32uc3l 14.6.25 generic clock control name: gcctrl access type: read/write offset: 0x0070-0x0080 reset value: 0x00000000 there is one gcctrl register per generic clock in the design. ? div: division factor ? oscsel: oscillator select ? diven: divide enable 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 div 15 14 13 12 11 10 9 8 oscsel 76543210 ------divencen table 14-9. generic clock sources oscsel clock/oscillator description 0 rcsys system rc oscillator clock 1 osc32k output clock from osc32k 2 dfll output clock from dfll 3 osc0 output clock from oscillator 4 rc120m output from 120mhz rcosc 5 clk_cpu the clock the cpu runs on 6 clk_hsb high speed bus clock 7 clk_pba peripheral bus a clock 8 clk_pbb peripheral bus b clock 9 rc32k output from 32khz rcosc 10 reserved 11 clk_1k 1khz output clock from osc32k 12-15 reserved
235 32099a?avr32?06/09 at32uc3l 0: the generic clock equals the undivided source clock. 1: the generic clock equals the source clock divided by 2*(div+1). ? cen: clock enable 0: clock is stopped. 1: clock is running.
236 32099a?avr32?06/09 at32uc3l 14.6.26 oscillator 0 version register name: osc0version access type: read-only offset: 0x03c8 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
237 32099a?avr32?06/09 at32uc3l 14.6.27 32khz oscillator version register name: osc32version access type: read-only offset: 0x03cc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
238 32099a?avr32?06/09 at32uc3l 14.6.28 digital frequency locked loop version register name: dfllif version access type: read-only offset: 0x03d0 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
239 32099a?avr32?06/09 at32uc3l 14.6.29 brown-out detector version register name: bodifaversion access type: read-only offset: 0x03d4 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
240 32099a?avr32?06/09 at32uc3l 14.6.30 voltage regulator version register name: vregifbversion access type: read-only offset: 0x03d8 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
241 32099a?avr32?06/09 at32uc3l 14.6.31 rc oscillator version register name: rcoscifaversion access type: read-only offset: 0x03dc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
242 32099a?avr32?06/09 at32uc3l 14.6.32 3.3v supply monitor version register name: sm33ifaversion access type: read-only offset: 0x03e0 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
243 32099a?avr32?06/09 at32uc3l 14.6.33 temperature sensor version register name: tsensifaversion access type: read-only offset: 0x03e4 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
244 32099a?avr32?06/09 at32uc3l 14.6.34 120mhz rc oscillator version register name: rc120mifaversion access type: read-only offset: 0x03ec reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
245 32099a?avr32?06/09 at32uc3l 14.6.35 backup register interface version register name: brifaversion access type: read-only offset: 0x03f0 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
246 32099a?avr32?06/09 at32uc3l 14.6.36 32khz rc oscillator version register name: rc32kifaversion access type: read-only offset: 0x03f4 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
247 32099a?avr32?06/09 at32uc3l 14.6.37 generic clock version register name: gclkversion access type: read-only offset: 0x03f8 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
248 32099a?avr32?06/09 at32uc3l 14.6.38 scif version register name: version access type: read-only offset: 0x03fc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:0] 76543210 version[7:0]
249 32099a?avr32?06/09 at32uc3l 14.7 module configuration the specific configuration for each scif instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 14-10. scif clock name module name clock name scif clk_scif table 14-11. register reset values register reset value osc0version 0x00000100 osc32version 0x00000101 dfllvifersion 0x00000201 bodifaversion 0x00000101 vregifbversion 0x00000101 rcoscifaversion 0x00000101 sm33ifaversion 0x00000100 tsensifaversion 0x00000100 rc120mifaversion 0x00000101 brifaversion 0x00000100 rc32kifaversion 0x00000100 gclkversion 0x00000100 version 0x00000102
250 32099a?avr32?06/09 at32uc3l 15. asynchronous timer (ast) rev: 3.0.0.0 15.1 features ? 32-bit counter with 32-bit prescaler ? clocked source ? system rc oscillator (rcsys) ? 32khz crystal oscillator (osc32k) ?pb clock ? generic clock (gclk) ? 1khz clock from 32khz oscillator ? operation and wakeup during shutdown ? optional calendar mode supported ? digital prescaler tuning for increased accuracy ? periodic interrup t(s) and peripheral event(s) supported ? alarm interrupt(s) and peripheral event(s) supported ? optional clear on alarm 15.2 overview the asynchronous timer (ast) enables periodi c interrupts and periodic peripheral events, as well as interrupts and peripheral events at a specifi ed time in the future. the ast consists of a 32-bit prescaler which feeds a 32-bit up-counter. the prescaler can be clocked from five differ- ent clock sources, including the low-power 32khz oscillator, which allows the ast to be used as a real-time timer with a maximum timeout of more than 100 years. also, the pb clock or a generic clock can be used for high-speed operation, allowing the ast to be used as a general timer. the ast can generate periodic interrupts and peripheral events from output from the prescaler, as well as alarm interrupts and peripheral events, which can trigger at any counter value. addi- tionally, the timer can trigger an overflow interrupt and peripheral event, and be reset on the occurrence of any alarm. this allows periodic interrupts and peripheral events at very long and accurate intervals. to keep track of time during shutdown the ast can run while the rest of the core is powered off. this will reduce the power consumption when the system is idle. the ast can also wake up the system from shutdown using either the alarm wakeup, periodic wakeup. or overflow wakeup mechanisms. the ast has been designed to meet the system tick and real time clock requirements of most embedded operating systems.
251 32099a?avr32?06/09 at32uc3l 15.3 block diagram figure 15-1. asynchronous timer block diagram 15.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 15.4.1 power management when the ast is enabled, it will re main clocked as long as its sele cted clock source is running. it can also wake the cpu from the currently active sleep mode. refer to the power manager chap- ter for details on the different sleep modes. 15.4.2 clocks the clock for the ast bus interface (clk_ast) is generated by the power manager. this clock is turned on by default, and can be enabled and disabled in the power manager. a number of clocks can be selected as source for the internal presca ler clock clk_ast_prsc. the prescaler, counter, an d interrupt will function as long as this selected clock source is active. the selected clock must be enabled in the system control interface (scif). the following clock sources are available: ? system rc oscillator (rcsys). th is oscillator is always enabl ed, except in some sleep modes. please refer to the electrical characteri stics chapter for the characteristic frequency of this oscillator. ? 32khz crystal oscillator (osc32k). this oscillator must be enabled before use. ? peripheral bus clock (pb clock). this is the cl ock of the peripheral bus the ast is connected to. 32-bit prescaler 32-bit counter alarm interrupts counter value clk_ast_cnt ovf control register en cssel psel periodic interrupts alarm register interrupt status and control irqs periodic interval register events wake control wake wake enable register digital tuner register rcosc osc32 pb clock gclk clk_1k clk_ast clk_ast_prsc clk_ast clk_ast
252 32099a?avr32?06/09 at32uc3l ? generic clock (gclk). one of the generic clocks is connected to the ast. this clock must be enabled before use, and remains enabled in sleep modes when the pb clock is active. ? 1khz clock from the 32khz oscillator (clk_1k). th is clock is only available in crystal mode, and must be enabled before use. please refer to the scif chapter for details. in shutdown mode only the 32kh z oscillator and the 1khz clock are available, using certain pins. please refer to the power manager chapter for details. 15.4.3 interrupts the ast interrupt request lines are connected to the interrupt controller. using the ast inter- rupts requires the interrupt controller to be programmed first. 15.4.4 peripheral events the ast peripheral events are connected via the peripheral event system. refer to the periph- eral event system chapter for details. 15.4.5 debug operation the ast prescaler and counter is frozen during debug operation, unless the run in debug bit in the development control register is set and the bit corresponding to the ast is set in the peripheral debug register. please refer to th e on-chip debug chapter in the avr32uc techni- cal reference manual for details. if the ast is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 15.5 functional description 15.5.1 initialization before enabling the ast, the internal ast clock clk_ast_prsc must be enabled, following the procedure specified in section 15.5.1.1 . the clock source select field in the clock register (clock.cssel) selects the source for this clock. the clock en able bit in the clock register (clock.cen) enables the clk_ast_prsc. when clk_ast_prsc is enabled, the ast can be enabled by writing a one to the enable bit in the control register (cr.en). 15.5.1.1 enabling and disabling the ast clock the clock source selection field (clock.cssel ) and the clock enable bit (clock.cen) can- not be changed simultaneously. special procedures must be followed for enabling and disabling the clk_ast_prsc and for changing the source for this clock. to enable clk_ast_prsc: ? write the selected value to clock.cssel ? wait until sr.clkbusy reads as zero ? write a one to clock.cen, without changi ng clock.cssel ? wait until sr.clkbusy reads as zero to disable the clock: ? write a zero to clock.cen to disable the clock, without changing clock.cssel ? wait until sr.clkbusy reads as zero
253 32099a?avr32?06/09 at32uc3l 15.5.1.2 changing the source clock the clk_ast_prsc must be disabled before swit ching to another source clock. the clock busy bit in the status register (sr.clkbusy) indicates whether the clock is busy or not. this bit is set when the cen bit in the clock register is changed, and cleared when the clock reg- ister can be changed. to change the clock: ? write a zero to clock.cen to disable the clock, without changing clock.cssel ? wait until sr.clkbusy reads as zero ? write the selected value to clock.cssel ? wait until sr.clkbusy reads as zero ? write a one to clock.cen to enable the clock, without changing the clock.cssel ? wait until sr.clkbusy reads as zero 15.5.2 basic operation 15.5.2.1 prescaler when the ast is enabled, the 32-bit pr escaler will increment on the rising edge of clk_ast_prsc. the prescaler value cannot be read or written, but it can be reset by writing a one to the prescaler clear bit in the control register (cr.pclr). the prescaler select field in the control regist er (cr.psel) selects the prescaler bit psel as source clock for the counter (clk_ast_cnt). this results in a counter frequency of: where f prsc is the frequency of the internal prescaler clock clk_ast_prsc. 15.5.2.2 counter operation when enabled, the ast will increment on every 0-to-1 transition of the selected prescaler tap- ping. when the calender bit in the control regi ster (cr.cal) is zero, the counter operates in counter mode. it will increm ent until it reaches the top value of 0xffffffff, and then wrap to 0x00000000. this sets the status bit overflow in the status register (s r.ovf). optionally, the counter can also be reset when an alarm occurs (see section 15.5.3.2 on page 255 . this will also set the ovf bit. the ast counter value can be read from or written to the counter value (cv) register. note that due to synchronization, continuous reading of the cv register with the lowest prescaler setting will skip every third value. in addition, if clk_ast_prsc is as fast as, or faster than, the clk_ast, the prescaler value must be 3 or higher to be able to read the cv without skipping values. f cnt f prsc 2 psel 1 + ---------------------- - =
254 32099a?avr32?06/09 at32uc3l 15.5.2.3 calendar operation when the cal bit in the control register is one, the counter operates in calendar mode. before this mode is enabled, the prescaler should be set up to give a pulse every second. the date and time can then be read from or written to the calendar value (calv) register. time is reported as seconds, minutes, and hours according to the 24-hour clock format. date is the numeral date of month (starting on 1). month is the numeral month of the year (1 = january, 2 = february, etc.). year is a 6-bit field coun ting the offset from a software-defined leap year (e.g. 2000). the date is automatically compensated for leap years, assuming every year divisible by 4 is a leap year. all peripheral events and interrupts work the same way in calendar mode as in counter mode. however, the alarm register (arn) must be written in time/date format for the alarm to trigger correctly. 15.5.3 interrupts the ast can generate five separate interrupt requests: ?ovf: ovf ? per: per0 , per1 ?alarm: alarm0 , alarm1 ? clkready ? ready this allows the user to allocate separate handlers and priorities to the different interrupt types. the generation of the per interrupt is described in section 15.5.3.1 ., and the generation of the alarm interrupt is described in section 15.5.3.2 . the ovf interrupt is generated when the counter overflows, or when the alarm value is re ached, if the clear on alarm bit in the control register is one. the clkready interrupt is generated when sr.clkbusy has a 1-to-0 transi- tion, and indicates that the clock synchroniz ation is completed. the ready interrupt is generated when sr.busy has a 1-to-0 transition, and indicates that the synchronization described in section 15.5.8 is completed. an interrupt request will be generated if the corresponding bit in the interrupt mask register (imr) is set. bits in imr are set by writing a one to the corresponding bit in the interrupt enable register (ier), and cleared by writing a one to the corresponding bit in the interrupt disable register (idr). the interrupt request remains acti ve until the corresponding bit in sr is cleared by writing a one to the corresponding bit in the status clear register (scr). the ast interrupts can wake the cpu from any sleep mode where the source clock and the interrupt controller is active. 15.5.3.1 periodic interrupt the ast can generate periodic interrupts. if the pern bit in the interrupt mask register (imr) is one, the ast will generate an interrup t request on the 0-to-1 transition of the selected bit in the prescaler when the ast is enabled. the bit is selected by the interval select field in the corre- sponding periodic interval register (pirn.insel), resulting in a periodic interrupt frequency of where f cs is the frequency of the selected clock source. the corresponding pern bit in the status register (sr) will be set when the select ed bit in the the prescaler has a 0-to-1 transition.
255 32099a?avr32?06/09 at32uc3l because of synchronizat ion, the transfer of the insel va lue will not happen immediately. when changing/setting the insel value, the user must make sure that the prescaler bit number insel will not have a 0-to-1 transition be fore the insel value is transferr ed to the register. in that case, the first periodic interrupt afte r the change will no t be triggered. 15.5.3.2 alarm interrupt the ast can also generate alar m interrupts. if the al armn bit in imr is one, the ast will gen- erate an interrupt request when the counter val ue matches the selected alarm value, when the ast is enabled. the alarm value is selected by writing the value to the value field in the corre- sponding alarm register (arn.value). the corresponding alarmn bit in sr will be set when the counter reaches the selected alarm value. because of synchronization, the transfer of t he alarm value will not happen immediately. when changing/setting the alarm value, the user must make sure that the counter will not count the selected alarm value before the value is transferred to the register. in that case, the first alarm interrupt after the cha nge will not be triggered. if the clear on alarm bit in the control register (cr.can) is one, the corresponding alarm inter- rupt will clear the count er and set the ovf bit in the stat us register. this will generate an overflow interrupt if the ovf bit in imr is set. 15.5.4 peripheral events the ast can generate a number of peripheral events: ?ovf ? per0 ? per1 ?alarm0 ?alarm1 the pern peripheral event(s) is generated the same way as the per interrupt, as described in section 15.5.3.1 . the alarmn peripheral event(s) is generated the same way as the alarm interrupt, as described in section 15.5.3.2 . the ovf peripheral event is generated the same way as the ovf interrupt, as described in section 15.5.3 - the peripheral event will be genera ted if the corresponding bit in the event mask (evm) register is set. bits in evm register are set by writing a one to the corresponding bit in the event enable (eve) register, and cleared by writing a one to the corresponding bit in the event disable (evd) register. f pa f cs 2 insel 1 + ------------------------- =
256 32099a?avr32?06/09 at32uc3l 15.5.5 ast wakeup the ast can wake up the cpu directly, without the need to trigger an interrupt. a wakeup can be generated when the counter overflows, when the counter reaches the selected alarm value, or when the selected prescaler bit has a 0-to-1 transition. in this case, the cpu will continue executing from the instruction following the sleep instruction. the ast wakeup is enabled by writing a one to th e corresponding bit in the wake enable regis- ter (wer). when the cpu wakes from sleep, the wake signal must be cleared by writing a one to the corresponding bit in scr to clear the internal wake signal to the sleep controller. if the wake signal is not cleared after waking from sl eep, the next sleep instru ction will have noe effect because the cpu will wake immediatel y after this sl eep instruction. the ast wakeup can wake the cpu from any sleep mode where the source clock is active. the ast wakeup can be configured independently of the interrupt masking. 15.5.6 shutdown mode if the ast is configured to use a clock that is available in shutdown mode, the ast can be used to wake up the system from sh utdown. both the alarm wakeup, periodic wakeup, and overflow wakeup mechanisms can be used in this mode. when waking up from shutdown mode all control registers will have the same value as before the shutdown was entered, except the interrupt mask register (imr). imr will be reset with all interrupts turned off. the software must first reconfigure the interrupt controller and then enable the interrupts in the ast to again receive interrupts from the ast. the cv register will be updated with the current counter value directly after wakeup from shut- down. the sr will show the status of the ast, including the status bits set during shutdown operation. when waking up the system from shutdown the cpu will start executi ng code from the reset start address. 15.5.7 digital tuner the digital tuner adds the possibility to compensate for a too slow or a too fast input clock. the add bit in the digital tuner re gister (dtr.add) selects if the tuned frequency should be reduced or increased. the resulting frequency is for , where is the original frequency of the prescaler. value and exp are chosen by writing the selected value to the corresponding bitfield in dtr. 15.5.8 synchronization as the prescaler and counter operate asynchronously from the user interface, the ast needs a few clock cycles to synchronize the values written to the cr, cv, scr, wer, eve, evd, pirn, arn, and dtr registers. the busy bit in the status register (sr.busy) indicates that the syn- chronization is ongoing. during this time , writes to these regi sters will be discarded. f tuned f 0 1 1 1 value ------------------- - ?? ?? 2 exp 8 + () () ? 1 ? -------------------------------------------------------------------- - ?? ?? ?? ?? ?? = value 0 > f 0
257 32099a?avr32?06/09 at32uc3l note that synchronization takes place also if the prescaler is clocked from clk_ast.
258 32099a?avr32?06/09 at32uc3l 15.6 user interface note: 1. the reset values are device specific. please refer to the modue configuration section at the end of this chapter. 2. the number of alarm and periodic interval registers are device specific. please refer to the module configuration section at the end of this chapter. table 15-1. ast register memory map offset register register name access reset 0x00 control register cr read/write 0x00000000 0x04 counter value cv read/write 0x00000000 0x08 status register sr read-only 0x00000000 0x0c status clear register scr write-only 0x00000000 0x10 interrupt enable register ier write-only 0x00000000 0x14 interrupt disable register idr write-only 0x00000000 0x18 interrupt mask register imr read-only 0x00000000 0x1c wake enable register wer read/write 0x00000000 0x20 alarm register 0 (2) ar0 read/write 0x00000000 0x24 alarm register 1 (2) ar1 read/write 0x00000000 0x30 periodic interval register 0 (2) pir0 read/write 0x00000000 0x34 periodic interval register 1 (2) pir1 read/write 0x00000000 0x40 clock control register clock read/write 0x00000000 0x44 digital tuner register dtr read/write 0x00000000 0x48 event enable eve write-only 0x00000000 0x4c event disable evd write-only 0x00000000 0x50 event mask evm read-only 0x00000000 0x54 calendar value calv read/write 0x00000000 0xf0 parameter register parameter read-only - (1) 0xfc version register version read-only - (1)
259 32099a?avr32?06/09 at32uc3l 15.6.1 control register name: cr access type: read/write offset: 0x00 reset value: 0x00000000 ? psel: prescaler select selects prescaler bit psel as source clock for the counter. ? can: clear on alarm n 0: the corresponding alarm will not clear the counter. 1: the corresponding alarm will clear the counter. ? cal: calendar mode 0: the ast operates in counter mode. 1: the ast operates in calendar mode. ? pclr: prescaler clear writing a zero to this bit has no effect. writing a one to this bit clears the prescaler. this bit always reads as zero. ? en: enable 0: the ast is disabled. 1: the ast is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - psel 15 14 13 12 11 10 9 8 ------ca1ca0 76543210 - - - - - cal pclr en
260 32099a?avr32?06/09 at32uc3l 15.6.2 counter value name: cv access type: read/write offset: 0x04 reset value: 0x00000000 ? value: ast value the current value of the ast counter. 31 30 29 28 27 26 25 24 value[31:24] 23 22 21 20 19 18 17 16 value[23:16] 15 14 13 12 11 10 9 8 value[15:8] 76543210 value[7:0]
261 32099a?avr32?06/09 at32uc3l 15.6.3 status register name: sr access type: read-only offset: 0x08 reset value: 0x00000000 ? clkrdy: clock ready this bit is cleared when the corresponding bit in scr is written to one. this bit is set when the sr.clkbusy bit has a 1-to-0 transition. ? clkbusy: clock busy 0: the clock is ready and can be changed. 1: clock.cen has been written and the clock is busy. ? ready: ast ready this bit is cleared when the corresponding bit in scr is written to one. this bit is set when the sr.busy bit has a 1-to-0 transition. ? busy: ast busy 0: the ast accepts writes to cr, cv, scr, wer, eve, evd, arn, pirn, and dtr. 1: the ast is busy and will discard writes to cr, cv, scr, wer, eve, evd, arn, pirn, and dtr. ? pern: periodic n this bit is cleared when the corresponding bit in scr is written to one. this bit is set when the selected bit in the prescaler has a 0-to-1 transition. ? alarmn: alarm n this bit is cleared when the corresponding bit in scr is written to one. this bit is set when the counter reaches the selected alarm value. ? ovf: overflow this bit is cleared when the corresponding bit in scr is written to one. this bit is set when an overflow has occurred. 31 30 29 28 27 26 25 24 - - clkrdy clkbusy - - ready busy 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
262 32099a?avr32?06/09 at32uc3l 15.6.4 status clear register name: scr access type: write-only offset: 0x0c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 - - clkrdy - - - ready - 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
263 32099a?avr32?06/09 at32uc3l 15.6.5 interrupt enable register name: ier access type: write-only offset: 0x10 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 - - clkrdy - - - ready - 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
264 32099a?avr32?06/09 at32uc3l 15.6.6 interrupt disable register name: idr access type: write-only offset: 0x14 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 - - clkrdy - - - ready - 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
265 32099a?avr32?06/09 at32uc3l 15.6.7 interrupt mask register name: imr access type: read-only offset: 0x18 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 - - clkrdy - - - ready - 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
266 32099a?avr32?06/09 at32uc3l 15.6.8 wake enable register name: wer access type: read/write offset: 0x1c reset value: 0x00000000 this register enables the wakeup signal from the ast. ? pern: periodic n 0: the cpu will not wake up from sleep mode when the se lected bit in the prescaler has a 0-to-1 transition. 1: the cpu will wake up from sleep mode when the sele cted bit in the prescaler has a 0-to-1 transition. ? alarmn: alarm n 0: the cpu will not wake up from sleep mode when the counter reaches the selected alarm value. 1: the cpu will wake up from sleep mode when the counter reaches the selected alarm value. ? ovf: overflow 0: a counter overflow will not wake up the cpu from sleep mode. 1: a counter overflow will wake up the cpu from sleep mode. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
267 32099a?avr32?06/09 at32uc3l 15.6.9 alarm register 0 name: ar0 access type: read/write offset: 0x20 reset value: 0x00000000 ? value: alarm value when the counter reaches this value, an alarm is generated. 31 30 29 28 27 26 25 24 value[31:24] 23 22 21 20 19 18 17 16 value[23:16] 15 14 13 12 11 10 9 8 value[15:8] 76543210 value[7:0]
268 32099a?avr32?06/09 at32uc3l 15.6.10 alarm register 1 name: ar1 access type: read/write offset: 0x24 reset value: 0x00000000 ? value: alarm value when the counter reaches this value, an alarm is generated. 31 30 29 28 27 26 25 24 value[31:24] 23 22 21 20 19 18 17 16 value[23:16] 15 14 13 12 11 10 9 8 value[15:8] 76543210 value[7:0]
269 32099a?avr32?06/09 at32uc3l 15.6.11 periodic interval register 0 name: pir0 access type: read/write offset: 0x30 reset value: 0x00000000 ? insel: interval select the per0 bit in sr will be set when the insel bit in the prescaler has a 0-to-1 transition. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - insel
270 32099a?avr32?06/09 at32uc3l 15.6.12 periodic interval register 1 name: pir1 access type: read/write offset: 0x34 reset value: 0x00000000 ? insel: interval select the per1 bit in sr will be set when the insel bit in the prescaler has a 0-to-1 transition. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - insel
271 32099a?avr32?06/09 at32uc3l 15.6.13 clock control register name: clock access type: read/write offset: 0x40 reset value: 0x00000000 ? cssel: clock source selection this field defines the clock source clk_ast_prsc for the prescaler: ? cen: clock enable 0: clk_ast_prsc is disabled. 1: clk_ast_prsc is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - cssel 76543210 -------cen table 15-2. clock source selection cssel clock source 0 system rc oscillator (rcsys) 1 32khz oscillator (osc32k) 2 pb clock 3 generic clock (gclk) 4 1khz clock from 32khz oscillator (clk_1k)
272 32099a?avr32?06/09 at32uc3l 15.6.14 digital tuner register name: dtr access type: read/write offset: 0x44 reset value: 0x00000000 ? add: 0: the resulting frequency is for . 1: the resulting frequency is for . 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 value 76543210 - - add exp ff 01 1 1 value ------------------- - ?? ?? 2 exp 8 + () ? 1 ? ---------------------------------------------------------------- ? ?? ?? ?? ?? ?? = value 0 > ff 01 1 1 value ------------------- - ?? ?? 2 exp 8 + () ? 1 ? ---------------------------------------------------------------- + ?? ?? ?? ?? ?? = value 0 >
273 32099a?avr32?06/09 at32uc3l 15.6.15 event enable register name: eve access type: write-only offset: 0x48 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in evm. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
274 32099a?avr32?06/09 at32uc3l 15.6.16 event disable register name: evd access type: write-only offset: 0x4c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in evm. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
275 32099a?avr32?06/09 at32uc3l 15.6.17 event mask register name: evm access type: read-only offset: 0x50 reset value: 0x00000000 0: the corresponding peripheral event is disabled. 1: the corresponding peripheral event is enabled. this bit is cleared when the corresponding bit in evd is written to one. this bit is set when the corresponding bit in eve is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - - per1 per0 15 14 13 12 11 10 9 8 - - - - - - alarm1 alarm0 76543210 -------ovf
276 32099a?avr32?06/09 at32uc3l 15.6.18 calendar value name: calv access type: read/write offset: 0x54 reset value: 0x00000000 ? year: year current year. the year is considered a leap year if year[1:0] = 0. ?month: month 1 = january 2 = february ... 12 = december ?day: day day of month, starting with 1. ? hour: hour hour of day, in 24-hour clock format. legal values are 0 through 23. ? min: minute minutes, 0 through 59. ? sec: second seconds, 0 through 59. 31 30 29 28 27 26 25 24 year month[3:2] 23 22 21 20 19 18 17 16 month[1:0] day hour[4] 15 14 13 12 11 10 9 8 hour[3:0] min[5:2] 76543210 min[1:0] sec
277 32099a?avr32?06/09 at32uc3l 15.6.19 parameter register name: parameter access type: read-only offset: 0xf0 reset value: - this register gives the configuration used in the specific device. also refe r to the module configuration section. ? dt: digital tuner 0: digital tuner not implemented. 1: digital tuner implemented. ? dtrexpwa: digital tuner exponent writeable 0: digital tuner exponent is a constant value. writes to exp field in dtr will be discarded. 1: digital tuner exponent is chos en by writing to exp field in dtr. ? dtrexpvalue: digital tuner exponent value digital tuner exp onent value if dtexpwa is zero. ? numar: number of alarm comparators 0: zero alarm comparators. 1: one alarm comparator. 2: two alarm comparators. ? numpir: number of periodic comparators 0: one periodic comparator. 1: two periodic comparator. ? pirnwa: periodic interval n writeable 0: periodic interval n prescaler tapping is a constant value. writes to insel field in pirn register will be discarded. 1: periodic interval n prescaler tapping is chos en by writing to insel field in pirn register. ? pernvalue: periodic interval n value periodic interval prescaler n tapping if pirnwa is zero. 31 30 29 28 27 26 25 24 - - - per1value 23 22 21 20 19 18 17 16 - - - per0value 15 14 13 12 11 10 9 8 pir1wa pir0wa - numpir - - numar 76543210 - dtexpvalue dtexpwa dt
278 32099a?avr32?06/09 at32uc3l 15.6.20 version register name: version access type: read-only offset: 0xfc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
279 32099a?avr32?06/09 at32uc3l 15.7 module configuration the specific configuration for each ast instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 15-3. module configuration feature ast number of alarm comparators 1 number of periodic comparators 1 digital tuner on table 15-4. module clock name clock name description clk_ast clock for the ast bus interface gclk the generic clock used for the ast is gclk2 pb clock peripheral bus clock from the pba clock domain table 15-5. register reset values register reset value version 0x00000300 parameter 0x00004103
280 32099a?avr32?06/09 at32uc3l 16. watchdog timer (wdt) rev: 4.0.2.0 16.1 features ? watchdog timer counter with 32-bit counter ? timing window watchdog ? clocked from system rc oscillator or the 32 khz crystal oscillator ? configuration lock ? wdt may be enabled at reset by a fuse 16.2 overview the watchdog timer (wdt) will reset the device unless it is periodically serviced by the soft- ware. this allows the device to recover from a condition that has caused the system to be unstable. the wdt has an internal counter clocked from th e system rc oscillator or the 32 khz crystal oscillator. the wdt counter must be periodically cleared by software to avoid a watchdog reset. if the wdt timer is not cleared correctly, the device will reset and start executing from the boot vector. 16.3 block diagram figure 16-1. wdt block diagram 16.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. clk_cnt watchdog detector 32-bit counter watchdog reset 0 1 rcsys osc32k cssel cen sync clk_cnt domain pb clock domain pb wdtclr window, cleared en, mode, psel, tban ctrl clr sr
281 32099a?avr32?06/09 at32uc3l 16.4.1 power management when the wdt is enabled, the wdt remains clocked in all sleep modes. it is not possible to enter sleep modes where the source clock of clk_cnt is stopped. atte mpting to do so will result in the chip entering the lowest sleep mode where the source clock is running, leaving the wdt operational. please refer to the power manager chapter for details about sleep modes. after a watchdog reset the wdt bit in the reset cause register (rcause) in the power man- ager will be set. 16.4.2 clocks the clock for the wdt bus interface (clk_wdt) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to dis- able the wdt before disabling the clock, to avoid freezing the wdt in an undefined state. there are two possible clock sources for the watchdog timer (clk_cnt): ? system rc oscillator (rcsys): th is oscillator is always enabl ed when selected as clock source for the wdt. please re fer to the power manager chapter for details about the rcsys and sleep modes. please refer to the electrical characteristics chapter for the characteristic frequency of this oscillator. ? 32 khz crystal oscillator (osc32k) : this oscillator has to be en abled in the system control interface before using it as cloc k source for the wdt. the wdt will not be able to detect if this clock is stopped. 16.4.3 debug operation the wdt counter is frozen during debug operation, unless the run in debug bit in the develop- ment control register is set and the bit corresponding to the wdt is set in the peripheral debug register. please refer to the on-chip debug chapter in the avr32uc technical reference manual for details. if the wdt counter is not frozen during debug operation it will need periodi- cally clearing to avoid a watchdog reset. 16.4.4 fuses the wdt can be enabled at reset. this is controlled by the wdtauto fuse, see section 16.5.4 for details. please refer to the fuse settings se ction in the flash controller chapter for details about wdtauto and how to program the fuses. 16.5 functional description 16.5.1 basic mode 16.5.1.1 wdt control register access to avoid accidental disabling of the watchdog, the control register (ctrl) must be written twice, first with the key field set to 0x55, t hen 0xaa without changing the other bits. failure to do so will cause the write operat ion to be ignored, an d the value in the ctrl register will not be changed. 16.5.1.2 changing clk_cnt clock source after any reset, except for watchdog reset, clk_cnt will be enabled with the rcsys as source.
282 32099a?avr32?06/09 at32uc3l to change the clock for the wdt the following steps need to be taken. note that the wdt should always be disabled before changing the clk_cnt source: 1. write a zero to the clock enable (cen) bit in the ctrl register, leaving the other bits as they are in the ctrl register. this will stop clk_cnt. 2. read back the ctrl register until the cen bit reads zero. the clock has now been stopped. 3. modify the clock source select (cssel) bit in the ctrl register wit h your new clock selec- tion and write it to the ctrl register. 4. write a one to the cen bit, leaving the other bits as they are in the ctrl register. this will enable the clock. 5. read back the ctrl register until the cen bit reads one. the clock has now been enabled. 16.5.1.3 configuring the wdt if the mode bit in the ctrl register is zero, the wdt is in basic mode. the time out prescale select (psel) field in the ctrl regi ster selects the wdt timeout period: t timeout = t psel = 2 (psel+1) / f clk_cnt 16.5.1.4 enabling the wdt to enable the wdt write a one to the enable (en) bit in the ctrl register. due to internal syn- chronization, it will take some time for the ctrl.en bit to read back as one. 16.5.1.5 clearing the wdt counter the wdt counter is cleared by writing a one to the watchdog clear (wdtclr) bit in the clear (clr) register, at any correct write to the ctrl register, or when the counter reaches t timeout and the chip is reset. in basic mode the clr.wd tclr can be written at any time when the wdt counter cleared (cleared) bit in the status register (sr) is one. due to internal synchroniza- tion, clearing the wdt counter takes some time . the sr.cleared bit is cleared when writing to clr.wdtclr bit and set when the clearing is done. any write to the clr.wdtclr bit while sr.cleared is ze ro will be ignored. writing to the clr.wdtclr bit has to be done in a particular sequence to be valid. the clr register must be written twice, first with the key field set to 0x 55 and wdtclr set to one, then a second write with the key set to 0xaa without changing the wdtclr bit. writing to the clr register without the correct sequence has no effect. if the wdt counter is periodically cleared within t psel no watchdog rese t will be issued, see fig- ure 16-2 on page 283 .
283 32099a?avr32?06/09 at32uc3l figure 16-2. basic mode wdt timing diagram, normal operation. if the wdt counter is not cleared within t psel a watchdog reset will be issued at the end of t psel , see figure 16-3 on page 283 . figure 16-3. basic mode wdt timing diagram, no clear within t psel . 16.5.1.6 watchdog reset a watchdog reset will result in a reset and the code will start executing from the boot vector, please refer to the power manager chapter for details. if the disable after reset (dar) bit in the ctrl register is zero, the wdt counter will restart counting from zero when the watchdog reset is released. if the ctrl.dar bit is one the wdt will be di sabled after a watchdog re set. only the ctrl.en bit will be changed after the watc hdog reset. however, if wdtauto fuse is configured to enable the wdt after a watchdog reset, and the ctrl.fcd bit is zero, writing a one to the ctrl.dar bit will have no effect. t psel timeout write one to clr.wdtclr watchdog reset t=t 0 t psel timeout write one to clr.wdtclr watchdog reset t=t 0
284 32099a?avr32?06/09 at32uc3l 16.5.2 window mode the window mode can protect against tight loops of runaway code. this is obtained by adding a ban period to timeout period. during the ban period clearing the wdt counter is not allowed. if the wdt mode (mode) bit in the ctrl register is one, the wdt is in window mode. note that the ctrl.mode bit can only be change d when the wdt is di sabled (ctrl.en=0). the psel and time ban prescale select (tban) fields in the ctrl register selects the wdt timeout period t timeout = t tban + t psel = (2 (tban+1) + 2 (psel+1) ) / f clk_cnt where t tban sets the time period when clearing the wdt counter by writing to the clr.wdtclr bit is not allowed. doing so will result in a watc hdog reset, the device w ill receive a reset and the code will start executing form the boot vector, see figure 16-5 on page 285 . the wdt counter will be cleared. writing a one to the clr.wdtclr bit within the t psel period will clear the wdt counter and the counter starts counting from zero (t=t 0 ), entering t tban , see figure 16-4 on page 284 . if the value in the ctrl register is changed , the wdt counter will be cleared without a watch- dog reset, regardless of if the value in the wdt counter and the tban value. if the wdt counter reaches t timeout , the counter will be cleared, the device will receive a reset and the code will start execut ing form the boot vector. figure 16-4. window mode wdt timing diagram t tban t psel timeout write one to clr.wdtclr watchdog reset t=t 0
285 32099a?avr32?06/09 at32uc3l figure 16-5. window mode wdt timing diagram, clearing within t tban , resulting in watchdog reset. 16.5.3 disabling the wdt the wdt is disabled by writing a zero to the ctrl.en bit. when disabling the wdt no other bits in the ctrl register should be changed until the ctrl.en bit reads back as zero. if the ctrl.cen bit is written to zero, the ctrl.en bit will never read back as zero if changing the value from one to zero. 16.5.4 flash calibration the wdt can be enabled at rese t. this is controlled by the wdtauto fuse. the wdt will be set in basic mode, rcsys is set as source fo r clk_cnt, and psel will be set to a value giving t psel above 100 ms. please refer to the fuse settings chapter for details about wdtauto and how to program the fuses. if the flash calibration done (fcd) bit in the ctrl register is zero at a watchdog reset the flash calibration will be redone, and the ctrl.fcd bi t will be set when the calibration is done. if ctrl.fcd is one at a watchdog reset, the conf iguration of the wdt will not be changed during flash calibration. after any other reset the fl ash calibration will always be done, and the ctrl.fcd bit will be set when the calibration is done. 16.5.5 special considerations care must be taken when selecting the psel/tban va lues so that the time out period is greater than the startup time of the ch ip. otherwise a watchdog reset will reset the chip before any code has been run. this can also be avoided by writ ing the ctrl.dar bit to one when configuring the wdt. if the store final value (sfv) bit in the ctrl register is one, the ctrl register is locked for further write accesses. all writes to the ctrl register will be i gnored. once the ctrl register is locked, it can only be unlocked by a reset (e.g. por, ocd, and wdt). the ctrl.mode bit can only be changed when the wdt is disabled (ctrl.en=0). t tban t psel timeout write one to clr.wdtclr watchdog reset t=t 0
286 32099a?avr32?06/09 at32uc3l 16.6 user interface note: 1. the reset value for this register is device specific. plea se refer to the module configur ation section at the end of thi s chapter. table 16-1. wdt register memory map offset register register name access reset 0x000 control register ctrl read/write 0x00010080 0x004 clear register clr write-only 0x00000000 0x008 status register sr read-only 0x00000003 0x3fc version register version read-only - (1)
287 32099a?avr32?06/09 at32uc3l 16.6.1 control register name: ctrl access type: read/write offset: 0x000 reset value: 0x00010080 ?key this field must be written twice, first with key value 0x55, t hen 0xaa, for a write operation to be effective. this field alway s reads as zero. ? tban: time ban prescale select counter bit tban is used as watchdog ?banned? time frame. in this time frame clearing the wdt timer is forbidden, otherwise a watchdog reset is generated and the wdt timer is cleared. ? cssel: clock source select 0: select the system rc oscillator (rcsys) as clock source. 1: select the 32khz crystal osc illator (osc32k) as clock source. ? cen: clock enable 0: the wdt clock is disabled. 1: the wdt clock is enabled. ? psel: time out prescale select counter bit psel is used as watchdog timeout period. ? fcd: flash calibration done this bit is set after any reset. 0: the flash calibration will be redone after a watchdog reset. 1: the flash calibration will not be redone after a watchdog reset. ? sfv: wdt control register store final value 0: wdt control register is not locked. 1: wdt control register is locked. once locked, the control register can not be re-written, only a reset unlocks the sfv bit. ?mode: wdt mode 0: the wdt is in basic mode, only psel time is used. 1: the wdt is in window mode. tota l timeout period is now tban+psel. writing to this bit when the wdt is enabled has no effect. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 - tban cssel cen 15 14 13 12 11 10 9 8 - - - psel 76543210 fcd - - - sfv mode dar en
288 32099a?avr32?06/09 at32uc3l ? dar: wdt disable after reset 0: after a watchdog reset, the wdt will still be enabled. 1: after a watchdog reset, the wdt will be disabled. ? en: wdt enable 0: wdt is disabled. 1: wdt is enabled. after writing to this bit the read back value will not change until the wdt is enabled/disabled. this due to internal synchronization.
289 32099a?avr32?06/09 at32uc3l 16.6.2 clear register name: clr access type: write-only offset: 0x004 reset value: 0x00000000 when the watchdog timer is enabled, this register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset. ?key this field must be written twice, first with key value 0x55, then 0xaa, for a write operation to be effective. ? wdtclr: watchdog clear writing a zero to this bit has no effect. writing a one to this bit clears the wdt counter. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------wdtclr
290 32099a?avr32?06/09 at32uc3l 16.6.3 status register name: sr access type: read-only offset: 0x008 reset value: 0x00000003 ? cleared: wdt counter cleared this bit is cleared when writing a one to the clr.wdtclr bit. this bit is set when clearing the wdt counter is done. ? window: within window this bit is cleared when the wdt counter is inside the tban period. this bit is set when the wdt counter is inside the psel period. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------clearedwindow
291 32099a?avr32?06/09 at32uc3l 16.6.4 version register name: version access type: read-only offset: 0x3fc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
292 32099a?avr32?06/09 at32uc3l 16.7 module configuration the specific configuration for each wdt instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 16-2. module clock name module name clock name module clk_wdt table 16-3. register reset values register reset value version 0x00000402
293 32099a?avr32?06/09 at32uc3l 17. external interrupt controller (eic) rev: 3.0.1.0 17.1 features ? dedicated interrupt requ est for each interrupt ? individually maskable interrupts ? interrupt on rising or falling edge ? interrupt on high or low level ? asynchronous interrupts fo r sleep modes without clock ? filtering of interrupt lines ? maskable nmi interrupt 17.2 overview the external interrupt controller (eic) allows pins to be configured as external interrupts. each external interrupt has its own interrupt request and can be individually masked. each external interrupt can generate an interrupt on rising or falling edge, or high or low level. every interrupt input has a configurable filter to remove spikes from the interrupt source. every interrupt pin can also be configured to be asynchronous in order to wake up the part from sleep modes where the clk_sync clock has been disabled. a non-maskable interrupt (nmi) is also supported. this has the same properties as the other external interrupts, but is connected to the nmi request of the cpu, enabling it to interrupt any other interrupt mode. the eic can wake up the part from sleep modes without triggering an interrupt. in this mode, code execution starts from the instruction following the sleep instruction.
294 32099a?avr32?06/09 at32uc3l 17.3 block diagram figure 17-1. eic block diagram 17.4 i/o lines description 17.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 17.5.1 i/o lines the external interrupt pins (extintn and nmi) may be multiplexed with i/o control- ler lines. the programmer must first program the i/o contro ller to assign the desired eic pins to their peripheral f unction. if i/o lines of the eic are not used by the applica- tion, they can be used for othe r purposes by the i/o controller. it is only required to enable the eic inputs actually in use. if an application requires two external interrupts, then only two i/o lines will be a ssigned to eic inputs. edge/level detector mask irqn extintn nmi intn level mode edge ier idr icr ctrl isr imr filter filter polarity control level mode edge asynchronus detector eic_wake enable en dis ctrl clk_sync wake detect async table 17-1. i/o lines description pin name pin description type nmi non-maskable interrupt input extintn external interrupt input
295 32099a?avr32?06/09 at32uc3l 17.5.2 power management all interrupts are available in all sleep modes as long as the eic module is powered. however, in sleep modes where clk_sync is stopped, the interrupt must be configured to asynchronous mode. 17.5.3 clocks the clock for the eic bus interface (clk_eic) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. the filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system rc osc illator (rcsys) is not running. this clock is referred to as clk_sync. 17.5.4 interrupts the external interrupt request lines are connected to the interrupt controller. using the external interrupts requires the interrupt controller to be programmed first. using the non-maskable interrupt does not require the interrupt controller to be programmed. 17.5.5 debug operation when an external debugger forces the cpu into debug mode, the eic continues normal opera- tion. if the eic is configured in a way that r equires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 17.6 functional description 17.6.1 external interrupts the external interrupts are not enabled by default, allowing the proper interrupt vectors to be set up by the cpu before the interrupts are enabled. each external interrupt intn can be configured to prod uce an interrup t on rising or falling edge, or high or low level. external interrupts ar e configured by the mode, edge, and level regis- ters. each interrupt has a bit intn in each of these registers. writing a zero to the intn bit in the mode register enables edge triggered interrupts, while writing a one to the bit enables level trig- gered interrupts. if intn is configured as an edge triggered interrupt, writing a zero to the intn bit in the edge register will cause the interrupt to be triggered on a falling edg e on extintn, while writing a one to the bit will cause the in terrupt to be triggered on a rising edge on extintn. if intn is configured as a leve l triggered interrupt, writing a zero to the intn bit in the level register will cause the interrupt to be triggered on a low level on extintn, while writing a one to the bit will cause the interrupt to be triggered on a high level on extintn. each interrupt has a corresponding bit in each of the interrupt control and status registers. writ- ing a one to the intn bit in the interrupt enabl e register (ier) enables the external interrupt from pin extintn to propagate from the eic to the interrupt controller, while writing a one to intn bit in the interrupt disable register (idr) disables this propagation. the interrupt mask register (imr) can be read to check which interrupts are enabled. when an interrupt triggers, the corresponding bit in th e interrupt status register (isr) will be set. this bit remains set until a one is written to the corresponding bit in the interrupt clear register (icr) or the interrupt is disabled.
296 32099a?avr32?06/09 at32uc3l writing a one to the intn bit in the enable regist er (en) enables the external interrupt on pin extintn, while writing a one to intn bit in the disable register (dis) disables the external inter- rupt. the control register (ctrl) can be read to check which interrupts are enabled. if a bit in the ctrl register is set, but the corresponding bit in imr is not set, an interrupt will not propa- gate to the interrupt controller. however, the corresponding bit in isr will be set, and eic_wake will be set. note that an external inte rrupt should not be en abled before it has been configured correctly. if the ctrl.intn bit is zero, the corresponding bi t in isr will always be ze ro. disabling an exter- nal interrupt by writing a one to the dis.intn bit will clear the corresponding bit in isr. please refer to the module configuration section for the number of external interrupts. 17.6.2 synchronization and filtering of external interrupts in synchronous mode the pin value of the extintn pin is synchronized to clk_sync, so spikes shorter than one clk_sync cycle are not guaranteed to produce an interrupt. the syn- chronization of the extintn to clk_sync will delay the propagation of the interrupt to the interrupt controller by two cycles of clk_sync, see figure 17-2 and figure 17-3 for examples (filter off). it is also possible to apply a filter on extintn by writing a one to the intn bit in the filter reg- ister. this filter is a majority voter, if the condition for an interrupt is true for more than one of the latest three cycles of clk_sync the interrup t will be set. this will additionally delay the propa- gation of the interrupt to the interrupt controller by one or two cycles of clk_sync, see figure 17-2 and figure 17-3 for examples (filter on). figure 17-2. timing diagram, synchronous interr upts, high level or rising edge extintn/nmi clk_sync isr.intn: filter off isr.intn: filter on
297 32099a?avr32?06/09 at32uc3l figure 17-3. timing diagram, synchrono us interrupts, low level or falling edge 17.6.3 non-maskable interrupt the nmi supports the same features as the external interrupts, and is accessed through the same registers. th e description in section 17.6.1 should be followed, accessing the nmi bit instead of the intn bits. the nmi is non-maskable within the cpu in the sense that it can interrupt any other execution mode. still, as for the other exte rnal interrupts, the actual nmi input can be enabled an d disabled by accessing the registers in the eic. 17.6.4 asynchronous interrupts each external inte rrupt can be made asynchronous by wr iting a one to intn in the async reg- ister. this will route the interrupt signal through the asynchronous path of the module. all edge interrupts will be interpreted as leve l interrupts and the f ilter is disabled. if an interrupt is config- ured as edge triggered interr upt in asynchronous mode, a zero in edge.intn will be interpreted as low level, and a one in edge.intn will be inte rpreted as high level. eic_wake will be set immediately after the source triggers the interrupt, while the correspond- ing bit in isr and the interrupt to the interrupt controller will be set on the next rising edge of clk_sync. please refer to figure 17-4 on page 298 for details. when clk_sync is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device . eic_wake will restart clk_sync and isr will be updated on the first rising edge of clk_sync. extintn/nmi clk_sync isr.intn: filter off isr.intn: filter on
298 32099a?avr32?06/09 at32uc3l figure 17-4. timing diagram, asynchronous interrupts 17.6.5 wakeup the external interrupts can be used to wake up the part from sleep modes. the wakeup can be interpreted in two ways. if the corresponding bit in imr is one, then the execution starts at the interrupt handler for this interrupt. if the bit in imr is zero, then the execution starts from the next instruction after the sleep instruction. extintn/nmi clk_sync isr.intn: rising edge or high level eic_wake: rising edge or high level extintn/nmi clk_sync isr.intn: rising edge or high level eic_wake: rising edge or high level
299 32099a?avr32?06/09 at32uc3l 17.7 user interface note: 1. the reset value is device specific. please refer to th e module configuration section at the end of this chapter. table 17-2. eic register memory map offset register register name access reset 0x000 interrupt enable register ier write-only 0x00000000 0x004 interrupt disable register idr write-only 0x00000000 0x008 interrupt mask register imr read-only 0x00000000 0x00c interrupt status register isr read-only 0x00000000 0x010 interrupt clear register icr write-only 0x00000000 0x014 mode register mode read/write 0x00000000 0x018 edge register edge read/write 0x00000000 0x01c level register level read/write 0x00000000 0x020 filter register filter read/write 0x00000000 0x024 test register test read/write 0x00000000 0x028 asynchronous register async read/write 0x00000000 0x030 enable register en write-only 0x00000000 0x034 disable register dis write-only 0x00000000 0x038 control register ctrl read-only 0x00000000 0x3cf version register version read-only - (1)
300 32099a?avr32?06/09 at32uc3l 17.7.1 interrupt enable register name: ier access type: write-only offset: 0x000 reset value: 0x00000000 ?intn: external interrupt n writing a zero to this bit has no effect. writing a one to this bit will set the corresponding bit in imr. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt rwriting a zero to this bit has no effect. iwrting a one to this bit will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
301 32099a?avr32?06/09 at32uc3l 17.7.2 interrupt disable register name: idr access type: write-only offset: 0x004 reset value: 0x00000000 ?intn: external interrupt n writing a zero to this bit has no effect. writing a one to this bit will clear the corresponding bit in imr. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt writing a zero to this bit has no effect. writing a one to this bit will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
302 32099a?avr32?06/09 at32uc3l 17.7.3 interrupt mask register name: imr access type: read-only offset: 0x008 reset value: 0x00000000 ?intn: external interrupt n 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable in terrupt is disabled. 1: the non-maskable interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
303 32099a?avr32?06/09 at32uc3l 17.7.4 interrupt status register name: isr access type: read-only offset: 0x00c reset value: 0x00000000 ?intn: external interrupt n 0: an interrupt event has not occurred. 1: an interrupt event has occurred. this bit is cleared by writing a one to the corresponding bit in icr. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: an interrupt event has not occurred. 1: an interrupt event has occurred. this bit is cleared by writing a one to the corresponding bit in icr. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
304 32099a?avr32?06/09 at32uc3l 17.7.5 interrupt clear register name: icr access type: write-only offset: 0x010 reset value: 0x00000000 ?intn: external interrupt n writing a zero to this bit has no effect. writing a one to this bit will clear the corresponding bit in isr. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt writing a zero to this bit has no effect. writing a one to this bit will clear the corresponding bit in isr. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
305 32099a?avr32?06/09 at32uc3l 17.7.6 mode register name: mode access type: read/write offset: 0x014 reset value: 0x00000000 ?intn: external interrupt n 0: the external interrupt is edge triggered. 1: the external interrupt is level triggered. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable interrupt is edge triggered. 1: the non-maskable interrupt is level triggered. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
306 32099a?avr32?06/09 at32uc3l 17.7.7 edge register name: edge access type: read/write offset: 0x018 reset value: 0x00000000 ?intn: external interrupt n 0: the external interrupt triggers on falling edge. 1: the external interrupt triggers on rising edge. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable interrupt triggers on falling edge. 1: the non-maskable interrupt triggers on rising edge. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
307 32099a?avr32?06/09 at32uc3l 17.7.8 level register name: level access type: read/write offset: 0x01c reset value: 0x00000000 ?intn: external interrupt n 0: the external interrupt triggers on low level. 1: the external interrupt triggers on high level. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable interrupt triggers on low level. 1: the non-maskable interrupt triggers on high level. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
308 32099a?avr32?06/09 at32uc3l 17.7.9 filter register name: filter access type: read/write offset: 0x020 reset value: 0x00000000 ?intn: external interrupt n 0: the external interrupt is not filtered. 1: the external interrupt is filtered. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable interrupt is not filtered. 1: the non-maskable interrupt is filtered. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
309 32099a?avr32?06/09 at32uc3l 17.7.10 test register name: test access type: read/write offset: 0x024 reset value: 0x00000000 ? testen: test enable 0: this bit disables external interrupt test mode. 1: this bit enables extern al interrupt test mode. ?intn: external interrupt n writing a zero to this bit will set the input value to intn to zero, if test mode is enabled. writing a one to this bit will set the input value to intn to one, if test mode is enabled. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt writing a zero to this bit will set the input value to nmi to zero, if test mode is enabled. writing a one to this bit will set the input value to nmi to one, if test mode is enabled. if testen is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be igno red. 31 30 29 28 27 26 25 24 testenint30int29int28int27int26int25int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
310 32099a?avr32?06/09 at32uc3l 17.7.11 asynchronous register name: async access type: read/write offset: 0x028 reset value: 0x00000000 ?intn: external interrupt n 0: the external interrupt is synchronized to clk_sync. 1: the external interrupt is asynchronous. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable interrupt is synchronized to clk_sync. 1: the non-maskable interrupt is asynchronous. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
311 32099a?avr32?06/09 at32uc3l 17.7.12 enable register name: en access type: write-only offset: 0x030 reset value: 0x00000000 ?intn: external interrupt n writing a zero to this bit has no effect. writing a one to this bit will enable the corresponding external interrupt. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt writing a zero to this bit has no effect. writing a one to this bit will enable the non-maskable interrupt. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
312 32099a?avr32?06/09 at32uc3l 17.7.13 disable register name: dis access type: write-only offset: 0x034 reset value: 0x00000000 ?intn: external interrupt n writing a zero to this bit has no effect. writing a one to this bit will disable the corresponding external interrupt. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt writing a zero to this bit has no effect. writing a one to this bit will disable the non-maskable interrupt. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
313 32099a?avr32?06/09 at32uc3l 17.7.14 control register name: ctrl access type: read-only offset: 0x038 reset value: 0x00000000 ?intn: external interrupt n 0: the corresponding external interrupt is disabled. 1: the corresponding external interrupt is enabled. please refer to the module configuration se ction for the number of external interrupts. ? nmi: non-maskable interrupt 0: the non-maskable in terrupt is disabled. 1: the non-maskable interrupt is enabled. 31 30 29 28 27 26 25 24 - int30 int29 int28 int27 int26 int25 int24 23 22 21 20 19 18 17 16 int23int22int21int20int19int18int17int16 15 14 13 12 11 10 9 8 int15int14int13int12int11int10 int9 int8 76543210 int7 int6 int5 int4 int3 int2 int1 nmi
314 32099a?avr32?06/09 at32uc3l 17.7.15 version register name: version access type: read-only offset: 0x3fc reset value: - ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
315 32099a?avr32?06/09 at32uc3l 17.8 module configuration the specific configuration for each eic instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 17-3. module configuration feature eic number of external interrupts, including nmi 6 table 17-4. module clock name module name clock name eic clk_eic table 17-5. register reset values register reset value version 0x00000301
316 32099a?avr32?06/09 at32uc3l 18. frequency meter (freqm) rev: 3.0.1.0 18.1 features ? accurately measures a clock frequency ? selectable reference clock ? a selectable clock can be measured ? ratio can be measured with 24-bit accuracy 18.2 overview the frequency meter (freqm) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 18.3 block diagram figure 18-1. frequency meter block diagram 18.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 18.4.1 power management the device can enter a sleep mode while a measurement is ongoing. however, make sure that neither clk_msr nor clk_ref is stopped in the actual sleep mode. freqm interrupts can wake up the device from sleep modes when the measurement is done, but only from sleep modes where clk_freqm is running. please refe r to the power manager chapter for details. counter clk_ref clk_msr refsel refnum, start clksel start value timer trigger isr
317 32099a?avr32?06/09 at32uc3l 18.4.2 clocks the clock for the freqm bus interface (clk_freqm) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the freqm before disabling the clock, to avoid freezing the freqm ia an undefined state. a set of clocks can be selected as referenc e (clk_ref) and another set of clocks can be selected for measurement (clk_msr). please refer to the clksel and refsel tables in the module configuration chapter for details. 18.4.3 debug operation when an external debugger forces the cpu in to debug mode, the freqm continues normal operation. if the freqm is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 18.4.4 interrupts the freqm interrupt request line is connected to the internal source of the interrupt controller. using the freqm interrupt requires the interrupt controller to be programmed first. 18.5 functional description the freqm accuratly measures the frequency of a clock by comparing the frequency to a known frequency: f clk_msr = (value/refnum)*f clk_ref 18.5.1 reference clock the reference clock selection (refsel) field in the mode register (mode) selects the clock source for clk_ref. the reference clock is enabled by writing a one to the reference clock enable (refcen) bit in the mode register. this clock should have a known frequency. clk_ref needs to be disabled before switching to another clock. the rclkbusy bit in the status register (sr) indicates whether the clock is busy or not. this bit is set when the mode.refcen bit is written. to change clk_ref: ? write a zero to the mode.refcen bit to disable the clock, without changing the other bits/fields in the mode register. ? wait until the sr.rclkbusy bit reads as zero. ? change the mode.refsel field. ? write a one to the mode.refcen bit to enable the clock, without changing the other bits/fields in the mode register. ? wait until the sr.rclkbusy bit reads as zero. to enable clk_ref: ? write the correct value to the mode.refsel field. ? write a one to the mode.refcen to enable the clock, without changing the other bits/fields in the mode register. ? wait until the sr.rclkbusy bit reads as zero. to disable clk_ref:
318 32099a?avr32?06/09 at32uc3l ? write a zero to the mode.refcen to disable he clock, without changing the other bits/fields in the mode register. ? wait until the sr.rclkbusy bit reads as zero. 18.5.2 measurement in the mode register the clock source sele ction (clksel) field selects clk_msr and the number of reference clock cycles (refnum) fi eld selects the duration of the measurement. the duration is given in number of clk_ref periodes. writing a one to the start bit in the control register (ctrl) starts the measurement. the busy bit in sr is cleared when the measurement is done. the result of the measurement can be read from the value register (value). the frequency of the measured clock clk_msr is then: f clk_msr = (value/refnum)*f clk_ref 18.5.3 interrupts the freqm has two interrupt sources: ? done: a frequency measurement is done ? rclkrdy: the reference clock is ready these will generate an interrupt request if the corresponding bit in the interrupt mask register (imr) is set. bits in imr are set by writing a one to the corresponding bit in the interrupt enable register (ier) and cleared by writing a one to this bit in the interrupt disable register (idr). the interrupt request remains active until the correspondi ng bit in the interrupt status register (isr) is cleared by writing a one to this bit in the interrupt clear register (icr).
319 32099a?avr32?06/09 at32uc3l 18.6 user interface note: 1. the reset value for this register is device specific. please refer to the module configuration section at the end of thi s chapter. table 18-1. freqm register memory map offset register register name access reset 0x000 control register ctrl write-only 0x00000000 0x004 mode register mode read/write 0x00000000 0x008 status register status read-only 0x00000000 0x00c value register value read-only 0x00000000 0x010 interrupt enable register ier write-only 0x00000000 0x014 interrupt disable register idr write-only 0x00000000 0x018 interrupt mask register imr read-only 0x00000000 0x01c interrupt status register isr read-only 0x00000000 0x020 interrupt clear register icr write-only 0x00000000 0x3fc version register version read-only - (1)
320 32099a?avr32?06/09 at32uc3l 18.6.1 control register name: ctrl access type: write-only offset: 0x000 reset value: 0x00000000 ?start writing a zero to this bit has no effect. writing a one to this bit will start a measurement. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------start
321 32099a?avr32?06/09 at32uc3l 18.6.2 mode register name: mode access type: read/write offset: 0x004 reset value: 0x00000000 ? refcen: reference clock enable 0: the reference clock is disabled 1: the reference clock is enabled ? clksel: clock source selection selects the source for clk_msr. see table in module configuration chapter for details. ? refnum: number of reference clock cycles setects the duration of a measurement, given in number of clk_ref cycles. ? refsel: reference clock selection selects the source for clk_ref. see table in module configuration chapter for details. 31 30 29 28 27 26 25 24 refcen------- 23 22 21 20 19 18 17 16 - - - clksel 15 14 13 12 11 10 9 8 refnum 76543210 - - - - - refsel
322 32099a?avr32?06/09 at32uc3l 18.6.3 status register name: status access type: read-only offset: 0x008 reset value: 0x00000000 ? rclkbusy: freqm reference clock status 0: the freqm ref clk is ready, so a measurement can start. 1: the freqm ref clk is not ready, so a measurement should not be started. ? busy: freqm status 0: the frequency meter is idle. 1: frequency measurement is on-going. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkbusybusy
323 32099a?avr32?06/09 at32uc3l 18.6.4 value register name: value access type: read-only offset: 0x00c reset value: 0x00000000 ? value: result from measurement. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 value[23:16] 15 14 13 12 11 10 9 8 value[15:8] 76543210 value[7:0]
324 32099a?avr32?06/09 at32uc3l 18.6.5 interrupt enable register name: ier access type: write-only offset: 0x010 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkrdydone
325 32099a?avr32?06/09 at32uc3l 18.6.6 interrupt disable register name: idr access type: write-only offset: 0x014 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkrdydone
326 32099a?avr32?06/09 at32uc3l 18.6.7 interrupt mask register name: imr access type: read-only offset: 0x018 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkrdydone
327 32099a?avr32?06/09 at32uc3l 18.6.8 interrupt status register name: isr access type: read-only offset: 0x01c reset value: 0x00000000 0: the corresponding interrupt is cleared. 1: the corresponding interrupt is pending. a bit in this register is set when the corresponding bit in status has a one to zero transition. a bit in this register is cleared when the corresponding bit in icr is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkrdydone
328 32099a?avr32?06/09 at32uc3l 18.6.9 interrupt clear register name: icr access type: write-only offset: 0x020 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in isr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------rclkrdydone
329 32099a?avr32?06/09 at32uc3l 18.6.10 version register name: version access type: read-only offset: 0x3fc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
330 32099a?avr32?06/09 at32uc3l 18.7 module configuration the specific configuration for each freqm instance is listed in the following tables. the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 18-2. module clock name module name clock name description freqm clk_freqm bus interface clock clk_msr measured clock clk_ref reference clock table 18-3. register reset values register reset value version 0x00000301 table 18-4. clock sources for clk_msr clksel clock/oscillator description 0 clk_cpu the clock the cpu runs on 1 clk_hsb high speed bus clock 2 clk_pba peripheral bus a clock 3 clk_pbb peripheral bus b clock 4 osc0 output clock from oscillator 0 5 osc32k output clock from osc32k 6 rcsys output clock from rcsys oscillator 7 dfll0 output clock from dfll0 8 reserved 9-14 gclk0-5 generic clock 0 through 5 15 rc120m aw clock output clock from rc120m to aw 16 rc120m output clock from rc120m to main clock mux 17 rc32k output clock from rc32k 18-31 reserved table 18-5. clock sources for clk_ref refsel clock/oscillator description 0 rcsys system rc oscillator clock 1 osc32k output clock form osc32k 2-7 reserved
331 32099a?avr32?06/09 at32uc3l 19. general-purpose input/ output controller (gpio) version: 2.1.1.4 19.1 features ? each gpio line features: ? configurable pin-change, rising-edge, or falling-edge interrupt ? configurable peripheral event generator ? glitch filter providing rejection of pulses shorter than one clock cycle ? open drain mode allowing an i/o pin to be shared between th e mcu and external components ? input visibility and output control ? multiplexing of peripheral functions on i/o pins ? programmable internal pull-up resistor ? programmable internal pull-down resistor ? programmable internal buskeeper ? programmable output driver strength ? programmable internal input schmitt trigger ? programmable output slew rate ? optional locking of configuration to avoid accidental reconfiguration 19.2 overview the general purpose input/output controller (gpio) controls the i/o pins of the microcontroller. each gpio pin may be used as a general-purpose i/o or be assigned to a function of an embed- ded peripheral. the gpio is configured using the peripheral bus (pb). some registers can also be configured using the low latency cpu local bus. see section 19.6.2.10 for details.
332 32099a?avr32?06/09 at32uc3l 19.3 block diagram figure 19-1. gpio block diagram 19.4 io lines description interrupt controller power manager embedded peripheral general purpose input/output - gpio gpio interrupt request clk_gpio pin control signals pin pin pin pin pin mcu i/o pins configuration interface pin name description type gpion gpio pin n digital
333 32099a?avr32?06/09 at32uc3l 19.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 19.5.1 power management if the cpu enters a sleep mode that disables cl ocks used by the gpio, the gpio will stop func- tioning and resume operation after the system wakes up from sleep mode. if a peripheral function is configured for a gpio pin, the peripheral will be able to control the gpio pin even if the gpio clock is stopped. 19.5.2 clocks the gpio is connected to a peripheral bus clock (clk_gpio). this clock is generated by the power manager. clk_gpio is enabled at reset, and can be disabled by writing to the power manager. clk_gpio must be enabled in order to access the configuration registers of the gpio or to use the gpio interrupts. after configuring the gpio, the clk_gpio can be disabled by writing to the power manager if interrupts are not used. if the cpu local bus is used to access the c onfiguration interface of the gpio, the clk_gpio must be equal to the cpu clock to avoid data loss. 19.5.3 interrupts the gpio interrupt request lines are connected to the interrupt controller. using the gpio inter- rupts requires the interrupt controller to be programmed first. 19.5.4 peripheral events the gpio peripheral events are connected via the peripheral event system. refer to the peripheral event system chapter for details. 19.5.5 debug operation when an external debugger forces the cpu into debug mode, the gpio continues normal oper- ation. if the gpio is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging.
334 32099a?avr32?06/09 at32uc3l 19.6 functional description the gpio controls the i/o pins of the microcontr oller. the control logic associated with each pin is shown in figure 19-2 . figure 19-2. overview of the gpio 0 1 gpio_odmer 0 1 0 1 gper 1 0 ovr oder pmrn periph. func. a periph.func. b periph. func. c pin puer* pvr 0 1 glitch filter gfer edge detector 1 0 interrupt request imr1 imr0 ier odcrn* osrrn* drive strength and slew rate control ster* schmitt trigger pder* pullup, pulldown and buskeeper .... output output enable input *) register value is overrided if a peripheral function that support this function is enabled ifr
335 32099a?avr32?06/09 at32uc3l 19.6.1 basic operation 19.6.1.1 module configuration the gpio user interface registers are organiz ed into ports and each port controls 32 different gpio pins. most of the registers supports bit wise access operations such as set, clear and tog- gle in addition to the standard word access. for details regarding interface registers, refer to section 19.7 . 19.6.1.2 available features most of the gpio features are configurable for each product. the programmer must refer to the module configuration section and the gpio f unction multiplexing section in the package and pinout chapter for the configuration used in this product. product specific settings includes: ? number of gpio pins ? functions implemented on each pin ? peripheral function(s) multiplexed on each gpio pin ? reset state of registers 19.6.1.3 inputs the level on each gpio pin can be read through the pin value register (pvr). this register indicates the level of the gpio pins regardless of the pins being driven by the gpio or by an external component. note that due to power saving measures , the pvr register will only be updated when the corresponding bit in gper is one or if an interrupt is enabled for the pin, i.e. ier is one for the corresponding pin. 19.6.1.4 output control when the gpio pin is assigned to a peripheral function, i.e. the corresponding bit in gper is zero, the peripheral determines whether the pin is driven or not. when the gpio pin is controlled by the gpio, the value of output driver enable register (oder) determines whether the pin is driven or not. when a bit in this register is one, the corre- sponding gpio pin is driven by the gpio. when the bit is zero, the gpio does not drive the pin. the level driven on a gpio pin can be determined by writing the value to the corresponding bit in the output value register (ovr). 19.6.1.5 peripheral muxing the gpio allows a single gpio pin to be shared by multiple peripheral pins and the gpio itself. peripheral pins sharing the same gpio pin are arranged into peripheral functions that can be selected one at a time. peripheral functions are configured by writing the selected function value to the peripheral mux registers (pmrn). to allow a peripheral pin access to the shared gpio pin, gpio control must be disabled for that pin, i.e. the corresponding bit in gper must read zero. a peripheral function value is set by writing bit zero to pmr0 and bit one to the same index posi- tion in pmr1 and so on. in a system with 4 peripheral functions a,b,c, and d, peripheral function c for gpio pin four is selected by writi ng a zero to bit four in pmr0 and a one to the same bit index in pmr1. refer to the gpio function multiplexing chapter for details regarding pin function configuration for each gpio pin.
336 32099a?avr32?06/09 at32uc3l 19.6.2 advanced operation 19.6.2.1 peripheral i/o pin control when a gpio pin is assigned to a peripheral function, i.e. the corresponding bit in gper is zero, output and output enable is controlled by the selected peripheral pin. in addition the peripheral may control some or all of the other gpio pin functions listed in table 19-1 , if the peripheral sup- ports those features. all pin features not controlled by the selected peripheral is controlled by the gpio. refer to the module configuration section for details regarding implemented gpio pin functions and to the peripheral chapter for details regarding i/o pin function control. 19.6.2.2 pull-up resistor, pull-down resistor and buskeeper control pull-up, pull-down, and buskeeper can be configured for each gpio pin. pull-up allows the pin and any connected net to be pulled up to vdd if the net is not driven. pull-down pulls the net to gnd, while buskeeper keeps the current logic level if the net becomes undriven. pull-up and pull-down are useful for detecting if a pin is unconnected or if a mechanical button is pressed, for various communication protocols an d to keep unconnected pins from floating. pull-up can be enabled and disabled by writing a one and a zero respectively to the correspond- ing bit in the pull-up enable register (puer). pu ll-down can be enabled and disabled by writing a one and a zero respectively to the corresponding bit in the pull-down enable register (pder). to enable the buskeeper for a pin, the corresponding bit in puer and pder must be written to one. 19.6.2.3 output pin timings figure 19-3 shows the timing of the gpio pin when writing to the output value register (ovr). the same timing applies when performing a ?set? or ?clear? access, i.e. writing to ovrs or ovrc. the timing of pvr is also shown. table 19-1. i/o pin function control function name gpio mode peripheral mode output ovr peripheral output enable oder peripheral pull-up puer peripheral if supported, else gpio pull-down pder peripheral if supported, else gpio buskeeper puer&pder peripheral if supported, else gpio drive strength odcrn peripheral if supported, else gpio slew rate osrrn peripheral if supported, else gpio open drain odmr peripheral if supported, else gpio schmitt trigger ster peripheral if supported, else gpio
337 32099a?avr32?06/09 at32uc3l figure 19-3. output pin timings 19.6.2.4 pin output driver control the gpio has registers for contro lling output drive propert ies of each pin, such as output driving capability and slew rate control. the driving capability is contro lled by the output driving capa bility registers (odcrn) and the slew rate settings are controlled by the output slew rate registers (osrrn). for a gpio pin with four different slew rate settings, a slew rate of two can be selected by writing a zero to the osrr0 register at the bit position corresponding to the gpio pin, and a one to the osrr1 at the same bit position. the odcrn registers are configur ed in the same way. 19.6.2.5 open drain mode 19.6.2.6 each gpio pin can be independently configured to operat e in open drain mode. this permits several drivers to be connected on the same gpio pin. the drivers should only actively drive the pin low. an external pull-up resistor (or enabling the internal one) is generally required to guarantee a high level on the pin when no driver is active. the open drain mode is controlled by the open drain mode enable register (odmer) input schmitt trigger each gpio pin can be configured with an input schm itt trigger. an input schmitt trigger filters input signal using an hysteresis function, st opping noise from propagation into the system. the input schmitt trigger can be enabled and disabled by writing a one and a zero respectively to the schmitt trigger enable register (ster). 19.6.2.7 interrupts the gpio can be configured to generate an inte rrupt when it detects a change on a gpio pin. interrupts on a pin are enabled by writing a one to the corresponding bit in the interrupt enable register (ier). the module can be configured to generate an interrupt whenever a pin changes value, or only on rising or falling edges. this is controlled by the interrupt mode registers (imrn). interrupts on a pin can be enabled rega rdless of the gpio pin being controlled by the gpio or assigned to a peripheral function. an interrupt can be generated on each gpio pin. these interrupt generators are further grouped into groups of eight and connected to the interrupt controller. an interrupt request from any of the gpio pin generators in the group will result in an interrupt request from that group to the inter- rupt controller if the corresponding bit for the gp io pin in the ier is set. by grouping interrupt generators into groups of eight, four different interrupt handlers can be installed for each gpio port. pb access pb access clk_gpio write ovr to 1 write ovr to 0 ovr / i/o line pvr
338 32099a?avr32?06/09 at32uc3l the interrupt flag register (ifr) can be read by software to determine which pin(s) caused the interrupt. the interrupt flag must be manually cleared by writing a zero to the corresponding bit in ifr. gpio interrupts will only be gener ated when clk_gpio is enabled. 19.6.2.8 input glitch filter input glitch filters can be enabled on each gpio pi n. when the glitch filter is enabled, a glitch with duration of less than 1 clk_gpio cycle is automatically rejected, while a pulse with dura- tion of 2 clk_gpio cycles or more is accepted. for pulse durations between 1 and 2 clk_gpio cycles, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be guaranteed visible it must exceed 2 clk_gpio cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 clk_gpio cycle. the filter introduces 2 clock cycles latency. the glitch filters are controlled by the glitch filter enable register (gfer). when a bit in gfer is one, the glitch filter on the corresponding pin is enabled. the glitch filter affects only interrupt inputs. inputs to peripherals or the value read through pvr are not affected by the glitch filters. 19.6.2.9 interrupt timings figure 19-4 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is disabled. for the pulse to be registered, it must be sampled at the rising edge of the clock. in this example, this is not the case for the first pulse. the second pulse is sampled on a rising edge and will trigger an interrupt request. figure 19-4. interrupt timing with glitch filter disabled figure 19-5 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. for the pulse to be registered, it must be sampled on two subsequent rising edges. in the example, the first pulse is rejected while th e second pulse is accepted and causes an inter- rupt request. figure 19-5. interrupt timing with g litch filter enabled clk_gpio pin level ifr clk_gpio pin level ifr
339 32099a?avr32?06/09 at32uc3l 19.6.2.10 cpu local bus the cpu local bus can be used for application where low latency read and write access to the output value register (ovr) and output drive enable register (oder) is required. the cpu local bus allows the cpu to configure the mentioned gpio registers directly, bypassing the shared peripheral bus (pb). to avoid data loss when using the cpu local bus, the clk_gpio must run at the same fre- quency as the clk_cpu. see section 19.5.2 for details. the cpu local bus is mapped to a different base address than the gpio but the over and oder offsets are the same. see the cpu local bus mapping section in the memories chapter for details. 19.6.2.11 peripheral events peripheral events allow direct peripheral to peripheral communication of specified events. see the peripheral event system chapter for more information. the gpio can be programmed to output peripheral events whenever an interrupt condition is detected, such as pin value chan ge, or only when a rising or fallin g edge is detected. peripheral event on a pin is enabled by writing a one to th e corresponding bit in the event enable register (ever). the peripheral event trigger mode is s hared with the interrupt trigger and is configured by writing to the imr0 and imr1 registers. interrupt does not need to be enabled on a pin when peripheral events are enabled. pe ripheral events are also affected by the input glitch filter set- tings. see section 19.6.2.8 for more information. a peripheral event can be generated on each gpio pin. each port can then have up to 32 peripheral event generators. gro ups of eight peripheral event g enerators in each port are ored together to form a peripheral event line, so that each port has four peripheral event lines con- nected to the peripheral event system.
340 32099a?avr32?06/09 at32uc3l 19.7 user interface the gpio controller manages all the gpio pins on the avr32 microcontroller. the pins are managed as 32-bit ports that are configurable through a peripheral bus (pb) interface. each port has a set of configuration registers. the ov erall memory map of the gpio is shown below. the number of pins and hence the number of ports is product specific. figure 19-6. port configuration registers in the peripheral muxing table in the package and pinout chapter each gpio pin has a unique number. note that the pa, pb, pc and px ports do not directly correspond to the gpio ports. to find the corresponding port and pin the following formulas can be used: gpio port = floor((gpio number) / 32), example: floor((36)/32) = 1 gpio pin = gpio number % 32, example: 36 % 32 = 4 figure 19-6 on page 340 shows the configuration registers for one port. addresses shown are relative to the port address offset. the specific address of a configuration register is found by adding the register offset and the port offset to the gpio start address. one bit in each of the configuration registers corresponds to a gpio pin. 19.7.1 access types most configuration register can be accessed in four different ways. the first address location can be used to write the register directly. this address can also be used to read the register value. the following addresses facilitate th ree different types of write acce ss to the regi ster. performing a ?set? access, all bits written to one will be se t. bits written to zero will be unchanged by the operation. performing a ?clear? a ccess, all bits written to one will be cleared. bits written to zero will be unchanged by the operation. finally, a toggle access will toggle the value of all bits writ- port 0 configuration registers port 1 configuration registers port 2 configuration registers port n configuration registers 0x0000 0x0200 0x0400 n*0x200 ?.
341 32099a?avr32?06/09 at32uc3l ten to one. again all bits written to zero remain unchanged. note that for some registers (e.g. ifr), not all access methods are permitted. note that for ports with less than 32 bits, the corresponding control registers will have unused bits. this is also the case for features that are not implemented for a specific pin. writing to an unused bit will have no effect. reading unused bits will always return 0. 19.7.2 configuration protection in order to protect the configuration of individual gpio pins from software failure, configuration bits for individual gpio pins may be locked by writing a one to the corresponding bit in the lock register. while this bit is one, any write to the same bit position in any lockable gpio register will not have an effect. the registers required to clear bits in the lock register are protected by the access protection mechanism described in section 19.7.3 , ensuring the lock mechanis m itself is robust against software failure. 19.7.3 access protection in order to protect critical registers from software failure, some registers are protected by a key protection mechanism. these registers can only be changed by first writing the unlock regis- ter, then the protected register. protected registers are indicated in table 19-2 . the unlock register contains a key field which must always be written to 0xaa, and an offset field corre- sponding to the offset of the register to be modified. the next write operation resets the unlock register, so if the register is to be modified again, the unlock register must be written again. attempting to write to a protected register without first writing the unlock register results in the write operation being discarded, and the access error bit in the access status register (asr.ae) will be set. table 19-2. gpio register memory map offset register function register name access reset configuration protection access protection 0x000 gpio enable register read/write gper read/write (1) y n 0x004 gpio enable register set gpers write-only y n 0x008 gpio enable register clear gperc write-only y n 0x00c gpio enable register toggle gpert write-only y n 0x010 peripheral mux register 0 read/write pmr0 read/write (1) y n 0x014 peripheral mux register 0 set pmr0s write-only y n 0x018 peripheral mux register 0 clear pmr0c write-only y n 0x01c peripheral mux register 0 toggle pmr0t write-only y n 0x020 peripheral mux register 1 read/write pmr1 read/write (1) y n 0x024 peripheral mux register 1 set pmr1s write-only y n 0x028 peripheral mux register 1 clear pmr1c write-only y n 0x02c peripheral mux register 1 toggle pmr1t write-only y n
342 32099a?avr32?06/09 at32uc3l 0x030 peripheral mux register 2 read/write pmr2 read/write (1) y n 0x034 peripheral mux register 2 set pmr2s write-only y n 0x038 peripheral mux register 2 clear pmr2c write-only y n 0x03c peripheral mux register 2 toggle pmr2t write-only y n 0x040 output driver enable register read/write oder read/write (1) y n 0x044 output driver enable register set oders write-only y n 0x048 output driver enable register clear oderc write-only y n 0x04c output driver enable re gister toggle odert write-only y n 0x050 output value register read/write ovr read/write (1) n n 0x054 output value register set ovrs write-only n n 0x058 output value register clear ovrc write-only n n 0x05c output value register toggle ovrt write-only n n 0x060 pin value register read pvr read-only depen ding on pin states nn 0x064 pin value register - - - n n 0x068 pin value register - - - n n 0x06c pin value register - - - n n 0x070 pull-up enable register read/write puer read/write (1) y n 0x074 pull-up enable register set puers write-only y n 0x078 pull-up enable register clear puerc write-only y n 0x07c pull-up enable register toggle puert write-only y n 0x080 pull-down enable register read/write pder read/write (1) y n 0x084 pull-down enable register set pders write-only y n 0x088 pull-down enable register clear pderc write-only y n 0x08c pull-down enable register toggle pdert write-only y n 0x090 interrupt enable register read/write ier read/write (1) n n 0x094 interrupt enable register set iers write-only n n 0x098 interrupt enable register clear ierc write-only n n 0x09c interrupt enable register toggle iert write-only n n 0x0a0 interrupt mode register 0 read/write imr0 read/write (1) n n 0x0a4 interrupt mode regist er 0 set imr0s write-only n n 0x0a8 interrupt mode register 0 clear imr0c write-only n n 0x0ac interrupt mode register 0 toggle imr0t write-only n n 0x0b0 interrupt mode register 1 read/write imr1 read/write (1) n n table 19-2. gpio register memory map offset register function register name access reset configuration protection access protection
343 32099a?avr32?06/09 at32uc3l 0x0b4 interrupt mode register 1 set imr1s write-only n n 0x0b8 interrupt mode register 1 clear imr1c write-only n n 0x0bc interrupt mode register 1 toggle imr1t write-only n n 0x0c0 glitch filter enable regist er read/write gfer read/write (1) n n 0x0c4 glitch filter enable r egister set gfers write-only n n 0x0c8 glitch filter enable register clear gferc write-only n n 0x0cc glitch filter enable r egister toggle gfert write-only n n 0x0d0 interrupt flag register read ifr read-only (1) n n 0x0d4 interrupt flag register - - - n n 0x0d8 interrupt flag register clear ifrc write-only n n 0x0dc interrupt flag register - - - n n 0x0e0 open drain mode enable register read/write odmer read/write (1) y n 0x0e4 open drain mode enable register set odmer s write-only y n 0x0e8 open drain mode enable register clear odmer c write-only y n 0x0ec open drain mode enable register toggle odmer t write-only y n 0x0f0- 0x0fc reserved - - - - 0x100 output driving capability register 0 read/write odcr0 read/write (1) y n 0x104 output driving capability register 0 set odcr0s write-only y n 0x108 output driving capability register 0 clear odcr0c write-only y n 0x10c output driving capability register 0 toggle odcr0t write-only y n 0x110 output driving capability register 1 read odcr1 read/write (1) y n 0x114 output driving capability register 1 set odcr1s write-only y n 0x118 output driving capability register 1 clear odcr1c write-only y n 0x11c output driving capability register 1 toggle odcr1t write-only y n 0x120- 0x12c reserved - - - 0x130 output slew rate register 0 read osrr0 read/write y n 0x134 output slew rate register 0 set osrr0s write-only y n 0x138 output slew rate register 0 clear osrr0c write-only y n 0x13c output slew rate register 0 toggle osrr0t write-only y n 0x140- 0x15c reserved - - - 0x160 schmitt trigger enable register read ster read/write (1) y n table 19-2. gpio register memory map offset register function register name access reset configuration protection access protection
344 32099a?avr32?06/09 at32uc3l 0x164 schmitt trigger enable register set sters write-only y n 0x168 schmitt trigger enable register clear sterc write-only y n 0x16c schmitt trigger enable register toggle stert write-only y n 0x170- 0x17c reserved - - - 0x180 event enable register read ever read/write (1) n n 0x184 event enable register set evers write-only n n 0x188 event enable register clear everc write-only n n 0x18c event enable register toggle evert write-only n n 0x190- 0x19c reserved - - - 0x1a0 lock register read/write lock read/write (1) n y 0x1a4 lock register set locks write-only n n 0x1a8 lock register clear lockc write-only n y 0x1ac lock register toggle lockt write-only n y 0x1b0- 0x1dc reserved - - - 0x1e0 unlock register read/write unlock write-only n n 0x1e4 access status register read/write asr read/write n 0x1e8- 0x1f4 reserved - - - 0x1f8 parameter register read pa r a m e ter read-only - (1) n n 0x1fc version register read versio n read-only - (1) n n 1. the reset values for these registers are device specific. please refer to the module configuration section at the end of this chapter. table 19-2. gpio register memory map offset register function register name access reset configuration protection access protection
345 32099a?avr32?06/09 at32uc3l 19.7.4 gpio enable register name: gper access: read/write, set, clear, toggle offset : 0x000, 0x004, 0x008, 0x00c reset value: - ? p0-p31: gpio enable 0: a peripheral function controls the corresponding pin. 1: the gpio controls the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
346 32099a?avr32?06/09 at32uc3l 19.7.5 peripheral mux register 0 name: pmr0 access: read/write, set, clear, toggle offset : 0x010, 0x014, 0x018, 0x01c reset value: - ? p0-31: peripheral mult iplexer select bit 0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
347 32099a?avr32?06/09 at32uc3l 19.7.6 peripheral mux register 1 name: pmr1 access: read/write, set, clear, toggle offset : 0x020, 0x024, 0x028, 0x02c reset value: - ? p0-31: peripheral mult iplexer select bit 1 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
348 32099a?avr32?06/09 at32uc3l 19.7.7 peripheral mux register 2 name: pmr2 access: read/write, set, clear, toggle offset : 0x030, 0x034, 0x038, 0x03c reset value: - ? p0-31: peripheral mult iplexer select bit 2 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 {pmr2, pmr1, pmr0} selected peripheral function 000 a 001 b 010 c 011 d 100 e 101 f 110 g 111 h
349 32099a?avr32?06/09 at32uc3l 19.7.8 output driver enable register name: oder access: read/write, set, clear, toggle offset : 0x040, 0x044, 0x048, 0x04c reset value: - ? p0-31: output driver enable 0: the output driver is disabled for the corresponding pin. 1: the output driver is enabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
350 32099a?avr32?06/09 at32uc3l 19.7.9 output value register name: ovr access: read/write, set, clear, toggle offset : 0x050, 0x054, 0x058, 0x05c reset value: - ? p0-31: output value 0: the value to be driven on the gpio pin is 0. 1: the value to be driven on the gpio pin is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
351 32099a?avr32?06/09 at32uc3l 19.7.10 pin value register name: pvr access: read-only offset : 0x060, 0x064, 0x068, 0x06c reset value: depending on pin states ? p0-31: pin value 0: the gpio pin is at level zero. 1: the gpio pin is at level one. note that the level of a pin can only be read when the corresponding pin in gper is one or interrupt is enabled for the pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
352 32099a?avr32?06/09 at32uc3l 19.7.11 pull-up enable register name: puer access: read/write, set, clear, toggle offset : 0x070, 0x074, 0x078, 0x07c reset value: - ? p0-31: pull-up enable 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
353 32099a?avr32?06/09 at32uc3l 19.7.12 pull-down enable register name: pder access: read/write, set, clear, toggle offset : 0x080, 0x084, 0x088, 0x08c reset value: - ? p0-31: pull-down enable 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 {puer, pder} selected function 00 disabled 01 pull-down enabled 10 pull-up enabled 11 buskeeper enabled
354 32099a?avr32?06/09 at32uc3l 19.7.13 interrupt enable register name: ier access: read/write, set, clear, toggle offset : 0x090, 0x094, 0x098, 0x09c reset value: - ? p0-31: interrupt enable 0: interrupt is disabled for the corresponding pin. 1; interrupt is enabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
355 32099a?avr32?06/09 at32uc3l 19.7.14 interrupt mode register 0 name: imr0 access: read/write, set, clear, toggle offset : 0x0a0, 0x0a4, 0x0a8, 0x0ac reset value: - ? p0-31: interrupt mode bit 0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
356 32099a?avr32?06/09 at32uc3l 19.7.15 interrupt mode register 1 name: imr1 access: read/write, set, clear, toggle offset : 0x0b0, 0x0b4, 0x0b8, 0x0bc reset value: - ? p0-31: interrupt mode bit 1 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 {imr1, imr0} interrupt mode 00 pin change 01 rising edge 10 falling edge 11 reserved
357 32099a?avr32?06/09 at32uc3l 19.7.16 glitch filter enable register name: gfer access: read/write, set, clear, toggle offset : 0x0c0, 0x0c4, 0x0c8, 0x0cc reset value: - ? p0-31: glitch filter enable 0: glitch filter is disabled for the corresponding pin. 1: glitch filter is enabled for the corresponding pin. note! the value of this register should only be changed when the corresponding bit in ier is zero. updating gfer while interrupt on the corresponding pin is enabled can cause an unintentional interrupt to be triggered. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
358 32099a?avr32?06/09 at32uc3l 19.7.17 interrupt flag register name: ifr access: read, clear offset :0x0d0, 0x0d8 reset value: - ? p0-31: interrupt flag 0: an interrupt condition has been detected on the corresponding pin. 1: no interrupt condition has been detected on the corresponding pin. the number of interrupt request lines depe nds on the number of gpio pins on the mcu. refer to the product specific data for details. note also that a bit in the interrupt flag register is only valid if the corresponding bit in ier is one. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
359 32099a?avr32?06/09 at32uc3l 19.7.18 open drain mode enable register name: odmer access: read/write, set, clear, toggle offset : 0x0e0, 0x0e4, 0x0e8, 0x0ec reset value: - ? p0-31: open drain mode enable 0: open drain mode is disabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
360 32099a?avr32?06/09 at32uc3l 19.7.19 1: open drain mode is enabled for the corresponding pin. output driving capability register 0 name: odcr0 access: read/write, set, clear, toggle offset : 0x100, 0x104, 0x108, 0x10c reset value: - ? p0-31: output driving capability register bit 0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
361 32099a?avr32?06/09 at32uc3l 19.7.20 output driving capability register 1 name: odcr1 access: read/write, set, clear, toggle offset : 0x110, 0x114, 0x118, 0x11c reset value: - ? p0-31: output driving capability bit 1 for the actual drive strength of the pin, please refer to the electrical characteristics chapter. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 {odcr1, odcr0} interrupt mode 00 lowest drive strength 01 ... 10 ... 11 highest drive strength
362 32099a?avr32?06/09 at32uc3l 19.7.21 output slew rate register 0 name: osrr0 access: read/write, set, clear, toggle offset : 0x130, 0x134, 0x138, 0x13c reset value: - ? p0-31: output slew rate control enable 0: slew rate control is disabled for the corresponding pin. 1: slew rate control is enabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
363 32099a?avr32?06/09 at32uc3l 19.7.22 schmitt trigger enable register name: ster access: read/write, set, clear, toggle offset : 0x160, 0x164, 0x168, 0x16c reset value: - ? p0-31: schmitt trigger enable 0: schmitt trigger is disabled for the corresponding pin. 1: schmitt trigger is enabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
364 32099a?avr32?06/09 at32uc3l 19.7.23 event enable register name: ever access: read/write, set, clear, toggle offset : 0x180, 0x184, 0x188, 0x18c reset value: - ? p0-31: event enable 0: peripheral event is disabled for the corresponding pin. 1: peripheral event is enabled for the corresponding pin. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
365 32099a?avr32?06/09 at32uc3l 19.7.24 lock register name: lock access: read/write, set, clear, toggle offset : 0x1a0, 0x1a4, 0x1a8, 0x1ac reset value: - ? p0-31: lock state 0: pin is unlocked. the corresponding bit can be changed in any gpio register for this port. 1: pin is locked. the corresponding bit can not be changed in any gpio register for this port. the lock, lockc, and lockt registers are protected, which means they can only be written immediately after a write to the unlock register with the proper key and offset. locks is not protected, and can be written at any time. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
366 32099a?avr32?06/09 at32uc3l 19.7.25 unlock register name: unlock access: write-only offset :0x1e0 reset value: - ? offset: register offset this field must be written with the register offset value of the register to unlock. note that the two lsbs of this register wi ll always read as zero. ?key: unlocking key this bitfield must be written to 0xaa for a wr ite to this register to have an effect. this register always reads as zero. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------ offset 76543210 offset
367 32099a?avr32?06/09 at32uc3l 19.7.26 access status register name: asr access: read/write offset :0x1e4 reset value: - ? ae: access error this bit is set when a write to a locked register occurs. this bit can be written to 0 by software. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------ae
368 32099a?avr32?06/09 at32uc3l 19.7.27 parameter register name: parameter access type: read-only offset :0x1f8 reset value: - ? parameter: 0: this pin is not implemented in this gpio port. 1: this pin is implemented in this gpio port. there is one parameter register per gpio port. 31 30 29 28 27 26 25 24 pa r a m e t e r 23 22 21 20 19 18 17 16 pa r a m e t e r 15 14 13 12 11 10 9 8 pa r a m e t e r 76543210 pa r a m e t e r
369 32099a?avr32?06/09 at32uc3l 19.7.28 version register name: version access type: read-only offset :0x1fc reset value: - ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ---- version[11:8] 76543210 version[7:0]
370 32099a?avr32?06/09 at32uc3l 19.8 module configuration the specific configuration for each gpio instance is listed in the following tables. the module bus clocks listed here are conn ected to the system bus clocks. refer to the power manager chapter for details. the reset values for all gpio registers are zero, with the following exceptions: table 19-3. module configuration feature gpio number of gpio ports 2 number of peripheral functions 8 table 19-4. implemented pin functions pin function implemented notes pull-up yes controlled by puer or peripheral pull-down no writing to pder has no effect buskeeper no writing a one to puer and pder only enabled pull-up drive strength no writing to odcrn has no effect slew rate no writing to osrrn has no effect open drain no writing to odmr has no effect schmitt trigger no writing to ster has no effect table 19-5. module clock name module name clock name gpio clk_gpio table 19-6. register reset values port register reset value 0 gper 0x0026ffaf 0 puer 0x00000001 0 parameter 0x0effffff 0 version 0x00000211 1 gper 0x00001fcf 1 puer 0x00000000 1 parameter 0x00001fff 1 version 0x00000211
371 32099a?avr32?06/09 at32uc3l 20. universal synchronous asynchrono us receiver transmitter (usart) rev.4.4.0.3 20.1 features ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multidrop mode with address generation and detection ? spi mode ? master or slave ? serial clock programmable phase and polarity ? spi serial clock (clk) frequency up to internal clock frequency clk_usart/4 ? lin mode ? compliant with lin 1.3 and lin 2.0 sp ecifications ? master or slave ? processing of frames with up to 256 data bytes ? response data length can be configurable or defined automatica lly by the identifier ? self synchronization in slave node configuration ? automatic processing and verification of the ?synch break? an d the ?synch field? ? the ?synch break? is detected even if it is partially superimposed with a data byte ? automatic identifier parity ca lculation/sending and verification ? parity sending and verification can be disabled ? automatic checksum calculati on/sending and verification ? checksum sending and veri fication can be disabled ? support both ?classic? an d ?enhanced? checksum types ? full lin error checking and reporting ? frame slot mode: the master allocates sl ots to the scheduled frames automatically. ? generation of the wakeup signal ? test modes ? remote loopback, local loopback, automatic echo ? supports connection of two periph eral dma controller channels (pdca) ? offers buffer transfer without processor intervention 20.2 overview the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission.
372 32099a?avr32?06/09 at32uc3l the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485, lin and spi buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdca provides chained buffer manage- ment without any intervention of the processor. 20.3 block diagram figure 20-1. usart block diagram peripheral dma controller channel channel interrupt controller power manager div receiver transmitter user interface i/o controller rxd rts txd cts clk baudrate generator usart interrupt clk_usart clk_usart/div usart peripheral bus
373 32099a?avr32?06/09 at32uc3l 20.4 application block diagram figure 20-2. application block diagram table 20-1. spi operating mode pin usart spi slave spi master rxd rxd mosi miso txd txd miso mosi rts rts ? cs cts cts cs ? smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp lin driver lin transceiver spi driver spi bus
374 32099a?avr32?06/09 at32uc3l 20.5 i/o lines description table 20-2. i/o lines description name description type active level clk serial clock i/o txd transmit serial data or master out slave in (mosi) in spi master mode or master in slave out (miso) in spi slave mode output rxd receive serial data or master in slave out (miso) in spi master mode or master out slave in (mosi) in spi slave mode input cts clear to send or slave select (nss) in spi slave mode input low rts request to send or slave select (nss) in spi master mode output low
375 32099a?avr32?06/09 at32uc3l 20.6 product dependencies 20.6.1 i/o lines the pins used for interfacing the usart may be multiplexed with the i/o controller lines. the programmer must first program the i/o controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the i/o controller. to prevent the txd line from falling when the usart is di sabled, the use of an internal pull up is mandatory. if the hardware handshaking feature or modem mode is used, the internal pull up on txd must also be enabled. 20.6.2 clocks the clock for the usart bus interface (clk_usart) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to dis- able the usart before disabling the clock, to avoid freezing the usart in an undefined state. 20.6.3 interrupts the usart interrupt request line is connected to the interrupt controller. using the usart interrupt requires the interrupt controller to be programmed
376 32099a?avr32?06/09 at32uc3l first.
377 32099a?avr32?06/09 at32uc3l 20.7 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? spi mode ? master or slave ? serial clock programmable phase and polarity ? spi serial clock (clk) frequency up to internal clock frequency clk_usart/4 ? lin mode ? compliant with lin 1.3 and lin 2.0 sp ecifications ? master or slave ? processing of frames with up to 256 data bytes ? response data length can be configurable or defined automatica lly by the identifier ? self synchronization in slave node configuration ? automatic processing and verification of the ?synch break? an d the ?synch field? ? the ?synch break? is detected even if it is partially superimposed with a data byte ? automatic identifier parity ca lculation/sending and verification ? parity sending and verification can be disabled ? automatic checksum calculati on/sending and verification ? checksum sending and veri fication can be disabled ? support both ?classic? an d ?enhanced? checksum types ? full lin error checking and reporting ? frame slot mode: the master allocates sl ots to the scheduled frames automatically. ? generation of the wakeup signal ? test modes
378 32099a?avr32?06/09 at32uc3l ? remote loopback, local loopback, automatic echo 20.7.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (mr) between: ? clk_usart ? a division of clk_usart, the divider being product dependent, but generally set to 8 ? the external clock, available on the clk pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (brgr). if cd is programmed at 0, the baud rate gener- ator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external clk clock is selected, the duration of the low and high levels of the signal pro- vided on the clk pin must be longer than a clk_usart period. the frequency of the signal provided on clk must be at least 4.5 times lower than clk_usart. figure 20-3. baud rate generator 20.7.1.1 baud rate in asynchronous mode if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. 16-bit counter cd usclks cd clk_usart clk_usart/div reserved clk sync sync usclks= 3 fidi over sampling divider baudrate clock sampling clock 1 0 0 clk 0 1 2 3 >1 1 1 0 0 baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
379 32099a?avr32?06/09 at32uc3l this gives a maximum baud rate of clk_usar t divided by 8, assuming that clk_usart is the highest possible clock and that over is programmed at 1. 20.7.1.2 baud rate calculation example table 20-3 on page 379 shows calculations of cd to obtain a baud rate at 38400 bauds for dif- ferent source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. table 20-3. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% baudrate clkusart () cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? =
380 32099a?avr32?06/09 at32uc3l 20.7.1.3 fractional baud rate in asynchronous mode the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (brgr). if fp is not 0, the fractional part is acti vated. the resolution is one eighth of the clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: figure 20-4. fractional baud rate generator 20.7.1.4 baud rate in synchronous mode or spi mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart clk pin. no division is active. the value written in brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - = usclks cd modulus control fp fp cd glitch-free logic 16-bit counter over fidi sync sampling divider clk_usart clk_usart/div reserved clk clk baudrate clock sampling clock sync usclks = 3 >1 1 2 3 0 0 1 0 1 1 0 0 baudrate selectedclock cd ------------------------------------- - =
381 32099a?avr32?06/09 at32uc3l when either the external clock clk or the inte rnal clock divided (clk_usart/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the clk pin. if the internal clock clk_usart is selected, the baud rate generator ensures a 50:50 duty cycle on the clk pin, even if the value programmed in cd is odd. 20.7.1.5 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: ? b is the bit rate ? di is the bit-rate adjustment factor ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 20-4 on page 381 . fi is a binary value encoded on a 4-bit field, named fi, as represented in table 20-5 on page 381 . table 20-6 on page 381 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (mr) is first divided by the valu e programmed in the field cd in the baud rate generator register (brgr). the resulting clock can be provided to the clk pin to feed the smart card clock inputs. this means that the clko bit can be set in mr. b di fi ----- - f = table 20-4. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 20-5. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 20-6. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
382 32099a?avr32?06/09 at32uc3l this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 20-5 on page 382 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. figure 20-5. elementary time unit (etu) 20.7.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx re spectively, in the control register (cr). the software resets clear the status flag and rese t internal state machines but the user interface configuration registers hold the value configured prior to software reset. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (thr). if a time- guard is programmed, it is handled normally. 20.7.3 synchronous and asynchronous modes 20.7.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two 1 etu fi_di_ratio iso7816 clock cycles iso7816 clock on clk iso7816 i/o line on txd
383 32099a?avr32?06/09 at32uc3l stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in mr configures wh ich data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less signi ficant bit is sent first. the number of stop bits is selected by the nbstop field in mr. the 1.5 stop bit is supported in asynchronous mode only. figure 20-6. character transmit the characters are sent by writing in the tr ansmit holding register (thr). the transmitter reports two status bits in the channel status register (csr): txrdy (transmitter ready), which indicates that thr is empt y and txempty, which indicates that all the characters written in thr have been processed. when the current character processing is completed, the last character written in thr is transferred into the shift register of the transmitter and thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in thr while txrdy is low has no effect and the written character is lost. figure 20-7. transmitter status 20.7.3.2 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (mr). d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
384 32099a?avr32?06/09 at32uc3l the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl , mode9, msbf and par. for the synchronization mechanism only , the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the st op bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 20-8 on page 384 and figure 20-9 on page 384 illustrate start detection and character reception when usart operates in asynchronous mode. figure 20-8. asynchronous start detection figure 20-9. asynchronous character reception sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
385 32099a?avr32?06/09 at32uc3l 20.7.3.3 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a lo w level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 20-10 on page 385 illustrates a character rece ption in synch ronous mode. figure 20-10. synchronous mode character reception 20.7.3.4 receiver operations when a character reception is completed, it is transferred to the receive holding register (rhr) and the rxrdy bit in the st atus register (csr) rises. if a character is completed while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (cr) with the rststa (reset status) bit at 1. figure 20-11. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read rhr
386 32099a?avr32?06/09 at32uc3l 20.7.3.5 parity the usart supports five parity modes selected by programming the par field in the mode register (mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 387 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num- ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 20-7 on page 386 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (csr). the pare bit can be cleared by writing the control register (cr) with the rst- sta bit at 1. figure 20-12 on page 387 illustrates the parity bit st atus setting and clearing. table 20-7. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
387 32099a?avr32?06/09 at32uc3l figure 20-12. parity error 20.7.3.6 multidrop mode if the par field in the mode register (mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentia tes the data characters and the address charac- ters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bit set) when senda is written to cr. in this case, the next byte written to thr is transmitted as an address. any character written in thr without having written the command senda is transmitted normally with the parity at 0. 20.7.3.7 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit peri- ods programmed in tg in addition to the number of stop bits. as illustrated in figure 20-13 on page 388 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 durin g the timeguard transmission if a character has been written in thr. txempty remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write cr pare rxrdy rststa = 1
388 32099a?avr32?06/09 at32uc3l figure 20-13. timeguard operations table 20-8 on page 388 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 20.7.3.8 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeou t bit in csr remains at 0. otherwise, the receiver loads a counter with the value programmed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the coun- ter reaches 0, the timeout bit in the status register rises. then, the user can either: ? stop the counter clock until a new character is received. this is performed by writing the control register (cr) with the sttto (start time-out) bit at 1. in this case, the idle state on rxd before a new character is received will not provide a time-out. this prevents having to d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 20-8. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
389 32099a?avr32?06/09 at32uc3l handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a fram e is received. ? obtain an interrupt while no character is receiv ed. this is performed by writing cr with the retto (reload and start time-out) bit at 1. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so t hat a user time-out can be handled, for example when no key is pressed on a keyboard. figure 20-14 on page 389 shows the block diagram of the receiver time-out feature. figure 20-14. receiver time-o ut block diagram table 20-9 on page 389 gives the maximum time-out period for some standard baud rates. table 20-9. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
390 32099a?avr32?06/09 at32uc3l 20.7.3.9 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (cr) with the rststa bit at 1. figure 20-15. framing error status 20.7.3.10 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift reg- ister or in thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, t he character is first completed be fore the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 56000 18 1 170 57600 17 1 138 200000 5 328 table 20-9. maximum time-out period (continued) baud rate bit time time-out d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write cr frame rxrdy rststa = 1
391 32099a?avr32?06/09 at32uc3l the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing cr with the both sttbrk and stpbrk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte writ- ten into the transmit holding re gister while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 20-16 on page 391 illustrates the effect of both the start break (sttbrk ) and stop break (stpbrk) commands on the txd line. figure 20-16. break transmission 20.7.3.11 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in csr. this bit may be cleared by writing the control register (cr) with the bit rststa at 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 20.7.3.12 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 20-17 on page 392 . d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
392 32099a?avr32?06/09 at32uc3l figure 20-17. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the mode field in the mode register (mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires usin g the pdca channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 20-18 on page 392 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) coming from the pdca channel is high. norm ally, the remote device does not start trans- mitting while its cts pin (driven by rts) is hi gh. as soon as the receiver is enabled, the rts falls, indicating to the remote device that it can start transmitting. defining a new buffer to the pdca clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 20-18. receiver behavior when operating with hardware handshaking figure 20-19 on page 392 shows how the transmitter ope rates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the curr ent character and transmission of the next char- acter happens as soon as the pin cts falls. figure 20-19. transmitter behavior when operating with hardware handshaking usart txd cts remote device rxd txd rxd rts rts cts rts rxbuff write cr rxen = 1 rxd rxdis = 1 cts txd
393 32099a?avr32?06/09 at32uc3l 20.7.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the mode field in the mode regis- ter (mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. 20.7.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see ?baud rate generator? on page 378 ). the usart connects to a smart card as shown in figure 20-20 on page 393 . the txd line becomes bidirectional and the baud rate generator feeds the iso7816 clock on the clk pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. figure 20-20. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?mode register? on page 426 and ?par: parity type? on page 427 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this for- mat and the user has to perform an exclusive or on the data before writing it in the transmit holding register (thr) or after reading it in the receive holding register (rhr). 20.7.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 20-21 on page 394 . clk txd usart clk i/o smart card
394 32099a?avr32?06/09 at32uc3l if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 20-22 on page 394 . this error bit is also nam ed nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (rhr). it appropriately sets the pare bit in the status register (sr) so that the software can handle the error. figure 20-21. t = 0 protocol without parity error figure 20-22. t = 0 protocol with parity error 20.7.4.3 receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (ner) register. the nb_errors field ca n record up to 255 errors. reading ner auto- matically clears the nb_errors field. 20.7.4.4 receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inack bit is set in the status register (sr). the inack bit can be cleared by writing the control re gister (cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. 20.7.4.5 transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (mr) at a value higher than 0. each character can be transmitted up to eight times; the firs t transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
395 32099a?avr32?06/09 at32uc3l when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in csr can be cleared by writing the control register with the rsit bit at 1. 20.7.4.6 disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (mr). the maximum num- ber of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 20.7.4.7 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the par e bit in the channel status register (csr). 20.7.5 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 20-23 on page 395 . figure 20-23. typical connection to a rs485 bus the usart is set in rs485 mode by programming the mode field in the mode register (mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 20-24 on page 396 gives an example of the rts waveform during a character transmission when the timeguard is enabled. usart rts txd rxd differential bus
396 32099a?avr32?06/09 at32uc3l figure 20-24. example of rts drive with timeguard d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write thr txrdy txempty rts
397 32099a?avr32?06/09 at32uc3l 20.7.6 spi mode the serial peripheral interface (spi) mode is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master? which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turns being masters and one master may simultaneously shift data into multiple slaves. (multiple master protocol is the opposite of single master protocol, where one cpu is always the master while all of the others are always slaves.) however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when its nss signal is asserted by the master. the usart in spi master mode can address only one spi slave because it can generate only one nss signal. the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input of the slave. ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. ? serial clock (clk): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates. the clk line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows the master to select or deselect the slave. 20.7.6.1 modes of operation the usart can operate in master mode or in slave mode. operation in spi master mode is programmed by writing at 0xe the mode field in the mode register. in this case the spi lines must be connected as described below: ? the mosi line is driven by the output pin txd ? the miso line drives the input pin rxd ? the clk line is driven by the output pin clk ? the nss line is driven by the output pin rts operation in spi slave mode is programmed by writing at 0xf the mode field in the mode reg- ister. in this case the spi lines must be connected as described below: ? the mosi line drives the input pin rxd ? the miso line is driven by the output pin txd ? the clk line drives the input pin clk ? the nss line drives the input pin cts in order to avoid unpredicted behavior, any change of the spi mode must be followed by a soft- ware reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (see section 20.7.7.2 on page 402 ).
398 32099a?avr32?06/09 at32uc3l 20.7.6.2 baud rate in spi mode, the baudrate generator operates in the same way as in usart synchronous mode: see ?baud rate in synchronous mode or spi mode? on page 380. however, there are some restrictions: in spi master mode: ? the external clock clk must not be selected (usclks 0x3), and the bit clko must be set to ?1? in the mode register (mr), in order to generate correctly the serial clock on the clk pin. ? to obtain correct behavior of the receiver and the transmitter, the value programmed in cd of must be superior or equal to 4. ? if the internal clock divided (clk_usart/div) is selected, the value programmed in cd must be even to ensure a 50:50 mark/space ratio on the clk pin, this value can be odd if the internal clock is selected (clk_usart). in spi slave mode: ? the external clock (clk) selection is forced regardless of the value of the usclks field in the mode register (mr). likewise, the value written in brgr has no effect, because the clock is provided directly by the signal on the usart clk pin. ? to obtain correct behavior of the receiver and the transmitter, the external clock (clk) frequency must be at least 4 times lower than the system clock.
399 32099a?avr32?06/09 at32uc3l 20.7.6.3 data transfer up to 9 data bits are successively shifted out on the txd pin at each rising or falling edge (depending of cpol and cpha) of the programmed serial clock. there is no start bit, no parity bit and no stop bit. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (mr). the 9 bits are se lected by setting the mode 9 bit re gardless of the chrl field. the msb data bit is always sent first in spi mode (master or slave). four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the mode regi ster. the clock phase is programmed with the cpha bit. these two parameters determine the edges of the clock signal upon which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 20-10. spi bus protocol mode spi bus protocol mode cpol cpha 001 100 211 310
400 32099a?avr32?06/09 at32uc3l figure 20-25. spi transfer format (cpha=1, 8 bits per transfer) figure 20-26. spi transfer format (cpha=0, 8 bits per transfer) clk cycle (for reference) clk (cpol= 1) mosi spi master ->txd spi slave ->rxd miso spi master ->rxd spi slave ->txd nss spi master ->rts spi slave ->cts msb msb 1 clk (cpol= 0) 3 5 6 78 lsb 1 2 3 4 6 65 5 43 21 lsb 24 clk cycle (for reference) clk (cpol= 0) clk (cpol= 1) mosi spi master -> txd spi slave -> rxd miso spi master -> rxd spi slave -> txd nss spi master -> rts spi slave -> cts msb 6 5 msb 6 5 4 43 32 21 1 lsb lsb 8 7 6 5 4 3 2 1
401 32099a?avr32?06/09 at32uc3l 20.7.6.4 receiver and transmitter control see ?receiver and transmitter control? on page 382. 20.7.6.5 character transmission the characters are sent by writing in the tr ansmit holding register (thr). the transmitter reports two status bits in the channel status register (csr): txrdy (transmitter ready), which indicates that thr is empt y and txempty, which indicates that all the characters written in thr have been processed. when the current character processing is completed, the last character written in thr is transferred into the shift register of the transmitter and thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a character in thr while txrdy is low has no effect and the written character is lost. if the usart is in spi slave mode and if a character must be sent while the transmit holding register (thr) is empty, the unre (underrun error) bit is set. the txd transmission line stays at high level during all this time. the unre bit is cleared by writing the control register (cr) with the rststa (reset status) bit at 1. in spi master mode, the slave select line (nss) is asserted at low level 1 tbit before the trans- mission of the msb bit and released at high level 1 tbit after the transmission of the lsb bit. so, the slave select line (nss) is always released be tween each character transmission and a mini- mum delay of 3 tbits always inserted. however, in order to address slave devices supporting the csaat mode (chip select active after transfer), the slave select line (nss) can be forced at low level by writing the control register (cr) with the rtsen bit at 1. the slave select line (nss) can be released at high level only by wr iting the control register (cr) with the rtsdis bit at 1 (for example, when all data have been transferred to the slave device). in spi slave mode, the transmitter does not require a falling edge of the slave select line (nss) to initiate a character transmission but only a low level. however, this lo w level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 20.7.6.6 character reception when a character reception is completed, it is transferred to the receive holding register (rhr) and the rxrdy bit in the st atus register (csr) rises. if a character is completed while rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (cr) with the rststa (reset status) bit at 1. to ensure correct behavior of the receiver in spi slave mode, the master device sending the frame must ensure a minimum delay of 1 tb it between each character transmission. the receiver does not require a falling edge of the slave select line (nss) to initiate a character reception but only a low level. however, this low level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 20.7.6.7 receiver timeout because the receiver baudrate clock is active only during data transfers in spi mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field to) in the time-out register (rtor).
402 32099a?avr32?06/09 at32uc3l 20.7.7 lin mode the lin mode provides master node and slave node connectivity on a lin bus. the lin (local interconnect network) is a serial communication protocol which efficiently sup- ports the control of mechatronic nodes in distributed automotive applications. the main properties of the lin bus are: ? single master/multiple slaves concept ? low cost silicon implementation based on common uart/sci interface hardware, an equivalent in software, or as a pure state machine. ? self synchronization without quartz or ceramic resonator in the slave nodes ? deterministic signal transmission ? low cost single-wire implementation ? speed up to 20 kbit/s lin provides cost efficient bu s communication where the bandwid th and versatility of can are not required. the lin mode enables processing lin frames with a minimum of action from the microprocessor. 20.7.7.1 modes of operation the usart can act either as a lin master node or as a lin slave node. the node configuration is chosen by setting the mode field in the usart3 mode register (mr): ? lin master node (mode=0xa) ? lin slave node (mode=0xb) in order to avoid unpredicted behavior, any change of the lin node configuration must be fol- lowed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (see section 20.7.7.2 on page 402 ) 20.7.7.2 receiver and transmitter control see ?receiver and transmitter control? on page 382. 20.7.7.3 character transmission see ?transmitter operations? on page 382. 20.7.7.4 character reception see ?receiver operations? on page 385.
403 32099a?avr32?06/09 at32uc3l 20.7.7.5 header transmission (master node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. so in master node configuration, the frame handling starts with the sending of the header. the header is transmitted as soon as the identifier is written in the lin identifier register (linir). at this moment the flag txrdy falls. the break field, the synch field and the identif ier field are sent automatically one after the other. the break field consists of 13 dominant bits a nd 1 recessive bit, the synch field is the charac- ter 0x55 and the identifier corresponds to the character written in the lin identifier register (linir). the identifier parity bits can be automatically computed and sent (see section 20.7.7.8 on page 406 ). the flag txrdy rises when the identifier character is transferred into the shift register of the transmitter. figure 20-27. header transmission txd baud rate clock start bit write linir 10101010 txrdy stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 linir id
404 32099a?avr32?06/09 at32uc3l 20.7.7.6 header reception (slave node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. in slave node configuration, the frame handling starts with the reception of the header. the usart uses a break detection threshold of 11 nominal bit times at the actual baud rate. at any time, if 11 consecutive rece ssive bits are detected on the bus, the usart detects a break field. as long as a break field has not been detected, the usart stays idle and the received data are not taken in account. when a break field has been detected, the usar t expects the synch field character to be 0x55. this field is used to update the actual baud rate in order to stay synchronized (see section 20.7.7.7 on page 404 ). if the received synch character is not 0x55, an incons istent synch field error is generated (see section 20.7.8 on page 411 ). after receiving the synch field, the usart expects to receive the identifier field. when the identifier has been received, the flag linid is set to ?1?. at this moment the field idchr in the lin identifier register (linir) is updated with the re ceived character. the identifier parity bits can be automatically computed and checked (see section 20.7.7.8 on page 406 ). figure 20-28. header reception 20.7.7.7 slave node synchronization the synchronization is done only in slave node configuration. the procedure is based on time measurement between fallin g edges of the synch field. the falling edges are available in dis- tances of 2, 4, 6 and 8 bit times. figure 20-29. synch field the time measurement is made by a 19-bit counter clocked by the sampling clock (see section 20.7.1 on page 378 ). break field 13 dominant bits (at 0) break delimiter 1 recessive bit (at 1) start bit 10101010 stop bit start bit id0 id1 id2 id4 id3 id6 id5 id7 stop bit synch byte = 0x55 baud rate clock rxd write us_cr with rststa=1 us_linir linid start bit stop bit synch field 8 tbit 2 tbit 2 tbit 2 tbit 2 tbit
405 32099a?avr32?06/09 at32uc3l when the start bit of the synch field is detected the counter is reset. then during the next 8 tbits of the synch field, the counter is increm ented. at the end of these 8 tbits, the counter is stopped. at this moment, the 16 most significant bi ts of the counter (value divided by 8) gives the new clock divider (cd) and the 3 least significant bits of this value (the remainder) gives the new fractional part (fp). when the synch field has been re ceived, the clock divider (cd) and the fractional part (fp) are updated in the baud rate generator register (brgr). figure 20-30. slave node synchronization the accuracy of the synchronization depends on several parameters: ? the nominal clock frequency (f nom ) (the theoretical slave node clock frequency) ? the baudrate ? the oversampling (over=0 => 16x or over=0 => 8x) the following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (f slave is the real slave node clock frequency). f tol_unsynch is the deviation of the real slave node clock from the nominal clock frequency. the lin standard imposes that it must not exceed 15%. the lin standard imposes also that for communication between two nodes, their bit rate must not differ by more than 2%. this means that the baudrate_deviation must not exceed 1%. it follows from that, a minimum value for the nominal clock frequency: rxd baud rate clock linidrx synchro counter 000_0011_0001_0110_1101 brgr clcok divider (cd) 0000_0110_0010_1101 brgr fractional part (fp) 101 initial cd initial fp reset start bit 10101010 stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 baudrate_deviation 100 [ 82over ? () + ] baudrate 8f slave -------------------------------------------------------------------------------------------- - ?? ?? % = baudrate_deviation 100 [ 82over ? () + ] baudrate 8 f tol_unsynch 100 --------------------------------------- ?? ?? xf nom -------------------------------------------------------------------------------------------- - ?? ?? ?? ?? ?? % = 0.5 ? +0.5 -1 +1 << ?
406 32099a?avr32?06/09 at32uc3l examples: ? baudrate = 20 kbit/s, over=0 (oversampling 16x) => f nom (min) = 2.64 mhz ? baudrate = 20 kbit/s, over=1 (oversampling 8x) => f nom (min) = 1.47 mhz ? baudrate = 1 kbit/s, over=0 (oversampling 16x) => f nom (min) = 132 khz ? baudrate = 1 kbit/s, over=1 (oversampling 8x) => f nom (min) = 74 khz if the fractional baud rate is not used, the accuracy of the synchronization becomes much lower. when the counter is stopped, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (cd) . this value is rounded by adding th e first insignificant bit. the equation of the baudrate deviation is the same as given above, but the constants are as follows: it follows from that, a minimum value for the nominal clock frequency: examples: ? baudrate = 20 kbit/s, over=0 (oversampling 16x) => f nom (min) = 19.12 mhz ? baudrate = 20 kbit/s, over=1 (oversampling 8x) => f nom (min) = 9.71 mhz ? baudrate = 1 kbit/s, over=0 (oversampling 16x) => f nom (min) = 956 khz ? baudrate = 1 kbit/s, over=1 (oversampling 8x) => f nom (min) = 485 khz 20.7.7.8 identifier parity a protected identifier consists of two sub-fields; the identifier and the identifier parity. bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. the usart interface can generate/check these parity bits, but this feature can also be disabled. the user can choose between two modes by the pardis bit of the lin mode register (linmr): ? pardis = 0: during header transmission, the parity bits are computed and sent with the 6 least significant bits of the idchr field of the lin identifier register (linir). the bits 6 and 7 of this register are discarded. during header reception, the parity bits of the identifier are checked. if the parity bits are wrong, an identifier parity error occurs (see section 20.7.3.5 on page 386 ). only the 6 least significant bits of the idchr field are updated with the received identifier. the bits 6 and 7 are stuck at 0. ? pardis = 1: during header transmission, all th e bits of the idchr field of the lin identifier register (linir) are sent on the bus. during header reception, all the bits of the idchr field are updated with the received identifier. f nom min () 100 0.5 8 2 over ? () 1 + [] baudrate 8 15 ? 100 --------- - 1 + ?? ?? 1% ------------------------------------------------------------------------------------------------ ?? ?? ?? ?? ?? hz = 4 ? +4 -1 +1 << ? ? () 1 + [] baudrate 8 15 ? 100 --------- - 1 + ?? ?? 1% ------------------------------------------------------------------------------------------- ?? ?? ?? ?? ?? hz =
407 32099a?avr32?06/09 at32uc3l 20.7.7.9 node action in function of the identifier, the node is concerned, or not, by the lin response. consequently, after sending or receiving the identifier, the us art must be configured. there are three possi- ble configurations: ? publish: the node sends the response. ? subscribe: the node receives the response. ? ignore: the node is not concerned by the response, it does not send and does not receive the response. this configuration is made by the field, node action (nact), in the linmr register (see section 20.8.14 on page 441 ). example: a lin cluster that contains a master and two slaves: ? data transfer from the master to the slave 1 and to the slave 2: nact(master)=publish nact(slave1)=subscribe nact(slave2)=subscribe ? data transfer from the master to the slave 1 only: nact(master)=publish nact(slave1)=subscribe nact(slave2)=ignore ? data transfer from the slave 1 to the master: nact(master)=subscribe nact(slave1)=publish nact(slave2)=ignore ? data transfer from the slave1 to the slave2: nact(master)=ignore nact(slave1)=publish nact(slave2)=subscribe ? data transfer from the slave2 to the master and to the slave1: nact(master)=subscribe nact(slave1)=subscribe nact(slave2)=publish
408 32099a?avr32?06/09 at32uc3l 20.7.7.10 response data length the lin response data length is the number of data fields (bytes) of the response excluding the checksum. the response data length can either be configur ed by the user or be defined automatically by bits 4 and 5 of the identifier (compatibility to lin specification 1.1). the user can choose between these two modes by the dlm bit of the lin mode register (linmr): ? dlm = 0: the response data length is configured by the user via the dlc field of the lin mode register (linmr). the response data length is equal to (dlc + 1) bytes. dlc can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. ? dlm = 1: the response data length is defined by the identifier (idchr in linir) according to the table below. the dlc field of the lin mode register (linmr) is discarded. the response can contain 2 or 4 or 8 data bytes. figure 20-31. response data length table 20-11. response data length if dlm = 1 idchr[5] idchr[4] response data length [bytes] 00 2 01 2 10 4 11 8 user configuration: 1 - 256 data fields (dlc+1) identifier configuration: 2/4/8 data fields sync break sync field identifier field checksum field data field data field data field data field
409 32099a?avr32?06/09 at32uc3l 20.7.7.11 checksum the last field of a frame is the checksum. the checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. checksum calculation over the data bytes only is called classic checks um and it is used for communication with lin 1.3 slaves. checksum calculation over the data by tes and the protected identifier byte is called enhanced checksum and it is used for communication with lin 2.0 slaves. the usart can be configured to: ? send/check an enhanced checksum automatically (chkdis = 0 & chktyp = 0) ? send/check a classic checksum automatically (chkdis = 0 & chktyp = 1) ? not send/check a checksum (chkdis = 1) this configuration is made by the checksum type (chktyp) and ch ecksum disable (chkdis) fields of the lin mode register (linmr). if the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see section 20.7.7.10 on page 408 ).
410 32099a?avr32?06/09 at32uc3l 20.7.7.12 frame slot mode this mode is useful only for master nodes. it respects the following rule: each frame slot shall be longer than or equal to tframe_maximum. if the frame slot mode is enabled (fsdis = 0) and a frame transfer has been completed, the txrdy flag is set again only after tframe_maximum delay, from the start of frame. so the mas- ter node cannot send a new header if the frame slot duration of the previous frame is inferior to tframe_maximum. if the frame slot mode is disabled (fdis = 1) and a frame transfer has been completed, the txrdy flag is set again immediately. the tframe_maximum is calculated as below: if the checksum is sent (chkdis = 0): ? theader_nominal = 34 x tbit ? tresponse_nominal = 10 x (ndata + 1) x tbit ? tframe_maximum = 1.4 x (theader_nominal + tresponse_nominal + 1) (note:) ? tframe_maximum = 1.4 x (34 + 10 x (dlc + 1 + 1) + 1) x tbit ? tframe_maximum = (77 + 14 x dlc) x tbit if the checksum is not sent (chkdis = 1): ? theader_nominal = 34 x tbit ? tresponse_nominal = 10 x ndata x tbit ? tframe_maximum = 1.4 x (theader_nominal + tresponse_nominal + 1 (note:) ) ? tframe_maximum = 1.4 x (34 + 10 x (dlc + 1) + 1) x tbit ? tframe_maximum = (63 + 14 x dlc) x tbit note: the term ?+1? leads to an integer re sult for tframe_max (lin specification 1.3) figure 20-32. frame slot mode break synch protected identifier data n checksum header inter- frame space response space frame frame slot = tframe_maximum response txrdy write thr write linid data 1 data 2 data 3 data3 data n-1 data n frame slot mode disabled frame slot mode enabled lintc data 1
411 32099a?avr32?06/09 at32uc3l 20.7.8 lin errors 20.7.8.1 bit error this error is generated when the usart is transmitting and if the transmitted value on the tx line is different from the value sampled on the rx line. if a bit error is detected, the transmission is aborted at the next byte border. 20.7.8.2 inconsistent synch field error this error is generated in slave node configurati on if the synch field character received is other than 0x55. 20.7.8.3 parity error this error is generated if the parity of the identi fier is wrong. this error can be generated only if the parity feature is enabled (pardis = 0). 20.7.8.4 checksum error this error is set if th e received checksum is wrong. this error can be generated only if the checksum feature is enabled (chkdis = 0). 20.7.8.5 slave not responding error this error is set when the usart expects a response from another node (nact = sub- scribe) but no valid message appears on the bus within the time frame given by the maximum length of the message frame, tframe_maximum (see section 20.7.7.12 on page 410 ). this error is disabled if the usart does not expect any message (nact = publish or nact = ignore).
412 32099a?avr32?06/09 at32uc3l 20.7.9 lin frame handling 20.7.9.1 master node configuration ? write txen and rxen in cr to enable both the transmitter and the receiver. ? write mode in mr to select the lin mode and the master node configuration. ? write cd and fp in brgr to configure the baud rate. ? write nact, pardis, chkdis, chktype, dlcm, fdis and dlc in linmr to configure the frame transfer. ? check that txrdy in csr is set to ?1? ? write idchr in linir to send the header what comes next depends on the nact configuration: ? case 1: nact = publish, the usart sends the response ? wait until txrdy in csr rises ? write tchr in thr to send a byte ? if all the data have not been written, redo the two previous steps ? wait until lintc in csr rises ? check the lin errors ? case 2: nact = subscribe, the usart receives the response ? wait until rxrdy in csr rises ? read rchr in rhr ? if all the data have not been read, redo the two previous steps ? wait until lintc in csr rises ? check the lin errors ? case 3: nact = ignore, the usart is not concerned by the response ? wait until lintc in csr rises ? check the lin errors
413 32099a?avr32?06/09 at32uc3l figure 20-33. master node configuration, nact = publish figure 20-34. master node configur ation, nact=subscribe frame break synch protected identifier data 1 data n checksum txrdy write thr write linir data 1 data 2 data 3 data n-1 data n rxrdy header inter- frame space response space frame slot = tframe_maximum response data3 lintc fsdis=1 fsdis=0 break synch protected identifier data 1 data n checksum txrdy read rhr write linir data 1 data n-1 data n-1 rxrdy data n data n-2 header inter- frame space response space frame frame slot = tframe_maximum response data3 lintc fsdis=0 fsdis=1
414 32099a?avr32?06/09 at32uc3l figure 20-35. master node configuration, nact=ignore 20.7.9.2 slave node configuration ? write txen and rxen in cr to enable both the transmitter and the receiver. ? write mode in mr to select the lin mode and the slave node configuration. ? write cd and fp in brgr to configure the baud rate. ? wait until linid in csr rises ? check linisfe and linpe errors ? read idchr in rhr ? write nact, pardis, chkdis, chktype, dlcm and dlc in linmr to configure the frame transfer. important : if the nact configuration for this frame is publish, the us_linmr register, must be write with nact=publish even if this fiel d is already correctly configured, that in order to set the txready flag and the corresponding pdc write transfer request. what comes next depends on the nact configuration: ? case 1: nact = publish, the usart sends the response ? wait until txrdy in csr rises ? write tchr in thr to send a byte ? if all the data have not been written, redo the two previous steps ? wait until lintc in csr rises ? check the lin errors ? case 2: nact = subscribe, the usart receives the response ? wait until rxrdy in csr rises ? read rchr in rhr ? if all the data have not been read, redo the two previous steps ? wait until lintc in csr rises ? check the lin errors txrdy write linir rxrdy lintc break synch protected identifier data 1 data n checksum data n-1 header inter- frame space response space frame frame slot = tframe_maximum response data3 fsdis=1 fsdis=0
415 32099a?avr32?06/09 at32uc3l ? case 3: nact = ignore, the usart is not concerned by the response ? wait until lintc in csr rises ? check the lin errors figure 20-36. slave node configuration, nact = publish figure 20-37. slave node configuration, nact = subscribe figure 20-38. slave node configurat ion, nact = ignore break synch protected identifier data 1 data n checksum txrdy write thr read linid data 1 data 3 data n-1 data n rxrdy linidrx data 2 lintc txrdy read rhr read linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data 1 data n-1 data n-1 data n data n-2 txrdy read rhr read linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data n-1
416 32099a?avr32?06/09 at32uc3l 20.7.10 lin frame handling with the peripheral dma controller the usart can be used in association with the peripheral dma controller (pdca) in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. the pdca uses the trigger flags , txrdy and rxrdy, to write or read into the usart. the pdca always writes in the transmit holding re gister (thr) and it always reads in the receive holding register (rhr). the size of the data writ ten or read by the pdca in the usart is always a byte. 20.7.10.1 master node configuration the user can choose between two pdca modes by the pdcm bit in the lin mode register (linmr): ? pdcm = 1: the lin configuration is stored in the write buffer and it is written by the pdca in the transmit holding register thr (instead of the lin mode register linmr). because the pdca transfer size is limited to a byte, the transfer is split into two accesses. during the first access the bits, nact, pardis, chkdis, chktyp, dlm and fdis are written. during the second access the 8-bit dlc field is written. ? pdcm = 0: the lin configuration is not stored in the write buffer and it must be written by the user in the lin mode register (linmr). the write buffer also contains the identifier and the data, if the usart sends the response (nact = publish). the read buffer contains the data if the usart receives the response (nact = subscribe). figure 20-39. master node with pdca (pdcm=1) | | | | | | | | nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer pdca (dma) rxrdy usart3 lin controller peripheral bus nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer pdca (dma) rxrdy txrdy usart3 lin controller peripheral bus read buffer node action = publish node action = subscribe
417 32099a?avr32?06/09 at32uc3l figure 20-40. master node with pdca (pdcm=0) 20.7.10.2 slave node configuration in this configuration, the pdca transfers only the data. the identifier must be read by the user in the lin identifier register (linir). the lin mode must be written by the user in the lin mode register (linmr). the write buffer contains the data if the usart sends the response (nact=publish). the read buffer contains the data if the usart receives the response (nact=subscribe). important: if the nact configuration for a fr ame is publish, the us_linmr register, must be write with nact=publish even if this field is already correctly configured, that in order to set the txready flag and the corresponding pdc write transfer request. figure 20-41. slave node with pdca | | | | rxrdy txrdy peripheral bus usart3 lin controller data 0 data n | | | | write buffer pdca (dma) usart3 lin controller read buffer node action = publish node action = subscribe pdca (dma) rxrdy peripheral bus identifier data 0 data n write buffer identifier | | | | | | | | data 0 data n pdca (dma) rxrdy usart3 lin controller peripheral bus read buffer nact = subscribe data 0 data n pdca (dma) txrdy usart3 lin controller peripheral bus write buffer
418 32099a?avr32?06/09 at32uc3l 20.7.11 wake-up request any node in a sleeping lin cluster may request a wake-up. in the lin 2.0 specification, the wakeup reques t is issued by forcing the bus to the dominant state from 250 s to 5 ms. for this, it is necessa ry to send the character 0xf0 in order to impose 5 successive dominant bits. whatever the baud rate is, this character respects the specified timings. ? baud rate min = 1 kbit/s -> tbit = 1ms -> 5 tbits = 5 ms ? baud rate max = 20 kbit/s -> tbi t= 50 s -> 5 tbits = 250 s in the lin 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. the user can choose by the wkuptyp bit in the lin mode register (linmr) either to send a lin 2.0 wakeup request (wkuptyp=0) or to send a lin 1.3 wakeup request (wkuptyp=1). a wake-up request is transmitted by writing the c ontrol register (cr) with the linwkup bit at 1. once the transfer is completed, the lintc flag is asserted in the status register (sr). it is cleared by writing the control register (cr) with the rststa bit at 1.
419 32099a?avr32?06/09 at32uc3l 20.7.12 bus idle time-out if the lin bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. in the lin 2.0 specification, this time-out is fixed at 4 seconds. in the lin 1.3 specifica- tion, it is fixed at 25000 tbits. in slave node configuration, the receiver time -out detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (csr) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeou t bit in csr remains at 0. otherwise, the receiver loads a 17-bit counter with the value programmed in to. this counter is decremented at each bit period and reloaded ea ch time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. if sttto is performed, the counter clock is stopped until a first character is received. if retto is performed, the counter starts counting down immediately from the value to. table 20-12. receiver time-out programming lin specification baud rate time-out period to 2.0 1 000 bit/s 4s 4 000 2 400 bit/s 9 600 9 600 bit/s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 1.3 - 25 000 tbits 25 000
420 32099a?avr32?06/09 at32uc3l 20.7.13 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 20.7.13.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 20-42. normal mode configuration 20.7.13.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 20-43 on page 420 . programming the transmitter has no effect on the txd pin. the rxd pin is still conn ected to the receiver input, thus the receiver remains active. figure 20-43. automatic echo mode configuration 20.7.13.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 20-44 on page 420 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 20-44. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
421 32099a?avr32?06/09 at32uc3l 20.7.13.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 20-45 on page 421 . the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. figure 20-45. remote loopback mode configuration receiver transmitter rxd txd 1
422 32099a?avr32?06/09 at32uc3l 20.7.14 write protection registers to prevent any single software error that may corrupt usart behavior, certain address spaces can be write-protected by setting the wpen bit in the usart write protect mode register (wpmr). if a write access to the protected registers is detected, then the wpvs flag in the usart write protect status register (wpsr) is set and the field wpvsrc indicates in which regi ster the write access has been attempted. the wpvs flag is reset by writing the usart write protect mode register (wpmr) with the appropriate access key, wpkey. the protected registers are: ? ?mode register? on page 426 ? ?baud rate generator register? on page 436 ? ?receiver time-out register? on page 437 ? ?transmitter timeguard register? on page 438 ? ?fi di ratio register? on page 439 ? ?this register can only be written if the wpen bit is clea red in ?write protect mode register? on page 444.? on page 441
423 32099a?avr32?06/09 at32uc3l 20.8 user interface note: write is possible only in lin master node configuration. note: values in the version register vary with the version of the ip block implementation. table 20-13. usart register memory map offset register name access reset 0x0000 control register cr write-only ? 0x0004 mode register mr read-write 0x00000000 0x0008 interrupt enable register ier write-only ? 0x000c interrupt disable register idr write-only ? 0x0010 interrupt mask register imr read-only 0x00000000 0x0014 channel status register csr read-only 0x00000000 0x0018 receiver holding register rhr read-only 0x00000000 0x001c transmitter holding register thr write-only ? 0x0020 baud rate generator register brgr read-write 0x00000000 0x0024 receiver time-out register rtor read-write 0x00000000 0x0028 transmitter timeguard register ttgr read-write 0x00000000 0x0040 fi di ratio register fidi read-write 0x00000174 0x0044 number of errors re gister ner read-only 0x00000000 0x0054 lin mode register linmr read-write 0x00000000 0x0058 lin identifier register linir read-write (note:) 0x00000000 0xe4 write protect mode register wpmr read-write 0x00000000 0xe8 write protect status register wpsr read-only 0x00000000 0xfc version register version read-only 0x? (note:)
424 32099a?avr32?06/09 at32uc3l 20.8.1 control register name: cr access type: write-only offset: 0x0 reset value: - ? linwkup: send lin wakeup signal 0: no effect: 1: sends a wakeup signal on the lin bus. ? linabt: abort lin transmission 0: no effect. 1: abort the current lin transmission. ? rtsdis/rcs: request to send disable/release spi chip select if usart does not operate in spi master mode (mode 0xe): 0: no effect. 1: drives the pin rts to 1. if usart operates in spi master mode (mode = 0xe): rcs = 0: no effect. rcs = 1: releases the slave select line nss (rts pin). ? rtsen/fcs: request to send enable/force spi chip select if usart does not operate in spi master mode (mode 0xe): 0: no effect. 1: drives the pin rts to 0. if usart operates in spi master mode (mode = 0xe): fcs = 0: no effect. fcs = 1: forces the slave select line nss (rts pin) to 0, ev en if usart is no transmitting, in order to address spi slave devices supporting the csaat mode (chip select active after transfer). ? retto: rearm time-out 0: no effect 1: restart time-out ? rstnack: reset non acknowledge 0: no effect 1: resets nack in csr. ? rstit: reset iterations 0: no effect. 1: resets iteration in csr. no ef fect if the iso7816 is not enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? linwkup linabt rtsdis/rcs rtsen/fcs ? ? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
425 32099a?avr32?06/09 at32uc3l ? senda: send address 0: no effect. 1: in multidrop mode only, the next character writ ten to the thr is sent with the address bit set. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the ti me-out counter. resets the status bit timeout in csr. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one characte r length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in thr and the tr ansmit shift register have been transmitted. no effect if a break is already being transmitted. ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, lin be, linsfe, linipe, lince, linsnre and rxbrk in csr. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rstrx: reset receiver 0: no effect. 1: resets the receiver.
426 32099a?avr32?06/09 at32uc3l 20.8.2 mode register name: mr access type: read-write offset: 0x4 reset value: - this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sa mple filter (1/16-bit clock) (2 over 3 majority). ? max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value specifi ed in the max_iteration field. these parity errors generate a nack on the iso line. as soon as this value is reached, no addi tional nack is sent on the iso line. the flag iteration is asserted. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? clko: clock output select 0: the usart does not drive the clk pin. 1: the usart drives the clk pin if usclks does not select the external clock clk. ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? msbf/cpol: bit order or spi clock polarity if usart does not operate in spi mode (mode 0xe and 0xf): msbf = 0: least significant bit is sent/received first. msbf = 1: most significant bit is sent/received first. if usart operates in spi mode (slave or master, mode = 0xe or 0xf): cpol = 0: the inactive state value of spck is logic level zero. 31 30 29 28 27 26 25 24 ??? filter ? max_iteration 23 22 21 20 19 18 17 16 ? ? dsnack inack over clko mode9 msbf/cpol 15 14 13 12 11 10 9 8 chmode nbstop par sync/cpha 76543210 chrl usclks mode
427 32099a?avr32?06/09 at32uc3l cpol = 1: the inactive state va lue of spck is logic level one. cpol is used to determine the inactive state value of the seri al clock (spck). it is used with cpha to produce the required clock/data relationship between master and slave devices. ? chmode: channel mode ? nbstop: number of stop bits ? par: parity type ? sync/cpha: synchronous mode select or spi clock phase if usart does not operate in spi mode (mode is 0xe and 0xf): sync = 0: usart operates in asynchronous mode. sync = 1: usart operates in synchronous mode. if usart operates in spi mode (mode = 0xe or 0xf): cpha = 0: data is changed on the leading edge of spck and captured on the following edge of spck. cpha = 1: data is captured on the leading edge of spck and changed on the following edge of spck. cpha determines which edge of spck causes data to change an d which edge causes data to be captured. cpha is used with cpol to produce the required clock/data rela tionship between master and slave devices. table 20-14. chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input. 1 1 remote loopback. rxd pin is internally connected to the txd pin. table 20-15. nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved table 20-16. par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode
428 32099a?avr32?06/09 at32uc3l ? chrl: character length. ? usclks: clock selection ? mode 20.8.3 interrupt enable register name: ier access type: write-only offset: 0x8 reset value: - table 20-17. chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits table 20-18. usclks selected clock 0 0 clk_usart 0 1 clk_usart/div (div = 8) 10reserved 11 clk table 20-19. mode mode of the usart 0000normal 0001rs485 0 0 1 0 hardware handshaking 0 1 0 0 is07816 protocol: t = 0 0 1 1 0 is07816 protocol: t = 1 1 0 1 0 lin master 1011lin slave 1110spi master 1 1 1 1 spi slave others reserved 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ?
429 32099a?avr32?06/09 at32uc3l writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 23 22 21 20 19 18 17 16 ??? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 lintc linid nack/linbk rxbuff ? iter/unre txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
430 32099a?avr32?06/09 at32uc3l 20.8.4 interrupt disable register name: idr access type: write-only offset: 0xc reset value: - writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 ??? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 lintc linid nack/linbk rxbuff ? iter/unre txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
431 32099a?avr32?06/09 at32uc3l 20.8.5 interrupt mask register name: imr access type: read-only offset: 0x10 reset value: - 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is cleared when the corresponding bit in ier is written to one. 20.8.6 channel status register name: csr access type: read-only offset: 0x14 reset value: - ? linsnre: lin slave not responding error 0: no lin slave not responding error has been detected since the last rststa. 1: a lin slave not responding error has been detected since the last rststa. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 ??? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 lintc linid nack/linbk rxbuff ? iter/unre txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 lintc linid nack/linbk rxbuff ? iter/unre txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
432 32099a?avr32?06/09 at32uc3l ? lince: lin checksum error 0: no lin checksum error has been detected since the last rststa. 1: a lin checksum error has been detected since the last rststa. ? linipe: lin identifi er parity error 0: no lin identifier parity error has been detected since the last rststa. 1: a lin identifier parity error has been detected since the last rststa. ? linisfe: lin inconsistent synch field error 0: no lin inconsistent synch field erro r has been detected since the last rststa 1: the usart is configured as a slave node and a lin incons istent synch field error has been detected since the last rststa. ? linbe: lin bit error 0: no bit error has been detected since the last rststa. 1: a bit error has been detected since the last rststa. ? cts: image of cts input 0: cts is at 0. 1: cts is at 1. ? ctsic: clear to send input change flag 0: no input change has been detected on th e cts pin since the last read of csr. 1: at least one input change has been detect ed on the cts pin since the last read of csr. ? lintc: lin transfer completed 0: the usart is idle or a lin transfer is ongoing. 1: a lin transfer has been comp leted since the last rststa. ? linir: lin iden tifier received 0: no lin identifier received 1: the usart is configured as a slave node and a lin i dentifier has been received since the last rststa. ? nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? rxbuff: reception buffer full 0: the signal buffer full from the receive pdca channel is inactive. 1: the signal buffer full from the receive pdca channel is active. ? iter/unre: max number of repetitions reached or spi underrun error if usart does not operate in spi slave mode (mode 0xf): iter = 0: maximum number of repetitions has not been reached since the last rststa. iter = 1: maximum number of repetitions has been reached since the last rststa. if usart operates in spi slave mode (mode = 0xf): unre = 0: no spi underrun error has occurred since the last rststa. unre = 1: at least one spi underrun error has occurred since the last rststa. ? txempty: transmitter empty 0: there are characters in either thr or the tran smit shift register, or the transmitter is disabled. 1: there are no characters in thr, nor in the transmit shift register. ? timeout: receiver time-out 0: there has not been a time-out since the last start time-o ut command (sttto in cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in cr). ? pare: parity error 0: no parity error has been det ected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been det ected low since the last rststa.
433 32099a?avr32?06/09 at32uc3l ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of brea k detected since the last rststa. ? txrdy: transmitter ready 0: a character is in the thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as so on as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the thr. ? rxrdy: receiver ready 0: no complete character has been received since the last read of rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete character has been received and rhr has not yet been read.
434 32099a?avr32?06/09 at32uc3l 20.8.7 receive holding register name: rhr access type: read-only offset: 0x18 reset value: 0x00000000 ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. ? rxchr: received character last character received if rxrdy is set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr
435 32099a?avr32?06/09 at32uc3l 20.8.8 usart transmit holding register name: thr access type: write-only offset: 0x1c reset value: - ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a co mmand. start frame deli miter is command sync. ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr
436 32099a?avr32?06/09 at32uc3l 20.8.9 baud rate generator register name: brgr access type: read-write offset: 0x20 reset value: 0x00000000 this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. ? cd: clock divider 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp ? 15 14 13 12 11 10 9 8 cd 76543210 cd table 20-20. cd mode iso7816 mode = iso7816 sync = 0 sync = 1 or mode = spi (master or slave) over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
437 32099a?avr32?06/09 at32uc3l 20.8.10 receiver time-out register name: rtor access type: read-write offset: 0x24 reset value: 0x00000000 this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . ? to: time-out value 0: the receiver time-out is disabled. 1 - 131071: the receiver time-out is enabled and the time-out delay is to x bit period. note that the size of the to counter can change depending of implementation. see the mo dule configuration section. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????to 15 14 13 12 11 10 9 8 to 76543210 to
438 32099a?avr32?06/09 at32uc3l 20.8.11 transmitter timeguard register name: ttgr access type: read-write offset: 0x28 reset value: 0x00000000 this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
439 32099a?avr32?06/09 at32uc3l 20.8.12 fi di ratio register name: fidi access type: read-write offset: 0x40 reset value: 0x00000174 this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on clk divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
440 32099a?avr32?06/09 at32uc3l 20.8.13 number of errors register name: ner access type: read-only offset: 0x44 reset value: - ? nb_errors: number of errors total number of errors that occurred during an iso7816 tr ansfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
441 32099a?avr32?06/09 at32uc3l this register can only be written if the wpen bit is cleared in ?write protect mode register? on page 444 . 20.8.14 lin mode register name: linmr access type: read-write offset: 0x54 reset value: 0x00000000 ? pdcm: pdca mode 0: the lin mode register linm r is not written by the pdca. 1: the lin mode register linmr (excepti ng that flag) is written by the pdca. ? dlc: data length control 0 - 255: defines the response data length if dlm=0,in th at case the response data length is equal to dlc+1 bytes. ? wkuptyp: wakeup signal type 0: setting the bit linwkup in the contro l register sends a lin 2.0 wakeup signal. 1: setting the bit linwkup in the contro l register sends a lin 1.3 wakeup signal. ? fdis: frame slot mode disable 0: the frame slot mode is enabled. 1: the frame slot mode is disabled. ? dlm: data length mode 0: the response data length is defined by the field dlc of this register. 1: the response data length is defined by the bi ts 5 and 6 of the ident ifier (idchr in linir). ? chktyp: checksum type 0: lin 2.0 ?enhanced? checksum 1: lin 1.3 ?classic? checksum ? chkdis: checksum disable 0: in master node configuration, the checksum is computed and sent automatically. in slave node configuration, the checksum is checked automatically. 1: whatever the node configuration is, the checks um is not computed/sent and it is not checked. ? pardis: parity disable 0: in master node configuration, the identifier parity is computed and sent automatically. in master node and slave node configuration, the parity is checked automatically. 1:whatever the node configuration is , the identifier parity is not com puted/sent and it is not checked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????pdcm 15 14 13 12 11 10 9 8 dlc 76543210 wkuptyp fsdis dlm chktyp chkdis pardis nact
442 32099a?avr32?06/09 at32uc3l ? nact: lin node action table 1. nact mode description 0 0 publish: the usart transmits the response. 0 1 subscribe: the usart receives the response. 1 0 ignore: the usart does not transmit and does not receive the response. 11reserved
443 32099a?avr32?06/09 at32uc3l 20.8.15 lin identifier register name: linir access type: read-write or read-only offset: 0x58 reset value: 0x00000000 ? idchr: identifier character if mode=0xa (master node configuration): idchr is read-write and its value is the identifier character to be transmitted. if mode=0xb (slave node configuration): idchr is read-only and its value is the last identifier character that has been received. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 idchr
444 32099a?avr32?06/09 at32uc3l 20.8.16 write protect mode register register name: wpmr access type: read-write offset: 0xe4 reset value: see table 20-13 on page 423 ? wpkey: write protect key should be written at value 0x858365 ("usa" in ascii). writing an y other value in this field aborts the write operation of the wpen bit. always reads as 0. ? wpen: write protect enable 0 = disables the write protect if wpkey corre sponds to 0x858365 ("usa" in ascii). 1 = enables the write protect if wpkey corr esponds to 0x858365 ("usa" in ascii). protects the registers: ? ?mode register? on page 426 ? ?baud rate generator register? on page 436 ? ?receiver time-out register? on page 437 ? ?transmitter timeguard register? on page 438 ? ?fi di ratio register? on page 439 ? ?this register can only be written if the wpen bit is clea red in ?write protect mode register? on page 444.? on page 441 ? ?manchester configuration register? on page 91 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????wpen
445 32099a?avr32?06/09 at32uc3l 20.8.17 write protect status register register name: wpsr access type: read-only offset: 0xe8 reset value: see table 20-13 on page 423 ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write- protected register (through address offs et or code) in which a write access has been attempted. ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the wpsr register. 1 = a write protect violation has occurred si nce the last read of the wpsr register. if this violation is an unauthorized attem pt to write a protected register, the associated violation is reported into field wpvsrc. note: reading wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????wpvs
446 32099a?avr32?06/09 at32uc3l 20.8.18 version register name: version access type: read-only offset: 0xfc reset value: - ? variant reserved. no functionality associated. ? version version of the module. no functionality associated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? variant 15 14 13 12 11 10 9 8 ???? version 76543210 version
447 32099a?avr32?06/09 at32uc3l 20.9 module configuration the specific configuration for each usart instance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. 20.9.1 clock connections each usart can be connected to an internally divided clock: 20.9.2 register reset values table 20-21. module configuration feature usart0 usart1 usart2 usart3 spi logic implemented implemented implemented implemented lin logic implemented implemented implemented implemented manchester logic not implemented not im plemented not implemented not implemented modem logic not implemented not implem ented not implemented not implemented irda logic not implemented not implemented not implemented not implemented fractional baudrate implemented implemented implemented implemented iso7816 not implemented not implement ed not implemented not implemented table 20-22. module clock name module name clock name usart0 clk_usart0 usart1 clk_usart1 usart2 clk_usart2 usart3 clk_usart3 table 20-23. usart clock connections usart source name connection 0 internal clk_div pba clock / 8 1 2 3 table 20-24. register reset value version 0x00000440
448 32099a?avr32?06/09 at32uc3l 21. serial peripheral interface (spi) rev. 2.1.1.1 21.1 features ? compatible with an embedded 32-bit microcontroller ? supports communication with serial external devices ? four chip selects with extern al decoder support allow co mmunication with up to 15 peripherals ? serial memories, such as da taflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, l cd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 4 - to 16-bit programmable da ta length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? connection to peripheral dma controller ch annel capabilities opti mizes data transfers ? one channel for the receiver, one channel for the transmitter ? next buffer support ? four character fifo in reception 21.2 overview the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this contro l line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware.
449 32099a?avr32?06/09 at32uc3l 21.3 block diagram figure 21-1. spi block diagram 21.4 application block diagram figure 21-2. application block diagram: single master/multiple slave implementation spi interface interrupt control peripheral dma controller i/o controller clk_spi peripheral bus spi interrupt spck npcs3 npcs2 npcs1 npcs0/nss mosi miso slave 0 slave 2 slave 1 spck npcs3 npcs2 npcs1 npcs0 mosi miso spi master spck nss mosi miso spck nss mosi miso spck nss mosi miso nc
450 32099a?avr32?06/09 at32uc3l 21.5 i/o lines description 21.6 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 21.6.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with i/o lines. the user must first configure the i/o controll er to assign the spi pins to their peripheral functions. 21.6.2 clocks the clock for the spi bus interface (clk_spi) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the spi before disabling the clock, to avoid freezing the spi in an undefined state. 21.6.3 interrupts the spi interrupt request line is connected to the interrupt controller. using the spi interrupt requires the interrupt controller to be programmed first. 21.7 functional description 21.7.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is configured by writing a one to the master/slave mode bit in the mode register (mr.mstr). the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the rece iver input and the mosi line driven as an output by the transmitter. if the mr.mstr bit is written to zero, the spi ope rates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the receiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. table 21-1. i/o lines description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
451 32099a?avr32?06/09 at32uc3l 21.7.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is configured with the clock polarity bit in the chip select registers (csrn.cpol). the clock phase is configured with the clock phase bit in the csrn registers (csrn.ncpha). these two bits determine the edges of the clock signal on which data is driven and sampled. each of the two bits has two possible states, resulting in four possible combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to com- municate. if multiple slaves are used and fix ed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. table 21-2 on page 451 shows the four modes and corresponding parameter settings. figure 21-3 on page 451 and figure 21-4 on page 452 show examples of data transfers. figure 21-3. spi transfer format (ncpha = 1, 8 bits per transfer) table 21-2. spi modes spi mode cpol ncpha 001 100 211 310 14 3 2 58 7 6 spck cycle (for reference) spck (cpol = 0) nss (to slave) miso (from slave) mosi (from master) spck (cpol = 1) msb 6 4 5lsb 1 2 3 msb 6 *** lsb 1 2 3 4 5 *** not defined, but normaly msb of previous character received
452 32099a?avr32?06/09 at32uc3l figure 21-4. spi transfer format (ncpha = 0, 8 bits per transfer) 21.7.3 master mode operations when configured in master mode, the spi uses the internal programmable baud rate generator as clock source. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the tr ansmit data register (tdr) and the receive data register (rdr), and a single shi ft register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the tdr register. the written data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing to the tdr, the peripheral chip select field in tdr (tdr.pcs) must be written in order to select a slave. if new data is written to tdr during the transfer, it stays in it until the current transfer is com- pleted. then, the received data is transferred from the shift register to rdr, the data in tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in tdr in the shift register is indicated by the transmit data reg- ister empty bit in the status register (sr.tdre). when new data is written in tdr, this bit is cleared. the sr.tdre bit is used to trigger the transmit peripheral dma controller channel. the end of transfer is indicated by the transmission registers empty bit in the sr register (sr.txempty). if a transfer delay (csrn.dlybct) is greater than zero for the last transfer, sr.txempty is set after the completion of said delay. the clk_spi can be switched off at this time. during reception, received data are transferred from the shift register to the reception fifo. the fifo can contain up to 4 characters (both receive data and peripheral chip select fields). while a character of the fifo is unread, the receive data register full bit in sr remains high (sr.rdrf). characters are read through the rdr re gister. if the four char acters stored in the fifo are not read and if a new character is stored, this sets the overrun error status bit in the sr register (sr.ovres). the procedure to follow in such a case is described in section 21.7.3.8 . 14 3 2 58 7 6 spck cycle (for reference) spck (cpol = 0) nss (to slave) miso (from slave) mosi (from master) spck (cpol = 1) msb 6 4 5lsb 1 2 3 6 lsb 1 2 3 4 5 *** not defined, but normaly lsb of previous character transmitted msb ***
453 32099a?avr32?06/09 at32uc3l in master mode, if the received data is not read fast enough compared to the transfer rhythm imposed by the write accesses in the tdr, some overrun errors may occur, even if the fifo is enabled. to insure a perfect data integrity of received data (especially at high data rate), the mode wait data read before transfer can be enabled in the mr register (mr.wdrbt). when this mode is activated, no transfer starts while received data remains unread in the rdr. when data is written to the tdr and if unread received data is stored in the rdr, the transfer is paused until the rdr is read. in this mode no ov errun error can occur. please note that if this mode is enabled, it is useless to activate the fifo in reception. figure 21-5 on page 453 shows a block diagram of the spi when operating in master mode. fig- ure 21-6 on page 454 shows a flow chart describing how transfers are handled. 21.7.3.1 master mode block diagram figure 21-5. master mode block diagram baud rate generator rxfifoen 4 ? character fifo shift register tdre rxfifoen 4 ? character fifo ps pcsdec current peripheral modf modfdis mstr scbr csr0..3 csr0..3 cpol ncpha bits rdr rd rdrf ovres td tdr pcs rdr csaat csnaat csr0..3 pcs mr pcs tdr spck clk_spi miso mosi msb lsb npcs1 npcs2 npcs3 npcs0 spi clock 0 1 0 1 0 1 npcs0
454 32099a?avr32?06/09 at32uc3l 21.7.3.2 master mode flow diagram figure 21-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = tdr(pcs) npcs = mr(pcs) delay dlybs serializer = tdr(td) tdre = 1 data transfer rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 tdr(pcs) = npcs ? no yes mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = tdr(pcs) npcs = 0xf delay dlybcs npcs = mr(pcs), tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
455 32099a?avr32?06/09 at32uc3l 21.7.3.3 clock generation the spi baud rate clock is generated by dividing the clk_spi , by a value between 1 and 255. this allows a maximum operating baud rate at up to clk_spi and a minimum operating baud rate of clk_spi divided by 255. writing the serial clock baud rate field in the csrn registers (csrn.scbr) to zero is forbid- den. triggering a transfer while csrn.scbr is zero can lead to unpredictable results. at reset, csrn.scbr is zero and the user has to configure it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be configured in the csrn.scbr field. this allows the spi to au tomatically adapt the baud rate for each interfaced peripheral without reprogramming. 21.7.3.4 transfer delays figure 21-7 on page 455 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be configured to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the chip selects by writing to the delay between chip selects field in the mr register (mr. dlybcs). allows insertion of a delay between release of one chip select and before assertion of a new one. ? the delay before spck, independently programmable for each chip select by writing the delay before spck field in the csrn register s (csrn.dlybs). allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the delay between consecutive transfers field in the csrn registers (csrn.dlybct). allows insertion of a delay be tween two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 21-7. programmable delays dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
456 32099a?avr32?06/09 at32uc3l 21.7.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: ? fixed peripheral select: spi exchanges data with only one peripheral ? variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing a ze ro to the peripheral select bit in mr (mr.ps). in this case, the current peripheral is defined by the mr.pcs field and the tdr.pcs field has no effect. variable peripheral select is activated by writing a one to the mr.ps bit . the tdr.pcs field is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the periph- eral dma controller is an optimal means, as the size of the data transfer between the memory and the spi is either 4 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mr register. data written to tdr is 32-bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the peripheral dma controller in this mode requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, however the spi still controls the number of bits (8 to16) to be transferr ed through miso and mosi lines with the csrn registers. this is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 21.7.3.6 peripheral chip select decoding the user can configure the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external logic. this can be enabled by writing a one to the chip select decode bit in the mr register (mr.pcsdec). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mr register or the tdr register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at one) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, the crs0 register defines the characteristics of the exter nally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 21.7.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in tdr is completed, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding
457 32099a?avr32?06/09 at32uc3l to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select li ne to remain active during a full set of transfers. to facilitate interfacing with such devices, the csrn registers can be configur ed with the chip select active after transfer bit written to one (csrn.csaat) . this allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. when the csrn.csaat bit is written to qero, the npcs does not rise in all cases between two transfers on the same peripheral. during a transfe r on a chip select, the sr.tdre bit rises as soon as the content of the tdr is transferred into the internal shifter. when this bit is detected the tdr can be reloaded. if this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. this migh t lead to difficulties fo r interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. to facilitate interfacing with such devices, the csrn register s can be configured with the chip select not active after transfer bit (csrn.csnaat) written to one. this allows to de-assert systematically the chip select lines during a time dlybcs. (the value of th e csrn.csnaat bit is taken into account only if the csrn.csaat bit is written to zero for the same chip select). figure 21-8 on page 458 shows different peripheral deselection cases and the effect of the csrn.csaat and csrn.csnaat bits. 21.7.3.8 fifo management a fifo has been implemented in reception fifo (both in master and in slave mode), in order to be able to store up to 4 characters without causing an overrun error. if an attempt is made to store a fifth character, an overrun error rises. if such an event occurs, the fifo must be flushed. there are two ways to flush the fifo: ? by performing four read accesses of the rdr (the data read must be ignored) ? by writing a one to the flush fifo command bit in the cr register (cr.flushfifo). after that, the spi is able to receive new data.
458 32099a?avr32?06/09 at32uc3l figure 21-8. peripheral deselection figure 21-8 on page 458 shows different peripheral deselection cases and the effect of the csrn.csaat and csrn.csnaat bits. 21.7.3.9 mode fault detection a mode fault is detected when the spi is configur ed in master mode and a low level is driven by an external master on the npcs0/nss signal. npcs0, mosi, miso and spck must be config- ured in open drain through the i/o controller, so that external pull up resistors are needed to guarantee high level. a npcs[0..3] write tdr tdre npcs[0..3] write tdr tdre npcs[0..3] write tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 and csnaat = 0 dlybct aa csaat = 1 and csnaat= 0 / 1 a dlybcs pcs = a dlybct aa csaat = 0 and csnaat = 1 npcs[0..3] write tdr tdre pcs = a dlybct aa csaat = 0 and csnaat = 0
459 32099a?avr32?06/09 at32uc3l when a mode fault is detected, the mode fault error bit in the sr (sr.modf) is set until the sr is read and the spi is automatically disabled until re-enabled by writing a one to the spi enable bit in the cr register (cr.spien). by default, the mode fault detection circuitry is enabled. the user can disable mode fault detec- tion by writing a one to the mode fault dete ction bit in the mr re gister (mr.modfdis). 21.7.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits per transfer field of the chip select register 0 (csr0.bits). these bits are processed following a phase and a polarity defined respectively by the csr0.ncpha and csr0.cpol bits. note that the bits, cpol, and ncp ha bits of the other chip select registers have no effect when the spi is configured in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. when all the bits are processed, the received data is transferred in the receive data register and the sr.rdrf bit rises. if the rdr register has not been read before new data is received, the sr.ovres bit is set. as long as this bit is set, data is loaded in rdr. the user has to read the sr register to clear the sr.ovres bit. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the tdr register, the last data received is transferred. if no data has been received since the last reset, all bits are transmi tted low, as the shift register resets to zero. when a first data is written in tdr, it is trans ferred immediately in the shift register and the sr.tdre bit rises. if new data is written, it rema ins in tdr until a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. w hen the transfer occurs, the last data written in tdr is transferred in the shift register and the sr.tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the tdr. in case no character is ready to be transmitted, i.e. no character has been written in tdr since the last load from tdr to the shift register, the shift register is not modified and the last received character is retransmitted. in this case the underrun error status bit is set in sr (sr.undes). figure 21-9 on page 460 shows a block diagram of the spi when operating in slave mode.
460 32099a?avr32?06/09 at32uc3l figure 21-9. slave mode functional block diagram shift register spck spiens lsb msb nss mosi spi clock tdre tdr td rdrf ovres csr0 cpol ncpha bits spien spidis miso undes rdr rd 4 - character fifo 0 1 rxfifoen
461 32099a?avr32?06/09 at32uc3l 21.8 user interface note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. table 21-3. spi register memory map offset register register name access reset 0x00 control register cr write-only 0x00000000 0x04 mode register mr read/write 0x00000000 0x08 receive data register rdr read-only 0x00000000 0x0c transmit data register tdr write-only 0x00000000 0x10 status register sr read-only 0x000000f0 0x14 interrupt enable register ier write-only 0x00000000 0x18 interrupt disable register idr write-only 0x00000000 0x1c interrupt mask register imr read-only 0x00000000 0x30 chip select register 0 csr0 read/write 0x00000000 0x34 chip select register 1 csr1 read/write 0x00000000 0x38 chip select register 2 csr2 read/write 0x00000000 0x3c chip select register 3 csr3 read/write 0x00000000 0x e4 write protection control register wpcr read/write 0x00000000 0xe8 write protection status register wpsr read-only 0x00000000 0xfc version register version read-only - (1)
462 32099a?avr32?06/09 at32uc3l 21.8.1 control register name: cr access type: write-only offset: 0x00 reset value: 0x00000000 ? lastxfer: last transfer 1: the current npcs will be deasserted after the character wr itten in td has been transferred. when csrn.csaat is one, this allows to close the communication with the current serial peri pheral by raising the corresponding npcs line as soon as td transfer has completed. 0: writing a zero to this bit has no effect. ? flushfifo: flush fifo command 1: if the fifo mode is enabled (mr.fifoen written to one) and if an overrun error has been detected, this command allows to empty the fifo. 0: writing a zero to this bit has no effect. ? swrst: spi software reset 1: writing a one to this bit will reset the spi. a software-trigger ed hardware reset of the spi interface is performed. the spi is in slave mode after software reset. peripheral dma controller channels are not affected by software reset. 0: writing a zero to this bit has no effect. ? spidis: spi disable 1: writing a one to this bit will disable the spi. as soon as spi dis is written to one, the spi finishes its transfer, all pins are set in input mode and no data is received or transmitted. if a transfe r is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the cr register is written, the spi is disabled. 0: writing a zero to this bit has no effect. ? spien: spi enable 1: writing a one to this bit will enable the spi to transfer and receive data. 0: writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------lastxfer 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------flushfifo 76543210 swrst - - - - - spidis spien
463 32099a?avr32?06/09 at32uc3l 21.8.2 mode register name: mr access type: read/write offset: 0x04 reset value: 0x00000000 ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the activation of another npcs. the dlybcs time guarantees non- overlapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six clk_spi periods will be inserted by default. otherwise, the following equation determines the delay: ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0npcs[3:0] = 1110 pcs = xx01npcs[3:0] = 1101 pcs = x011npcs[3:0] = 1011 pcs = 0111npcs[3:0] = 0111 pcs = 1111forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? llb: local loopback enable 1: local loopback path enabled. llb controls the local loopback on the data serializer for testing in master mode only (miso is internally connected on mosi). 0: local loopback path disabled. ? rxfifoen: fifo in reception enable 1: the fifo is used in reception (f our characters can be stored in the spi). 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ---- pcs 15 14 13 12 11 10 9 8 -------- 76543210 llb rxfifoen wdrbt modfdis - pcsdec ps mstr delay between chip selects dlybcs clkspi ---------------------- - =
464 32099a?avr32?06/09 at32uc3l 0: the fifo is not used in reception (onl y one character can be stored in the spi). ? wdrbt: wait data read before transfer 1: in master mode, a transfer can start only if the rdr regist er is empty, i.e. does not contain any unread data. this mode prevents overrun error in reception. 0: no effect. in master mode, a transfer can be in itiated whatever the state of the rdr register is. ? modfdis: mode fault detection 1: mode fault detection is disabled. 0: mode fault detection is enabled. ? pcsdec: chip select decode 0: the chip selects are directly connected to a peripheral device. 1: the four chip select lines are co nnected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the csrn registers define the characteristics of the 15 chip selects according to the following rules: csr0 defines peripheral chip select signals 0 to 3. csr1 defines peripheral chip select signals 4 to 7. csr2 defines peripheral chip select signals 8 to 11. csr3 defines peripheral chip select signals 12 to 14. ? ps: peripheral select 1: variable peripheral select. 0: fixed peripheral select. ? mstr: master/slave mode 1: spi is in master mode. 0: spi is in slave mode.
465 32099a?avr32?06/09 at32uc3l 21.8.3 receive data register name: rdr access type: read-only offset: 0x08 reset value: 0x00000000 ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- pcs 15 14 13 12 11 10 9 8 rd[15:8] 76543210 rd[7:0]
466 32099a?avr32?06/09 at32uc3l 21.8.4 transmit data register name: tdr access type: write-only offset: 0x0c reset value: 0x00000000 ? lastxfer: last transfer 1: the current npcs will be deasserted after the character wr itten in td has been transferred. when csrn.csaat is one, this allows to close the communication with the current serial peri pheral by raising the corresponding npcs line as soon as td transfer has completed. 0: writing a zero to this bit has no effect. this field is only used if variable peripheral select is active (mr.ps = 1). ? pcs: peripheral chip select if pcsdec = 0: pcs = xxx0npcs[3:0] = 1110 pcs = xx01npcs[3:0] = 1101 pcs = x011npcs[3:0] = 1011 pcs = 0111npcs[3:0] = 0111 pcs = 1111forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs this field is only used if variable peripheral select is active (mr.ps = 1). ? td: transmit data data to be transmitted by the spi interface is stored in this re gister. information to be transmitted must be written to the td r register in a right-justified format. 31 30 29 28 27 26 25 24 -------lastxfer 23 22 21 20 19 18 17 16 ---- pcs 15 14 13 12 11 10 9 8 td[15:8] 76543210 td[7:0]
467 32099a?avr32?06/09 at32uc3l 21.8.5 status register name: sr access type: read-only offset: 0x10 reset value: 0x00000000 ? spiens: spi enable status 1: this bit is set when the spi is enabled. 0: this bit is cleared when the spi is disabled. ? undes: underrun error st atus (slave mode only) 1: this bit is set when a transfer begins whereas no data has been loaded in the tdr register. 0: this bit is cleared when the sr register is read. ? txempty: transmission registers empty 1: this bit is set when tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. 0: this bit is cleared as soon as data is written in tdr. ? nssr: nss rising 1: a rising edge occurred on nss pin since last read. 0: this bit is cleared when the sr register is read. ? ovres: overrun error status 1: this bit is set when an overrun has occurred. an overrun occu rs when rdr is loaded at least twice from the serializer since the last read of the rdr. 0: this bit is cleared when the sr register is read. ? modf: mode fault error 1: this bit is set when a mode fault occurred. 0: this bit is cleared when the sr register is read. ? tdre: transmit data register empty 1: this bit is set when the last data written in the tdr register has been transferred to the serializer. 0: this bit is cleared when data has been written to tdr and not yet transferred to the serializer. tdre equals zero when the spi is disabled or at re set. the spi enable command sets this bit to one. ? rdrf: receive data register full 1: data has been received and the received data has been transferr ed from the serializer to rdr since the last read of rdr. 0: no data has been received since the last read of rdr 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------spiens 15 14 13 12 11 10 9 8 - - - - - undes txempty nssr 76543210 - - - - ovres modf tdre rdrf
468 32099a?avr32?06/09 at32uc3l 21.8.6 interrupt enable register name: ier access type: write-only offset: 0x14 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - undes txempty nssr 76543210 - - - - ovres modf tdre rdrf
469 32099a?avr32?06/09 at32uc3l 21.8.7 interrupt disable register name: idr access type: write-only offset: 0x18 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - undes txempty nssr 76543210 - - - - ovres modf tdre rdrf
470 32099a?avr32?06/09 at32uc3l 21.8.8 interrupt mask register name: imr access type: read-only offset: 0x1c reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - - undes txempty nssr 76543210 - - - - ovres modf tdre rdrf
471 32099a?avr32?06/09 at32uc3l 21.8.9 chip select register 0 name: csr0 access type: read/write offset: 0x30 reset value: 0x00000000 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers wi th the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equation determines the delay: ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equat ions determine the delay: ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to de rive the spck baud rate from the clk_spi. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: writing the scbr field to zero is forbidden. triggering a transfer while scbr is zero can lead to unpredictable results. at reset, scbr is zero and the user has to write it to a valid value before performing the first transfer. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol delay between consecutive transfers 32 dlybct clkspi ------------------------------------ = delay before spck dlybs clkspi --------------------- = spck baudrate clkspi scbr --------------------- =
472 32099a?avr32?06/09 at32uc3l ? bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. ? csaat: chip select active after transfer 1: the peripheral chip select does not ri se after the last transfer is achieved. it remains active until a new transfer is requ ested on a different chip select. 0: the peripheral chip select line rises as soon as the last transfer is achieved. ? csnaat: chip select not active afte r transfer (ignored if csaat = 1) 0: the peripheral chip select does not rise between two transfers if the tdr is reloaded before the end of the first transfer a nd if the two transfers occur on the same chip select. 1: the peripheral chip select rises system atically between each transfe r performed on the same slave for a minimal duration of: (if dlybct field is different from 0) (if dlybct field equals 0) ? ncpha: clock phase 1: data is captured on the leading edge of spck and changed on the following edge of spck. 0: data is changed on the leading edge of spck and captured on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the requir ed clock/data relationship between master and slave devices. ?cpol: clock polarity 1: the inactive state value of spck is logic level one. 0: the inactive state value of spck is logic level zero. cpol is used to determine the inactive state value of the seri al clock (spck). it is used wit h ncpha to produce the required clock/data relationship between master and slave devices. bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 reserved 1110 reserved 1111 reserved dlybcs clkspi ---------------------- - dlybcs 1 + clkspi -------------------------------- -
473 32099a?avr32?06/09 at32uc3l 21.8.10 chip select register 1 name: csr1 access type: read/write offset: 0x34 reset value: 0x00000000 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers wi th the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equation determines the delay: ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equat ions determine the delay: ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to de rive the spck baud rate from the clk_spi. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: writing the scbr field to zero is forbidden. triggering a transfer while scbr is zero can lead to unpredictable results. at reset, scbr is zero and the user has to write it to a valid value before performing the first transfer. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol delay between consecutive transfers 32 dlybct clkspi ------------------------------------ = delay before spck dlybs clkspi --------------------- = spck baudrate clkspi scbr --------------------- =
474 32099a?avr32?06/09 at32uc3l ? bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. ? csaat: chip select active after transfer 1: the peripheral chip select does not ri se after the last transfer is achieved. it remains active until a new transfer is requ ested on a different chip select. 0: the peripheral chip select line rises as soon as the last transfer is achieved. ? csnaat: chip select not active afte r transfer (ignored if csaat = 1) 0: the peripheral chip select does not rise between two transfers if the tdr is reloaded before the end of the first transfer a nd if the two transfers occur on the same chip select. 1: the peripheral chip select rises system atically between each transfe r performed on the same slave for a minimal duration of: (if dlybct field is different from 0) (if dlybct field equals 0) ? ncpha: clock phase 1: data is captured on the leading edge of spck and changed on the following edge of spck. 0: data is changed on the leading edge of spck and captured on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the requir ed clock/data relationship between master and slave devices. ?cpol: clock polarity 1: the inactive state value of spck is logic level one. 0: the inactive state value of spck is logic level zero. cpol is used to determine the inactive state value of the seri al clock (spck). it is used wit h ncpha to produce the required clock/data relationship between master and slave devices. bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 reserved 1110 reserved 1111 reserved dlybcs clkspi ---------------------- - dlybcs 1 + clkspi -------------------------------- -
475 32099a?avr32?06/09 at32uc3l 21.8.11 chip select register 2 name: csr2 access type: read/write offset: 0x38 reset value: 0x00000000 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers wi th the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equation determines the delay: ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equat ions determine the delay: ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to de rive the spck baud rate from the clk_spi. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: writing the scbr field to zero is forbidden. triggering a transfer while scbr is zero can lead to unpredictable results. at reset, scbr is zero and the user has to write it to a valid value before performing the first transfer. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol delay between consecutive transfers 32 dlybct clkspi ------------------------------------ = delay before spck dlybs clkspi --------------------- = spck baudrate clkspi scbr --------------------- =
476 32099a?avr32?06/09 at32uc3l ? bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. ? csaat: chip select active after transfer 1: the peripheral chip select does not ri se after the last transfer is achieved. it remains active until a new transfer is requ ested on a different chip select. 0: the peripheral chip select line rises as soon as the last transfer is achieved. ? csnaat: chip select not active afte r transfer (ignored if csaat = 1) 0: the peripheral chip select does not rise between two transfers if the tdr is reloaded before the end of the first transfer a nd if the two transfers occur on the same chip select. 1: the peripheral chip select rises system atically between each transfe r performed on the same slave for a minimal duration of: (if dlybct field is different from 0) (if dlybct field equals 0) ? ncpha: clock phase 1: data is captured on the leading edge of spck and changed on the following edge of spck. 0: data is changed on the leading edge of spck and captured on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the requir ed clock/data relationship between master and slave devices. ?cpol: clock polarity 1: the inactive state value of spck is logic level one. 0: the inactive state value of spck is logic level zero. cpol is used to determine the inactive state value of the seri al clock (spck). it is used wit h ncpha to produce the required clock/data relationship between master and slave devices. bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 reserved 1110 reserved 1111 reserved dlybcs clkspi ---------------------- - dlybcs 1 + clkspi -------------------------------- -
477 32099a?avr32?06/09 at32uc3l 21.8.12 chip select register 3 name: csr3 access type: read/write offset: 0x3c reset value: 0x00000000 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers wi th the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equation determines the delay: ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equat ions determine the delay: ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to de rive the spck baud rate from the clk_spi. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: writing the scbr field to zero is forbidden. triggering a transfer while scbr is zero can lead to unpredictable results. at reset, scbr is zero and the user has to write it to a valid value before performing the first transfer. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat csnaat ncpha cpol delay between consecutive transfers 32 dlybct clkspi ------------------------------------ = delay before spck dlybs clkspi --------------------- = spck baudrate clkspi scbr --------------------- =
478 32099a?avr32?06/09 at32uc3l ? bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. ? csaat: chip select active after transfer 1: the peripheral chip select does not ri se after the last transfer is achieved. it remains active until a new transfer is requ ested on a different chip select. 0: the peripheral chip select line rises as soon as the last transfer is achieved. ? csnaat: chip select not active afte r transfer (ignored if csaat = 1) 0: the peripheral chip select does not rise between two transfers if the tdr is reloaded before the end of the first transfer a nd if the two transfers occur on the same chip select. 1: the peripheral chip select rises system atically between each transfe r performed on the same slave for a minimal duration of: (if dlybct field is different from 0) (if dlybct field equals 0) ? ncpha: clock phase 1: data is captured on the leading edge of spck and changed on the following edge of spck. 0: data is changed on the leading edge of spck and captured on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the requir ed clock/data relationship between master and slave devices. ?cpol: clock polarity 1: the inactive state value of spck is logic level one. 0: the inactive state value of spck is logic level zero. cpol is used to determine the inactive state value of the seri al clock (spck). it is used wit h ncpha to produce the required clock/data relationship between master and slave devices. bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 reserved 1110 reserved 1111 reserved dlybcs clkspi ---------------------- - dlybcs 1 + clkspi -------------------------------- -
479 32099a?avr32?06/09 at32uc3l 21.8.13 write protection control register register name: wpcr access type: read-write offset: 0xe4 reset value: 0x00000000 ? spiwpkey: spi write protection key password if a value is written in spiwpen, the value is taken into acc ount only if spiwpkey is written wit h ?spi? (spi written in ascii code, i.e. 0x535049 in hexadecimal). ? spiwpen: spi write protection enable 1: the write protection is enabled 0: the write protection is disabled 31 30 29 28 27 26 25 24 spiwpkey[23:16] 23 22 21 20 19 18 17 16 spiwpkey[15:8] 15 14 13 12 11 10 9 8 spiwpkey[7:0] 76543210 -------spiwpen
480 32099a?avr32?06/09 at32uc3l 21.8.14 write protection status register register name: wpsr access type: read-only offset: 0xe8 reset value: 0x00000000 ? spiwpvsrc: spi write protection violation source this field indicates the peripheral bus offset of th e register concerned by the violation (mr or csrx) ? spiwpvs: spi write prot ection violation status 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 spiwpvsrc 76543210 - - - - - spiwpvs spiwpvs value violation type 1 the write protection has blocked a write access to a protected register (since the last read). 2 software reset has been performed while write protection was enabled (since the last read or since the last write acce ss on mr, ier, idr or csrx). 3 both write protection violation and software reset with write protection enabled have occurred since the last read. 4 write accesses have been detected on mr (while a chip select was active) or on csri (while the chip select ?i? was active) since the last read. 5 the write protection has blocked a write acce ss to a protected register and write accesses have been detected on mr (while a chip select was active) or on csri (while the chip select ?i? was active) since the last read. 6 software reset has been performed while write protection was enabled (since the last read or since the last write access on mr, ier, idr or csrx) and some write accesses have been detected on mr (while a chip select was active) or on csri (while the chip select ?i? was active) since the last read. 7 - the write protection has blocked a write access to a protected register. and - software reset has been performed while write protection was enabled. and - write accesses have been detected on mr (while a chip select was active) or on csri (while the chip select ?i? was active) since the last read.
481 32099a?avr32?06/09 at32uc3l 21.8.15 version register register name: version access type: read-only offset: 0xfc reset value: ? ? variant reserved. no functionality associated. ? version version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 version[11:8] 76543210 version[7:0]
482 32099a?avr32?06/09 at32uc3l 21.9 module configuration the specific configuration for each spi instance is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. table 21-4. spi clock name module name clock name spi clk_spi table 21-5. register reset value version 0x00000211
483 32099a?avr32?06/09 at32uc3l 22. two-wire master interface (twim) rev 1.0.1.0 22.1 features ? compatible with i 2 c standard ? multi-master support ? 100 and 400 kbit/s transfer speeds ? 7- and 10-bit and general call addressing ? compatible with smbus standard ? hardware packet error checking (crc) ge neration and verification with ack control ? smbus alert interface ? 25 ms clock low timeout delay ? 10 ms master cumulative clock low extend time ? 25 ms slave cumulative clock low extend time ? compatible with pmbus ? compatible with atmel two-wi re interface se rial memories ? dma interface for reducing cpu load ? arbitrary transfer lengths, including 0 data bytes ? optional clock stretching if transmit or receive buffers not ready for data transfer 22.2 overview the atmel two-wire interface master (twim) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. it can be used wi th any atmel two-wire interface bus serial eeprom and i2c compatible device such as a real rime cl ock (rtc), dot ma trix/graphic lcd controller and temperature sensor, to name a few. twim is always a bus master and can transfer sequential or single bytes. multiple ma ster capability is support ed. arbitration of the bus is performed internally and relinquishes the bus automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. table 22-1 on page 483 lists the compatibility level of the atmel two- wire interface in master mode and a full i2c compatible device. note: 1. start + b000000001 + ack + sr table 22-1. atmel twim compatib ility with i2c standard i2c standard atmel twim standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7- or 10-bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) supported clock stretching supported
484 32099a?avr32?06/09 at32uc3l table 22-2 on page 484 lists the compatibility le vel of the atmel two-wire master interface and a full smbus compatible master. 22.3 list of abbreviations table 22-2. atmel twim compatibilit y with smbus standard smbus standard atmel twim bus timeouts supported address resolution protocol supported alert supported host functionality supported packet error checking supported table 22-3. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge pstop sstart sr repeated start sadr slave address adr any address except sadr r read wwrite
485 32099a?avr32?06/09 at32uc3l 22.4 block diagram figure 22-1. block diagram 22.5 application block diagram figure 22-2. application block diagram 22.6 i/o lines description peripheral bus bridge two-wire interface i/o controller twck twd intc twi interrupt power manager clk_twim twalm twi master twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp table 22-4. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output twalm smbus smbalert input/output
486 32099a?avr32?06/09 at32uc3l 22.7 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 22.7.1 i/o lines both twd and twck are bidirectional lines, connected to a positive supply voltage via a cur- rent source or pull-up resistor (see figure 22-2 on page 485 ). when the bus is free, both lines are high. the output stages of devices connec ted to the bus must have an open-drain or open- collector to perform the wired-and function. twalm is used to implement the optional smbus smbalert signal. twd, twck and twalm pins may be multiplex ed with i/o controller lines. to enable the twim, the programmer must perform the following steps: ? program the i/o controller to: ? dedicate twd, twck and optionally twalm as peripheral lines. ? define twd, twck and optionally twalm as open-drain. 22.7.2 power management if the cpu enters a sleep mode th at disables clocks used by the twim, the twim will stop functioning and resume operation after the system wakes up from sleep mode. 22.7.3 clocks the clock for the twim bus interface (clk_twim) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the twim before disabling the clock, to avoid freezing the twim in an undefined state. 22.7.4 interrupts the twim interrupt request lines are connected to the interrupt controller. using the twim interrupts requires the interrupt controller to be programmed first. 22.7.5 debug operation when an external debugger forces the cpu into debug mode, the twim continues normal operation. if the twim is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging.
487 32099a?avr32?06/09 at32uc3l 22.8 functional description 22.8.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 22-4 on page 487 ). each transfer begins with a start condition and terminates with a stop condition (see fig- ure 22-4 on page 487 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. figure 22-3. start and stop conditions figure 22-4. transfer format 22.8.2 operation the twim has two modes of operation: ? master transmitter mode ? master receiver mode the master is the device which starts and st ops a transfer and generates the twck clock. these modes are described in the following chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop
488 32099a?avr32?06/09 at32uc3l 22.8.2.1 clock generation the clock waveform generator register (cwgr) is used to control the waveform of the twck clock. cwgr must be programmed so t hat the desired twi bus timings are generated. cwgr describes bus timings as a function of cycles of a prescaled clock. the clock prescal- ing can be selected through the exp field in cwgr. cwgr has the following fields: low: prescaled clock cycles in cl ock low count. used to time t low . and t buf . high: prescaled clock cycles in cl ock high count. used to time t high . stasto: prescaled clock cycles in cl ock high count. used to time t hd_sta , t su_sta , t su_sto . data: prescaled clock cycles for data setu p and hold count. used to time t hd_dat , t su_dat . exp: specifies the clo ck prescaler setting. note that the total clock low time generated is the sum of t hd_dat + t su_dat + t low . any slave or other bus master taking part in the transfer may extend the twck low period at any time. figure 22-5. bus timing diagram 22.8.2.2 setting up and performing a transfer operation of twim is mainly controlled by the control register (cr) and the command reg- ister (cmdr). the following list presents th e main steps in a ty pical communication: 1. before any transfers can be performed, bus timings must be configured by program- ming the clock waveform generator register (cwgr). if operating in smbus mode, the smbus timing register (smbtr) register must also be configured. 2. if a dma controller is to be used for the transfers, it must be set up. 3. cmdr or ncmdr must be programmed with a value describing the transfer to be performed. f prescaled f clkpb 2 exp 1 + ) () ------------------------- = s t hd:sta t low t su:dat t high t hd:dat t low p t su:sto sr t su:sta t su:dat
489 32099a?avr32?06/09 at32uc3l the interrupt system can be set up to give interrupt request on specific events or error condi- tions, for example when the transfer is complete or if arbitration is lost. the controller will refuse to star t a new transfer while anak, dnak or arblst is set in the status register (sr). this is necessary to avoi d a race when the software issues a continua- tion of the current transfer at the same time as one of these errors happen. also, if anak or dnak occur, a stop condition is sent automatically. the progr ammer will have to restart the transmission by clearing the errors bit in sr after resolving the cause for the nack. after a data or address nack from the slav e, a stop will be transmitted automatically. note that the valid bit in cmdr is not cleared in this case. if this transfer is to be discarded, the valid bit can be cleared manually allowing any command in ncmdr to be copied into cmdr. 22.8.3 master transmitter mode a start condition is transmitte d and master transmitter mode is initiated when the bus is free and cmdr has been written with start=1 and read=0. start and sadr+w will then be transmitted. during the address acknowledge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to acknowledge the address. the master polls the data line during this clock pulse and sets the address not acknowledged bit (anak ) in the status register if no slave acknowledges the address. after the address phase, the following is repeated: while (nbytes>0) 1. wait until thr contains a valid data byte, stretching low period of twck. sr.txrdy indicates the state of thr. software or a dma controller must write the data byte to thr. 2. transmit this data byte 3. decrement nbytes 4. if (nbytes==0) and stop=1, transmit stop condition programming cmdr with start=stop=1 and n bytes=0 will generate a transmission with no data bytes, ie start, sadr+w, stop. twi transfers require the slave to acknowledge each received data byte. during the acknowl- edge clock pulse (9th pulse), the master rel eases the data line (high), enabling the slave to pull it down in order to generate the acknowl edge. the master polls the data line during this clock pulse and sets the data acknowledge bit (dnack) in the status register if the slave does not acknowledge the data by te. as with the other status bits, an interrupt can be gener- ated if enabled in the interrupt enable register (twim_ier). txrdy is used as transmit ready for the pe ripheral dma controller transmit channel. the end of a command is marked by setting the sr.ccomp bit to one. see figure 22-6 on page 490 and figure 22-7 on page 490 .
490 32099a?avr32?06/09 at32uc3l figure 22-6. master write with one data byte figure 22-7. master write with mu ltiple data bytes 22.8.4 master receiver mode a start condition is transmitted and master receiver mode is initiated when the bus is free and cmdr has been written with start=1 and read=1. start and sadr+r will then be transmitted. during the address acknowledge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to acknowledge the address. the master polls the data line during this clock pulse and sets the address not acknowledged bit (anak) in the status register if no slave acknowledges the address. after the address phase, the following is repeated: while (nbytes>0) 1. wait until rhr is empty, st retching low period of twck. sr.rxrdy indicates the state of rhr. software or a dma controller must read any data byte present in rhr. 2. release twck generating a clock that the slave uses to transmit a data byte. 3. place the received data byte in rhr, set rxrdy. 4. if nbytes=0, generate a nak after the data byte, otherwise generate an ack. 5. decrement nbytes 6. if (nbytes==0) and stop=1, transmit stop condition. programming cmdr with start=stop=1 and n bytes=0 will generate a transmission with no data bytes, ie start, dadr+r, stop the twi transfers require the master to acknowledge each received data byte. during the acknowledge clock pulse (9th pulse), the slav e releases the data line (high), enabling the master to pull it down in order to generate the acknowledge. all data bytes except the last are tcomp txrdy write thr (data) stop sent automatically (ack received and nbytes= 0) twd a data a s dadr w p nbytes set to 1 a data n a s dadr w data n+5 a p data n+m a tcomp txrdy write thr (data n) nbytes set to m write thr (data n+1) write thr (data n+m) last data sent stop sent automatically (ack received and nbytes= 0) twd
491 32099a?avr32?06/09 at32uc3l acknowledged by the master. not acknowledging the last byte informs the slave that the trans- fer is finished. rxrdy is used as receive ready for the peripheral dma controller receive channel. figure 22-8. master read with one data byte figure 22-9. master read with mu ltiple data bytes 22.8.5 using the peripheral dma controller the use of the peripheral dma controller si gnificantly reduces the cpu load. the program- mer can set up ring buffers for the dma controller, containing data to transmit or free buffer space to place received data. to assure correct behavior, respect the following programming sequences: 22.8.5.1 data transmit with the peripheral dma controller 1. initialize the transmit peripheral dma controller (memory pointers, size, etc.). 2. configure the twim (adr, nbytes, etc.). 3. start the transfer by setting the peripheral dma controller txten bit. 4. wait for the peripheral dma controller end tx flag. 5. disable the peripheral dma controller by setting the peripheral dma controller txdis bit. a s dadr r data n p tcomp write start & stop bit, nbytes=1 rxrdy read rhr twd n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd tcomp write start + stop bit nbytes=m rxrdy send stop when nbytes=0 read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m)
492 32099a?avr32?06/09 at32uc3l 22.8.5.2 data receive with th e peripheral dma controller 1. initialize the receive peripheral dma controller (memory pointers, size, etc.). 2. configure the twim (adr, nbytes, etc.). 3. start the transfer by setting the peripheral dma controller rxten bit. 4. wait for the peripheral dma controller end rx flag. 5. disable the peripheral dma controller by setting the peripheral dma controller rxdis bit. 22.8.6 multi-master mode more than one master may access the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. the sr.arblst flag will be set. when the stop is detected, the master who lost arbitration may reinitiate the data transfer. arbitration is illustrated in figure 22-11 on page 493 . if the user starts a transfer and if the bus is busy, twim automatically waits for a stop condi- tion on the bus before initiating the transfer (see figure 22-10 on page 492 ). note: the state of the bus (busy or free) is not indicated in the user interface. figure 22-10. programmer sends data while the bus is busy twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free
493 32099a?avr32?06/09 at32uc3l figure 22-11. arbitration cases 22.8.7 combined transfers cmdr and ncmdr may be used to generate longer sequences of connected transfers, since generation of start and/or stop conditions is programmable on a per-command basis. programming ncmdr wit h start=1 when the previous transfer was programmed with stop=0 will cause a repeated start on the bu s. the ability to gene rate such connected transfers allows arbitrary transfer lengths, si nce it is legal to program cmdr with both start=0 and stop=0. if this is done in master receiver mode, the cmdr.acklast bit must also be controlled. as for single data transfers, the txrdy and rxrd y bits in the status register indicates when data to transmit can be written to the thr, or when received data can be read from rhr. transfer of data to thr and from rhr can also be done automatically by dma, see ?using the peripheral dma controller? on page 491 22.8.7.1 write followed by write consider the following transfer: start, dadr+w, data+a, data+a, repstart, dadr+w, data+a, data+a, stop. to generate this transfer: 1. program cmdr with start=1, stop=0, dadr, nbytes=2 and read=0. 2. program ncmdr with start=1, st op=1, dadr, nbytes=2 and read=0. 3. wait until sr.txrdy==1, then write first data byte to transfer to thr. 4. wait until sr.txrdy==1, then write second data byte to transfer to thr. twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
494 32099a?avr32?06/09 at32uc3l 5. wait until sr.txrdy==1, then write third data byte to transfer to thr. 6. wait until sr.txrdy==1, then write fourth data byte to transfer to thr. 22.8.7.2 read followed by read consider the following transfer: start, dadr+r, data+a, data+na, repstart, dadr+r, data+a, data+na, stop. to generate this transfer: 1. program cmdr with start=1, stop=0, dadr, nbytes=2 and read=1. 2. program ncmdr with start=1, st op=1, dadr, nbytes=2 and read=1. 3. wait until sr.rxrdy==1, then read first data byte received from rhr. 4. wait until sr.rxrdy==1, then read second data byte received from rhr. 5. wait until sr.rxrdy==1, then read third data byte received from rhr. 6. wait until sr.rxrdy==1, then read fourth data byte received from rhr. if combining several transfers, without any stop or repeated start between them, remember to set the acklast bit in cmdr to keep from ending each of the partial transfers with a nack. 22.8.7.3 write followed by read consider the following transfer: start, dadr+w, data+a, data+a, repstart, dadr+r, data+a, data+na, stop. figure 22-12. combining a write and read transfer to generate this transfer: 1. program cmdr with start=1, stop=0, dadr, nbytes=2 and read=0. 2. program ncmdr with start=1, st op=1, dadr, nbytes=2 and read=1. 3. wait until sr.txrdy==1, then write first data byte to transfer to thr. 4. wait until sr.txrdy==1, then write second data byte to transfer to thr. 5. wait until sr.rxrdy==1, then read first data byte received from rhr. 6. wait until sr.rxrdy==1, then read second data byte received from rhr. 22.8.7.4 read followed by write consider the following transfer: s adr w a data 0 a data 1 adr sr na r a data 2 a data 3 a p data 0 data 1 data 2 data 3 twd twi_thr twi_rhr txrdy rxrdy tcomp
495 32099a?avr32?06/09 at32uc3l start, dadr+r, data+a, data+na, repstart, dadr+w, data+a, data+a, stop. figure 22-13. combining a read and write transfer to generate this transfer: 1. program cmdr with start=1, stop=0, dadr, nbytes=2 and read=1. 2. program ncmdr with start=1, st op=1, dadr, nbytes=2 and read=0. 3. wait until sr.rxrdy==1, then read first data byte received from rhr. 4. wait until sr.rxrdy==1, then read second data byte received from rhr. 5. wait until sr.txrdy==1, then write first data byte to transfer to thr. 6. wait until sr.txrdy==1, then write second data byte to transfer to thr. 22.8.8 ten bit addressing setting cmdr.tenbit enables 10-bit addressing in hardware. performing transfers with 10- bit addressing is similar to transfers with 7-bit addresses, except that bits 10:7 of cmdr.adr must be set appropriately. in figure 22-14 on page 495 and figure 22-15 on page 496 , the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 22.8.8.1 master transmitter to perform a master transmitter transfer, 1. program cmdr with tenbit=1, repsame= 0, read=0, start=1, stop=1 and the desired address and nbytes value. figure 22-14. a write transfer with 10-bit addressing 22.8.8.2 master receiver when using master receiver mode with 10-bi t addressing, cmdr.repsame must also be controlled. cmdr.repsame must be written to one when the address phase of the transfer s sadr r a data 0 a data 1 sadr sr a w a data 2 a data 3 n a p data 0 data 2 data 3 data 1 tcomp txrdy rxrdy read twi_rhr twd twi_rhr twi_thr s slave address 1st 7 bits p a data rw a1 a2 slave address 2nd byte aa data 11110xx0
496 32099a?avr32?06/09 at32uc3l should consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. the i2c standard specifies that such addressing is required when addressing a slave for reads using 10-bit addressing. to perform a master receiver transfer, 1. program cmdr with tenbit=1, repsam e=0, read=0, start=1, stop=0, nbytes=0 and the desired address. 2. program ncmdr with tenbit=1, repsame=1, read=1, start=1, stop=1 and the desired address and nbytes value. figure 22-15. a read transfer with 10-bit addressing 22.8.9 smbus mode smbus mode is enabled and disabled by the smen and smdis bits in cr. smbus mode operation is similar to i2c opera tion with the following exceptions: ? only 7-bit addressing can be used. ? the smbus standard describes a set of timeout values to ensure progress and throughput on the bus. these timeout values must be programmed into smbtr. ? transmissions can optionally include a crc byte, called packet error check (pec). ? a dedicated bus line smbalert, allows a slave to get a master?s attention. ? a set of addresses have been reserved for protocol handling, such as alert response address (ara) and host header (hh) address. 22.8.9.1 packet error checking each smbus transfer can optionally end with a crc byte, called the pec byte. writing cmdr.pecen to one enables automatic pec handling in the current transfer. transfers with and without pec can freely be intermixed in t he same system, since some slaves may not support pec. the pec lfsr is always updated on every bit transmitted or received, so that pec handling on combined transfers will be correct. in master transmitter mode, the master calculat es a pec value and transmits it to the slave after all data byte s have been transmitted. upon reception of this pec byte, the slave will com- pare it to the pec value it has computed itself. if the values match, the data was received correctly, and the slave will return an ack to the master. if the pec values differ, data was corrupted, and the slave will return a nack value. the dnak bit in sr reflects the state of the last received ack/nack value. some slaves may not be able to check the received pec in time to return a nack if an error occurred. in this case, the slave should always return an ack after the pec byte, and some other mechanism must be implemented to verify that the trans- mission was received correctly. in master receiver mode, the slave calculates a pec value and transmits it to the master after all data bytes have been transmitted. upon recepti on of this pec byte, the master will com- pare it to the pec value it has computed itself. if the values match, the data was received correctly. if the pec values differ, data was corrupted, and the pecerr bit in sr is set. in master receiver mode, the pec byte is always followed by a nack transmitted by the master, since it is the last byte in the transfer. s slave address 1st 7 bits p a data rw a1 a2 slave address 2nd byte a data 11110xx0 sr slave address 1st 7 bits rw a3 11110xx1
497 32099a?avr32?06/09 at32uc3l the pec byte is automatically in serted in a master transmitter transmission if pec is enabled when nbytes reaches zero. the pec byte is ident ified in a master receiver transmission if pec is enabled when nbytes reaches zero. nbytes must therefore be set to the total num- ber of data bytes in the transmission, including the pec byte. in combined transfers, the pecen bit should only be set in the last of the combined transfers. consider the following transfer: s, adr+w, command_byte, ack, sr, adr+ r, data_byte, ack, pec_byte, nack, p this transfer is generated by writing two commands to the command registers. the first com- mand is a write with nbytes=1 and pecen=0, and the second is a read with nbytes=2 and pecen=1. writing a one to the stop bit in cr will place a stop condition on the bus after the current byte. no pec byte will be sent in this case. 22.8.9.2 timeouts the tlows and tlowm fields in smbtr configure the smbus timeout values. if a timeout occurs, the master will transmit a stop condition and leave the bus. the sr.tout bit is also set. 22.8.9.3 smbus alert signal a slave can get the master?s attention by pu lling the twalm line low. sr.smbal will then be set. this can be set up to trigger an interrupt, and software can then take the appropriate action, as defined in the smbus standard. 22.8.10 identifying bus events this chapter lists the different bus events, and how these affects bits in the twim registers. this is intended to help wr iting drivers for the twim. table 22-5. bus events event effect master transmitter has sent a data byte sr.thr is cleared. master receiver has received a data byte sr.rhr is set. start+sadr sent, no ack received from slave sr.anak is set. cmdr.ccomp not set. cmdr.valid remains set. stop automatically transmitted on bus. data byte sent to slave, no ack received from slave sr.dnak is set. cmdr.ccomp not set. cmdr.valid remains set. stop automatically transmitted on bus. arbitration lost sr.arblst is set. cmdr.ccomp not set. cmdr.valid remains set. twck and twd immediately released to a pulled-up state.
498 32099a?avr32?06/09 at32uc3l smbus alert received sr.smbal is set. smbus timeout received sr.smbtout is set. cmdr.ccomp not set. cmdr.valid remains set. stop automatically transmitted on bus. master transmitter receives smbus pec error sr.dnak is set. cmdr.ccomp not set. cmdr.valid remains set. stop automatically transmitted on bus. master receiver discovers smbus pec error sr.pecerr is set. cmdr.ccomp not set. cmdr.valid remains set. stop automatically transmitted on bus. cr.stop is written by user sr.stop is set. cmdr.ccomp set. cmdr.valid remains set. stop transmitted on bus after curr ent byte transfer has finished. table 22-5. bus events event effect
499 32099a?avr32?06/09 at32uc3l 22.9 user interface note: 1. the reset values for these registers are device specific. please refer to the module configuration section at the end of this chapter. table 22-6. twim register memory map offset register register name access reset 0x00 control cr write-only 0x00000000 0x04 clock waveform generator cwgr read/write 0x00000000 0x08 smbus timing smbtr read/write 0x00000000 0x0c command cmdr read/write 0x00000000 0x10 next command ncmdr read/write 0x00000000 0x14 receive holding rhr read-only 0x00000000 0x18 transmit holding thr write-only 0x00000000 0x1c status sr read-only 0x00000002 0x20 interrupt enable register ier write-only 0x00000000 0x24 interrupt disable register idr write-only 0x00000000 0x28 interrupt mask register imr read-only 0x00000000 0x2c status clear register scr write-only 0x00000000 0x30 parameter register pr read-only (1) 0x34 version register vr read-only (1)
500 32099a?avr32?06/09 at32uc3l 22.9.1 control register (cr) name: cr access type: write-only offset: 0x00 reset value: 0x00000000 ? stop: stop the current transfer writing a one to this bit terminates the current transfer, sendi ng a stop condition after the shifter has become idle. if there are additional pending transfers, they will have to be explicitly re started by software after the stop condition has been successfu lly sent. writing a zero to this bit has no effect. ? swrst: software reset writing a one to this bit resets the twim. all transfers ar e halted immediately, possibly violating the bus semantics. writing a zero to this bit has no effect. ? smdis: smbus disable writing a one to this bit disables smbus mode. writing a zero to this bit has no effect. ? smen: smbus enable writing a one to this bit enables smbus mode. writing a zero to this bit has no effect. ? mdis: master disable writing a one to this bit disables the master interface. writing a zero to this bit has no effect. ? men: master enable writing a one to this bit enables the master interface. writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------stop 76543210 swrst - smdis smen - - mdis men
501 32099a?avr32?06/09 at32uc3l 22.9.2 clock waveform generator register (cwgr) name: cwgr access type: read/write offset: 0x04 reset value: 0x00000000 ? exp: clock prescaler used to specify how to prescale the twck clock. coun ters are prescaled according to the following formula ? data: data setu p and hold cycles clock cycles for data setup and hold count. prescaled by cwgr.exp . used to time t hd_dat , t su_dat . ? stasto: start and stop cycles clock cycles in clock high count. prescaled by cwgr.exp. used to time t hd_sta , t su_sta , t su_sto ? high: clock high cycles clock cycles in clock high count. prescaled by cwgr.exp. used to time t high . ? low: clock low cycles clock cycles in clock low count. pre scaled by cwgr.exp. used to time t low , t buf . 31 30 29 28 27 26 25 24 - exp data 23 22 21 20 19 18 17 16 stasto 15 14 13 12 11 10 9 8 high 76543210 low f prescaled f clkpb 2 exp 1 + () ----------------------- =
502 32099a?avr32?06/09 at32uc3l 22.9.3 smbus timing register (smbtr) name: smbtr access type: read/write offset: 0x08 reset value: 0x00000000 ? exp: smbus timeout clock prescaler used to specify how to prescale the ti m and tlowm counters in smbtr. counters are prescaled according to the following formula ? thmax: clock high maximum cycles clock cycles in clock high maximum count. prescaled by smbtr.exp. used for bus free de tection. used to time t high:max . note: uses the prescaler specified by cw gr, not the prescaler specified by smbtr. ? tlowm: master clock stretch maximum cycles clock cycles in master maximum clock stretch count. prescaled by smbtr.exp. used to time t low:mext ? tlows: slave clock stretch maximum cycles clock cycles in slave maximum clock stretch coun t. prescaled by smbtr.exp. used to time t low:sext . 31 30 29 28 27 26 25 24 exp ---- 23 22 21 20 19 18 17 16 thmax 15 14 13 12 11 10 9 8 tlowm 76543210 tlows f prescaled smbus , f clkpb 2 exp 1 + () ----------------------- =
503 32099a?avr32?06/09 at32uc3l 22.9.4 command register (cmdr) name: cmdr access type: read/write offset: 0x0c reset value: 0x00000000 ? acklast: ack last master rx byte writing this bit to zero causes the last byte in master re ceive mode (when nbytes has reached 0) to be nacked. this is the standard way of ending a master receiver transfer. writing this bit to one causes the last byte in master rece ive mode (when nbytes has reached 0) to be acked. used for performing linked transfers in master re ceiver mode with no stop or repeated start between the subtransfers. this is needed when more than 255 bytes are to be received in one single transmission. ? pecen: packet error checking enable writing this bit to zero causes the transfer not to use pec by te verification. the pec lfsr is still updated for every bit transmitted or received. must be used if smbus mode is disabled. writing this bit to one causes the transfer to use pec. pec byte generation (if master transmitter) or pec byte verification (i f master receiver) will be performed. ? nbytes: number of data bytes in transfer the number of data bytes in the transfer. after the specified number of bytes have been transferred, a stop condition is transmitted if cmdr.stop is set. in smbus mode, if pec is used, nbytes includes the pec byte, ie there are nbytes-1 data bytes and a pec byte. ? valid: cmdr valid writing this to zero indicates that cmdr does not contain a valid command. writing this to one indicates that cmdr contains a valid command. this bit is cleared when the command is finished. ? stop: send stop condition write this bit to zero to not transmit a stop condition after the data bytes have been transmitted. write this bit to one to transmit a stop condition after the data bytes have been transmitted. ? start: send start condition write this bit to zero if the transfer in cmdr should not commence with a start or repeated start condition. write this bit to one if the transfer in cmdr should commence with a start or repeate d start condition. if the bus is free when the command is execut ed, a start condition is us ed, if the bus is busy, a repeated start is used. ? repsame: transfer is to same address as previous address only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode. 31 30 29 28 27 26 25 24 ------acklastpecen 23 22 21 20 19 18 17 16 nbytes 15 14 13 12 11 10 9 8 valid stop start repsame tenbit sadr[9:7] 76543210 sadr[6:0] read
504 32099a?avr32?06/09 at32uc3l write this bit to one if the command in cmdr performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. write this bit to zero otherwise. ? tenbit: ten bit addressing mode write this bit to zero to use 7-bit addressing mode. write this bit to one to use 10-bit addressing mode. must not be used when twim is in smbus mode. ? sadr: slave address address of the slave involved in the transfer. bi ts 9-7 are don?t care if 7-bit addressing is used. ? read: transfer direction write this bit to zero to let the master transmit data. write this bit to one to le t the master receive data.
505 32099a?avr32?06/09 at32uc3l 22.9.5 next command register (ncmdr) name: ncmdr access type: read/write offset: 0x10 reset value: 0x00000000 this register is identical to cmdr. when the valid bit in cmdr becomes 0, the contents of ncmdr is copied into cmdr, clearing the valid bit in ncmdr. if the valid bit in cmdr is cleared when ncmdr is written, the contents are copied immediately. 31 30 29 28 27 26 25 24 ------acklastpecen 23 22 21 20 19 18 17 16 nbytes 15 14 13 12 11 10 9 8 valid stop start repsame tenbit sadr[9:7] 76543210 sadr[6:0] read
506 32099a?avr32?06/09 at32uc3l 22.9.6 receive holding register (rhr) name: rhr access type: read-only offset: 0x14 reset value: 0x00000000 ? rxdata: received data when the rxrdy bit in the status regist er (sr) is set, this field contains a byte received from the twi bus. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rxdata
507 32099a?avr32?06/09 at32uc3l 22.9.7 transmit holding register (thr) name: thr access type: write-only offset: 0x18 reset value: 0x00000000 ? txdata: data to transmit write data to be transf erred on the twi bus here. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 txdata
508 32099a?avr32?06/09 at32uc3l 22.9.8 status register (sr) name: sr access type: read-only offset: 0x1c reset value: 0x00000002 ? menb: master interface enable 0: master interface is disabled. 1: master interface is enabled. ? stop: stop request accepted this bit is set when stop request caused by sett ing cr stop has been accepted, and transfer has stopped. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? pecerr: pec error this bit is set when a smbus pec error occurred. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ?tout: timeout this bit is set when a smbus timeout occurred. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? smbalert: smbus alert this bit is set when a smbus alert was received. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? arblst: arbitration lost this bit is set when the actual state of the sda line did not correspond to the data driven onto it, indicating a higher-priori ty transmission in progress by a different master. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? dnak: nak in data phase received this bit is set when no ack was received form slave during data transmission. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? anak: nak in address phase received this bit is set when no ack was received from slave during address phase this bit is cleared by writing 1 to the correspo nding bit in the status clear register (scr). ? idle: master interface is idle this bit is set when no command is in progress, and no command waiting to be issued. otherwise, this bit is cleared. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------menb 15 14 13 12 11 10 9 8 - stop pecerr tout smbalert arblst dnak anak 76543210 - - - idle ccomp crdy txrdy rxrdy
509 32099a?avr32?06/09 at32uc3l ? ccomp: command complete this bit is set when the current command has completed successfully and stop has been transmitted. not set if the command failed due to conditions such as a nak receved from slave. this bit is cleared by writing 1 to the corresp onding bit in the status clear register (scr). ? crdy: ready for more commands this bit is set when cmdr and/or ncmdr is ready to receive one or more commands. this bit is cleared when this is no longer true. ? txrdy: thr data ready this bit is set when thr is ready for one or more data bytes. this bit is cleared when this is no longer tr ue (i.e. thr is full or transmission has stopped). ? rxrdy: rhr data ready this bit is set when rx data are ready to be read from rhr. this bit is cleared when this is no longer true.
510 32099a?avr32?06/09 at32uc3l 22.9.9 interrupt enable register (ier) name: ier access type: write-only offset: 0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - stop pecerr tout smbalert arblst dnak anak 76543210 - - - idle ccomp crdy txrdy rxrdy
511 32099a?avr32?06/09 at32uc3l 22.9.10 interrupt disable register (idr) name: idr access type: write-only offset: 0x24 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - stop pecerr tout smbalert arblst dnak anak 76543210 - - - idle ccomp crdy txrdy rxrdy
512 32099a?avr32?06/09 at32uc3l 22.9.11 interrupt mask register (imr) name: imr access type: read-only offset: 0x28 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - stop pecerr tout smbalert arblst dnak anak 76543210 - - - idle ccomp crdy txrdy rxrdy
513 32099a?avr32?06/09 at32uc3l 22.9.12 status clear register (scr) name: scr access type : write-only offset: 0x2c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - stop pecerr tout smbalert arblst dnak anak 76543210 ----ccomp---
514 32099a?avr32?06/09 at32uc3l 22.9.13 parameter register (pr) name: pr access type: read-only offset: 0x30 reset value: 0x00000000 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
515 32099a?avr32?06/09 at32uc3l 22.10 module configuration the specific configuration for each twim inst ance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 22-7. module clock name module name clock name twim0 clk_twim0 twim1 clk_twim1 table 22-8. register reset values register reset value version 0x0000 0101 parameter 0x0000 0000
516 32099a?avr32?06/09 at32uc3l 23. two-wire slave interface (twis) rev 1.1.2.1 23.1 features ? compatible with i 2 c standard ? 100 and 400 kbit/s transfer speeds ? 7 and 10-bit and general call addressing ? compatible with smbus standard ? hardware packet error checking (crc) ge neration and verification with ack response ? smbalert interface ? 25 ms clock low timeout delay ? 25 ms slave cumulative clock low extend time ? compatible with pmbus ? dma interface for reducing cpu load ? arbitrary transfer lengths, including 0 data bytes ? optional clock stretching if transmit or receive buffers not ready for data transfer ? 32-bit peripheral bus interface for configuration of the interface 23.2 overview the atmel two-wire interface slave (twis) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus i2c or smbus compatible master. twis is always a bus slave and can transfer sequential or single bytes. below, table 23-1 on page 516 lists the compatibility level of t he atmel two-wire slave interface and a full i2c compatible device. note: 1. start + b000000001 + ack + sr table 23-1. atmel twis compatibility with i2c standard i2c standard atmel twis standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nak management supported slope control and input filtering (fast mode) supported clock stretching supported
517 32099a?avr32?06/09 at32uc3l below, table 23-2 on page 517 lists the compatibility level of the atmel two-wire slave inter- face and a full smbus compatible device. 23.3 list of abbreviations 23.4 block diagram figure 23-1. block diagram table 23-2. atmel twis compatibilit y with smbus standard smbus standard atmel twis bus timeouts supported address resolution protocol supported alert supported packet error checking supported table 23-3. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge pstop sstart sr repeated start sadr slave address adr any address except sadr r read wwrite peripheral bus bridge two-wire interface i/o controller twck twd interrupt controller twi interrupt power manager clk_twis twalm
518 32099a?avr32?06/09 at32uc3l 23.5 application block diagram figure 23-2. application block diagram 23.6 i/o lines description 23.7 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 23.7.1 i/o lines both twd and twck are bidirectional lines, connected to a positive supply voltage via a cur- rent source or pull-up resistor (see figure 23-2 on page 518 ). when the bus is free, both lines are high. the output stages of devices connec ted to the bus must have an open-drain or open- collector to perform the wired-and function. twalm is used to implement the optional smbus smbalert signal. twd, twck and twalm pins may be multiplex ed with i/o controller lines. to enable the twis, the programmer must perform the following steps: ? program the i/o controller to: ? dedicate twd, twck and optionally twalm as peripheral lines. ? define twd, twck and optionally twalm as open-drain. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp table 23-4. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output twalm smbus smbalert input/output
519 32099a?avr32?06/09 at32uc3l 23.7.2 power management if the cpu enters a sleep mode that disables clocks used by the twis, the twis will stop functioning and resume operation after the system wakes up from sleep mode. twis is able to wake the system from sleep mode upon address match, see section 23.8.7 on page 526 . 23.7.3 clocks the clock for the twis bus interface (clk_twis) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the twis before disabling the clock, to avoid freezing the twis in an undefined state. 23.7.4 interrupts the twis interrupt request lines are connected to the interrupt controller. using the twis interrupts requires the interrupt controller to be programmed first. 23.7.5 debug operation when an external debugger forces the cpu into debug mode, the twis continues normal operation. if the twis is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 23.8 functional description 23.8.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 23-4 on page 519 ). each transfer begins with a start condition and terminates with a stop condition (see fig- ure 23-3 on page 519 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. figure 23-3. start and stop conditions figure 23-4. transfer format twd twck start stop twd twck start address r/w ack data ack data ack stop
520 32099a?avr32?06/09 at32uc3l 23.8.2 operation twis has two modes of operation: ? slave transmitter mode ? slave receiver mode a master is a device which starts and stops a transfer and generates the twck clock. a slave is assigned an address and responds to requests from the master. these modes are described in the following chapters. figure 23-5. typical application block diagram 23.8.2.1 bus timing the timing register (tr) is used to control the timing of bus signals driven by twis. tr describes bus timings as a function of cycles of the prescaled clk_twis. the clock prescal- ing can be selected through tr.exp. tr has the following fields: tlows: prescaled clock cycles used to time smbus timeout t low:sext . ttout: prescaled clock cycles us ed to time smbus timeout t timeout . sudat: non-prescaled clock cycles for data setup and hold count. used to time t su_dat . exp: specifies the clock prescaler setting used for the smbus timeouts. host with twi interface twd twck atmel twi serial eeprom i2c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2c temp. sensor slave 4 rp: pull up value as given by the i2c standard rp rp f prescaled f clk twis ? 2 exp 1 + ) () --------------------------- =
521 32099a?avr32?06/09 at32uc3l figure 23-6. bus timing diagram 23.8.2.2 setting up and performing a transfer operation of twis is mainly controlled by th e control register (cr) . the following list pres- ents the main steps in a typical communication: 1. before any transfers can be performed, bus timings must be configured by program- ming the timing register (tr). 2. if a dma controller is to be used for the transfers, it must be set up. 3. the control register (cr) must be configured with information such as the slave address, smbus mode, packet error checking (pec), number of bytes to transfer, and which addresses to match. the interrupt system can be set up to give interrupt request on specific events or error condi- tions, for example when a byte has been received. the nbytes register is only used in smbus mode, when pec is enabled. in i2c mode or in smbus mode when pec is disabled, the nbytes register is not used, and should be written to 0. nbytes is updated by hardware, so in order to avoid hazards, software updates of nbytes can only be done through writes to the nbytes register. 23.8.2.3 address matching twis can be set up to match several different addresses. more than one address match may be enabled simultaneously, allowing twis to be assigned to several addresses. the address matching phase is initiated after a start or repeated start condition. when twis receives an address that generates an address match, an ack is automatically returned to the master. in i2c mode: ? the address in cr.adr is checked fo r address match if cr.smatch is set. ? the general call address is checked fo r address match if cr.gcmatch is set. in smbus mode: s t hd:sta t low t su:dat t high t hd:dat t low p t su:sto sr t su:sta t su:dat
522 32099a?avr32?06/09 at32uc3l ? the address in cr.adr is checked fo r address match if cr.smatch is set. ? the alert response address is checked for address match if cr.smal is set. ? the default address is checked for address match if cr.smda is set. ? the host header address is checked for address match if cr.smhh is set. 23.8.2.4 clock stretching any slave or bus master taking part in a transfer may extend the twck low period at any time. twis may extend the twck low period after each byte transfer if cr.stren=1 and: ? module is in slave transmitter mode, data should be transmitted, but thr is empty, or ? module is in slave receiver mode, a byte has been received and placed into the internal shifter, but rhr is full, or ? stretch-on-address-match bit cr.soam=1 and slave was addressed. bus clock remains stretched until all address match bits in sr have been cleared. if cr.stren=0 and: ? module is in slave transmitter mode, data should be transmitted but thr is empty: transmit the value present in thr (the last transmitted byte or reset value), and set sr.urun. ? module is in slave receiver mode, a byte has been received and placed into the internal shifter, but rhr is full: discard the received byte and set sr.orun. 23.8.2.5 bus errors if a bus error (misplaced start or stop) condi tion is detected, the sr.buserr bit is set and twis waits for a new start condition. 23.8.3 slave transmitter mode if twis matches an address in which the r/w bit in the twi address phase transfer is set, it will enter slave transmitte r mode and set sr.tra after the address phase, the following is done: 1. if smbus mode and pec is used, nbytes must be set up with the number of bytes to transmit. this is necessary in order to know when to transmit pec byte. nbytes can also be used to count the number of bytes received if using dma. 2. byte to transmit depends on i2c/smbus mode and cr.pec: ? if in i2c mode or cr.pec=0 or nbytes!=0: twis waits until thr contains a valid data byte, possibly stretching low period of twck. sr.txrdy indicates the state of thr. ? smbus mode and cr.pec=1: if nbytes=0, the generated pec byte is automatically transmitted in stead of a data byte from thr. twck will not be stretched by twis. 3. transmit the correct data byte. set sr.btf when done. 4. update nbytes. if cr.cup is set, n bytes is incremented, otherwise nbytes is decremented. 5. after each data byte has been transferred, the master transmits an ack or nak bit. if a nak bit is received, transfer is fini shed, and twis will wait for a stop or repeated start. if an ack bit is received, more data should be transmitted, jump to step 2. 6. if stop is received, sr.tcomp and sr.sto will be set.
523 32099a?avr32?06/09 at32uc3l 7. if repeated start is received, sr.rep will be set. the twi transfers require the receiver to acknowledge each received data byte. during the acknowledge clock pulse (9th pulse), the slav e releases the data line (high), enabling the master to pull it down in order to generate the acknowledge. the slave polls the data line dur- ing this clock pulse and sets the not acknowledge bit (nak ) in the status register if the master does not acknowledge the data byte. a nak means that the master does not wish to receive additional data bytes. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (ier). txrdy is used as transmit ready for the pe ripheral dma controller transmit channel. the end of the complete transfer is marked by the sr.tcomp bit set to one. see figure 23-7 on page 523 and figure 23-8 on page 523 . figure 23-7. slave transmitter with one data byte figure 23-8. master write with mu ltiple data bytes 23.8.4 slave receiver mode if twis matches an address in which the r/w bit in the twi address phase transfer is cleared, it will enter slave rece iver mode and clear sr.tra. after the address phase, the following is repeated: 1. if smbus mode and pec is used, nbytes must be set up with the number of bytes to receive. this is necessary in order to know which of the received bytes is the pec byte. nbytes can also be used to count the number of bytes received if using dma. 2. receive a byte. set sr.btf when done. tcomp txrdy write thr (data) stop sent automatically (ack received and nbytes= 0) twd a data a s dadr w p nbytes set to 1 a data n a s dadr w data n+5 a p data n+m a tcomp txrdy write thr (data n) nbytes set to m write thr (data n+1) write thr (data n+m) last data sent stop sent automatically (ack received and nbytes= 0) twd
524 32099a?avr32?06/09 at32uc3l 3. update nbytes. if cr.cup is written to one, nbytes is incremented, otherwise nbytes is decremented. nbytes is usually configured to count downwards if pec is used. 4. after a data byte has been received, the slave transmits an ack or nak bit. for ordi- nary data bytes, the cr.ack field controls if an ack or nak should be returned. if pec is enabled and the last byte received was a pec byte (indicated by nbytes=0), twis will automatically return an ack if the pec value was correct, otherwise a nak will be returned. 5. if stop is received, sr.tcomp will be set. 6. if repeated start is received, sr.rep will be set. the twi transfers require the receiver to acknowledge each received data byte. during the acknowledge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line dur- ing this clock pulse. rxrdy is used as receive ready for the peripheral dma controller receive channel. figure 23-9. slave receiver with one data byte figure 23-10. slave receiver with multiple data bytes 23.8.5 using the peripheral dma controller the use of the peripheral dma controller si gnificantly reduces the cpu load. the program- mer can set up ring buffers for the dma controller, containing data to transmit or free buffer space to place received data. by initializi ng nbytes to 0 before a transfer, and setting a s dadr r data n p tcomp write start & stop bit, nbytes=1 rxrdy read rhr twd n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd tcomp write start + stop bit nbytes=m rxrdy send stop when nbytes=0 read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m)
525 32099a?avr32?06/09 at32uc3l cr.cup, nbytes is incremented by 1 each time a data has been transmitted or received. this allows the programmer to detect how much data was actually transferred by the dma system. to assure correct behavior, respect the following programming sequences: 23.8.5.1 data transmit with the peripheral dma controller 1. initialize the transmit peripheral dma controller (memory pointers, size, etc.). 2. configure the twis (adr, nbytes, etc.). 3. start the transfer by setting the peripheral dma controller txten bit. 4. wait for the peripheral dma controller end tx flag. 5. disable the peripheral dma controller by setting the peripheral dma controller txdis bit. 23.8.5.2 data receive with th e peripheral dma controller 1. initialize the receive peripheral dma controller (memory pointers, size - 1 , etc.). 2. configure the twis (adr, nbytes, etc.). 3. start the transfer by setting the peripheral dma controller rxten bit. 4. wait for the peripheral dma controller end rx flag. 5. disable the peripheral dma controller by setting the peripheral dma controller rxdis bit. 23.8.6 smbus mode smbus mode is enabled when cr.smen is written to one. smbus mode operation is similar to i2c operation with the following exceptions: ? only 7-bit addressing can be used. ? the smbus standard describes a set of timeout values to ensure progress and throughput on the bus. these timeout values must be programmed into tr. ? transmissions can optionally include a crc byte, called packet error check (pec). ? a dedicated bus line, smbalert, allows a slave to get a master?s attention. ? a set of addresses have been reserved for protocol handling, such as alert response address (ara) and host header (hh) address. address matching on these addresses can be enabled by configuring cr appropriately. 23.8.6.1 packet error checking each smbus transfer can opti onally end with a crc byte, call ed the pec byte. writing a one to cr.pecen enables automatic pec handling in the current transfer. the pec generator is always updated on every bit transmitted or received, so that pec handling on following linked transfers will be correct. in slave receiver mode, the master calculates a pec value and transmits it to the slave after all data bytes have been transm itted. upon reception of this pec byte, the slave will compare it to the pec value it has computed itself. if the values match, the data was received correctly, and the slave will return an ack to the master. if the pec values differ, data was corrupted, and the slave will return a nak value. the sr.s mbpecerr bit is set automatically if a pec error occurred. in slave transmitter mode, the slave calculates a pec value and transmits it to the master after all data bytes have been transmitted. upon recepti on of this pec byte, the master will com-
526 32099a?avr32?06/09 at32uc3l pare it to the pec value it has computed itself. if the values match, the data was received correctly. if the pec values differ, data was corrupted, and the master must take appropriate action. the pec byte is automatically inserted in a slave transmitte r transmission if pec enabled when nbytes reaches zero. the pec byte is i dentified in a slave receiver transmission if pec enabled when nbytes reaches zero. nbytes must therefore be set to the total number of data bytes in the transmission, including the pec byte. 23.8.6.2 timeouts the timing register (tr) configures the smbu s timeout values. if a timeout occurs, the slave will leave the bus. the sr.smbtout bit is also set. 23.8.6.3 smbalert a slave can get the master?s attention by pullin g the smbalert line low. this is done by set- ting the cr.smbal bit. this will also enable address match on the alert response address (ara). 23.8.7 wakeup from sleep modes by twi address match the twis is able to wake the device up from sleep modes upon an address match, including modes where clk_twis is stopped. if a twi start condition is received in a sleep mode where clk_twis is stop ped, twis will stretch twck until clk_twis has started. the time required for restarting clk_twis depends on which sleep mode the system was in. when clk_twis has been restarted, the twck stretching is released and the slave address will be received on the twi bus. to save power, only a limited part of the device including twis receives a clock at this time. if the ad dress phase causes a twis address match, the entire device will be wakened and normal twis address match actions performed. normal twi transfer will then follow. if the twis was not addressed by the transfer, clk_twis will automatically be stopp ed and the system will go back to the original sleep mode. 23.8.8 identifying bus events this chapter lists the different bus events, and how these affects bits in the twis registers. this is intended to help wr iting drivers for the twis. table 23-5. bus events event effect slave transmitter has sent a data byte sr.thr is cleared. sr.btf is set. the value of the ack bit sent immediately after the data byte is given by cr.ack. slave receiver has received a data byte sr.rhr is set. sr.btf is set. sr.nak updated according to value of ack bit received from master. start+sadr on bus, but address is to another slave none. start+sadr on bus, current slave is addressed, but address match enable bit in cr is not set none.
527 32099a?avr32?06/09 at32uc3l start+sadr on bus, current slave is addressed, corresponding address match enable bit in cr set correct address match bit in sr is set. sr.tra updated according to transfer direction. slave enters appropriate transfer direction mode and data transfer can commence. start+sadr on bus, current slave is addressed, corresponding address match enable bit in cr set, sr.stren and sr.soam are set. correct address match bit in sr is set. sr.tra updated according to transfer direction. slave stretches twck immediately after transmitting the address ack bit. twck remains stretched until all address match bits in sr have been cleared. slave the enters appropriate transfer direction mode and data transfer can commence. repeated start received after being addressed sr.rep set. sr.tcomp unchanged. stop received after being addressed sr.sto set. sr.tcomp set. start, repeated start or stop received in illegal position on bus sr.buserr set. data is to be received in slave receiver mode, sr.stren is set, and rhr is full twck is stretched until rhr has been read. data is to be transmitted in slave receiver mode, sr.stren is set, and thr is empty twck is stretched until thr has been written. data is to be received in slave receiver mode, sr.stren is cleared, and rhr is full twck is not stretched, read data is discarded. sr.orun is set. data is to be transmitted in slave receiver mode, sr.stren is cleared, and thr is empty twck is not stretched, previous c ontents of thr is written to bus. sr.urun is set. smbus timeout received sr.smbtout is set. twck and twd are immediately released. slave transmitter in smbus pec mode has transmitted a pec byte, that was not identical to the pec calculated by the master receiver. master receiver will transmit a nak as usual after the last byte of a master receiver transfer. master receiver will retry the transfer at a later time. slave receiver discovers smbus pec error sr.smbpecerr is set. nak returned after the data byte. table 23-5. bus events event effect
528 32099a?avr32?06/09 at32uc3l 23.9 user interface note: 1. the reset values for these registers are de vice specific. please refer to the module configu- ration section at the end of this chapter. table 23-6. twis register memory map offset register register name access reset 0x00 control register cr read/write 0x00000000 0x04 nbytes register nbytes read/write 0x00000000 0x08 timing register tr read/write 0x00000000 0x0c receive holding register rhr read-only 0x00000000 0x10 transmit holding register thr write-only 0x00000000 0x14 packet error check register pecr read-only 0x00000000 0x18 status register sr read-only 0x00000002 0x1c interrupt enable register ier write-only 0x00000000 0x20 interrupt disable register idr write-only 0x00000000 0x24 interrupt mask register imr read-only 0x00000000 0x28 status clear register scr write-only 0x00000000 0x2c parameter register pr read-only (1) 0x30 version register vr read-only (1)
529 32099a?avr32?06/09 at32uc3l 23.9.1 control register name: cr access type: read/write offset :0x00 reset value: 0x00000000 ? tenbit: ten bit address match write this bit to zero to disable ten bit address match. write this bit to one to enable ten bit address match. ? adr: slave address slave address used in slave address match. bits 9: 0 are used if in 10-bit mode, bits 6:0 otherwise. ? soam: stretch clock on address match writing this bit to zero will not strech bus clock after address match. writing this bit to one will strech bus clock after address match. ? cup: nbytes count up writing this bit to zero causes nbytes to count down (decrement) per byte transferred. writing this bit to one causes nbytes to count up (increment) per byte transferred. ? ack: slave receiver data phase ack value writing this bit to zero causes a low value to be returned in the ack cycle of the data phase in slave receiver mode. writing this bit to one causes a high value to be returned in the ack cycle of the data phase in slave receiver mode. ? pecen: packet error checking enable writing this bit to zero disables smbus pec (crc) generation and check. writing this bit to one enables smbus pec (crc) generation and check. ? smhh: smbus host header writing this bit to zero causes twis not to acknowledge the smbus host header. writing this bit to one causes twis to acknowledge the smbus host header. ? smda: smbus default address writing this bit to zero causes twis not to acknowledge the smbus default address. writing this bit to one causes twis to acknowledge the smbus default address. ? smbalert: smbus alert writing this bit to zero causes twis to release the smbalert line and not to acknowledge the smbus alert response address (ara). writing this bit to zero causes twis to pull down the smbalert line and to acknowledge the smbus alert response address (ara). 31 30 29 28 27 26 25 24 -----tenbit adr[9:8] 23 22 21 20 19 18 17 16 adr[7:0] 15 14 13 12 11 10 9 8 - soam cup ack pecen smhh smda smbalert 76543210 swrst - - stren gcmatch smatch smen sen
530 32099a?avr32?06/09 at32uc3l ? swrst: software reset this bit will always read as 0. writing a zero to this bit has no effect. writing a one to this bit resets the twis. ? stren: clock stretch enable writing this bit to zero disables clock stretching if rhr/thr buffer full/empt y. may cause over/underrun. writing this bit to one enables clock stretching if rhr/thr buffer full/empty. ? gcmatch: general call address match writing this bit to zero causes twis no t to acknowledge the general call address. writing this bit to one causes twis to acknowledge the general call address. ? smatch: slave address match writing this bit to zero causes twis not to acknowledge the slave address. writing this bit to one causes twis to acknowledge the slave address. ? smen: smbus mode enable writing this bit to zero disables smbus mode. writing this bit to one enables smbus mode. ? sen: slave enable writing this bit to zero disables the slave interface. writing this bit to one enables the slave interface.
531 32099a?avr32?06/09 at32uc3l 23.9.2 nbytes register name: nbytes access type: read/write offset :0x04 reset value: 0x00000000 ? nbytes: number of bytes to transfer writing to this field updates the nbytes counter. can also be r ead to to learn the progress of the transfer. can be incremented or decremented automatically by hardware. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - 76543210 nbytes
532 32099a?avr32?06/09 at32uc3l 23.9.3 timing register name: tr access type: read/write offset :0x08 reset value: 0x00000000 ? exp: clock prescaler used to specify how to prescale the smbus tlows counter. the counter is prescaled according to the following formula: ? sudat: data setup cycles non-prescaled clock cycles for data setup count. used to time t su_dat . data is driven sudat cycles after twck low detected. this timing is used for timing the ack/nak bits, and any data bits driven in slave transmitter mode. ? ttout: smbus ttimeout cycles prescaled clock cycles used to time smbus t timeout . ? tlows: smbus tlow:sext cycles prescaled clock cycles used to time smbus t low:sext . 31 30 29 28 27 26 25 24 exp - 23 22 21 20 19 18 17 16 sudat 15 14 13 12 11 10 9 8 ttout 76543210 tlows f prescaled f clkpb 2 exp 1 + () ----------------------- =
533 32099a?avr32?06/09 at32uc3l 23.9.4 receive holding register name: rhr access type: read-only offset :0x0c reset value: 0x00000000 ? rxdata: received data byte when the rxrdy bit in the status regist er (sr) is set, this field contains a byte received from the twi bus. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rxdata
534 32099a?avr32?06/09 at32uc3l 23.9.5 transmit holding register name: thr access type: write-only offset :0x10 reset value: 0x00000000 ? txdata: data byte to transmit write data to be transf erred on the twi bus here. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 txdata
535 32099a?avr32?06/09 at32uc3l 23.9.6 packet error check register name: pecr access type: read-only offset :0x14 reset value: 0x00000000 ? pec: calculated pec value the calculated pec value. updated automatical ly by hardware after each byte has been transferred. reset by hardware after a stop condition. provided if the user manu ally wishes to control when the pec byte is transmitted, or wishes to access the pec value for other reasons. in ordinary operation, the pec handling is done automatically by hardware. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 pec
536 32099a?avr32?06/09 at32uc3l 23.9.7 status register name: sr access type: read-only offset :0x18 reset value: 0x000000002 ? btf: byte transfer finished this bit is set when byte transfer has completed. this bit is cleared when the corresponding bit in scr is written to one. ? rep: repeated start received this bit is set when repeated start condition received. this bit is cleared when the corresponding bit in scr is written to one. ? sto: stop received this bit is set when stop condition received. this bit is cleared when the corresponding bit in scr is written to one. ? smbdam: smbus default address match this bit is set when received address matched smbus default address. this bit is cleared when the corresponding bit in scr is written to one. ? smbhhm: smbus host header address match this bit is set when received address matched smbus host header address. this bit is cleared when the corresponding bit in scr is written to one. ? smbalertm: smbus alert response address match this bit is set when received address matched smbus alert response address. this bit is cleared when the corresponding bit in scr is written to one. ? gcm: general call match this bit is set when received address matched general call address. this bit is cleared when the corresponding bit in scr is written to one. ? sam: slave address match this bit is set when received address matched slave address. this bit is cleared when the corresponding bit in scr is written to one. ? buserr: bus error this bit is set when a misplaced start or stop condition has occurred. this bit is cleared when the corresponding bit in scr is written to one. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 btf rep sto smbdam smbhhm smbalertm gcm sam 15 14 13 12 11 10 9 8 - buserr smbpecerr smbtout - - - nak 76 5 43210 orun urun tra - tcomp sen txrdy rxrdy
537 32099a?avr32?06/09 at32uc3l ? smbpecerr: smbus pec error this bit is set when smbus pec error has occurred. this bit is cleared when the corresponding bit in scr is written to one. ? smbtout: smbus timeout this bit is set when smbus timeout has occurred. this bit is cleared when the corresponding bit in scr is written to one. ? nak: nak received this bit is set when nak was received from master during slave transmitter operation. this bit is cleared when the corresponding bit in scr is written to one. ? orun: overrun this bit is set when overrun has occurred in slave receiver mode. can only occur if cr.stren=0. this bit is cleared when the corresponding bit in scr is written to one. ? urun: underrun this bit is set when underrun has occurred in slave transmitter mode. can only occur if cr.stren=0. this bit is cleared when the corresponding bit in scr is written to one. ? tra: transmitter mode 0: the slave is in slave receiver mode. 1: the slave is in slave transmitter mode. ? tcomp: transmis sion complete this bit is set when transmission is complete. set after receiving a stop after being addressed. this bit is cleared when the corresponding bit in scr is written to one. ? sen: slave enabled 0: the slave interface is disabled. 1: the slave interface is enabled. ? txrdy: tx buffer ready 0: the tx buffer is full and should not be written to. 1: the tx buffer is empty, and can accept new data. ? rxrdy: rx buffer ready 0: no rx data ready in rhr. 1: rx data is ready to be read from rhr.
538 32099a?avr32?06/09 at32uc3l 23.9.8 interrupt enable register name: ier access type: write-only offset :0x1c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 btf rep sto smbdam smbhhm smbalertm gcm sam 15 14 13 12 11 10 9 8 - buserr smbpecerr smbtout - - - nak 76 5 43210 orun urun - - tcomp - txrdy rxrdy
539 32099a?avr32?06/09 at32uc3l 23.9.9 interrupt disable register name: idr access type: write-only offset :0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 btf rep sto smbdam smbhhm smbalertm gcm sam 15 14 13 12 11 10 9 8 - buserr smbpecerr smbtout - - - nak 76 5 43210 orun urun - - tcomp - txrdy rxrdy
540 32099a?avr32?06/09 at32uc3l 23.9.10 interrupt mask register name: imr access type: read-only offset :0x24 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -- - ----- 23 22 21 20 19 18 17 16 btf rep sto smbdam smbhhm smbalertm gcm sam 15 14 13 12 11 10 9 8 - buserr smbpecerr smbtout - - - nak 76 5 43210 orun urun - - tcomp - txrdy rxrdy
541 32099a?avr32?06/09 at32uc3l 23.9.11 status clear register name: scr access type: read/write offset :0x28 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 btf rep sto smbdam smbhhm smbalertm gcm sam 15 14 13 12 11 10 9 8 - buserr smbpecerr smbtout - - - nak 76 5 43210 orun urun - - tcomp - - -
542 32099a?avr32?06/09 at32uc3l 23.9.12 parameter register name: pr access type: read-only offset :0x2c reset value: 0x00000000 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
543 32099a?avr32?06/09 at32uc3l 23.9.13 version register (vr) name: vr access type: read-only offset: 0x30 reset value: device-specific ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 ---- version [11:8] 76543210 version [7:0]
544 32099a?avr32?06/09 at32uc3l
545 32099a?avr32?06/09 at32uc3l 23.10 module configuration the specific configuration for each twis instance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 23-7. module clock name module name clock name twis0 clk_twis0 twis1 clk_twis1 table 23-8. register reset values register reset value version 0x00000112 parameter 0x00000000
546 32099a?avr32?06/09 at32uc3l 24. basic pulse width modula tion controller (pwma) rev 1.0.1.0 24.1 features ? left-aligned non-inverted 8-bit pwm ? common 8-bit timebase counter ? asynchronous clock source supported ? spread-spectrum counter to allow a constantly varying duty cycle ? separate 8-bit duty cycle register per channel ? synchronized channel updates ? no glitches when changing the duty cycles ? interlinked operation supported ? multiple channels can be updated with the same duty cycle value at a time ? up to four channels can be updated with different duty cycle values at a time ? interrupt on pwm timebase overflow ? incoming peripheral events supported ? pre-defined channels support incoming (i ncrease/decrease) peripheral events from the peripheral event system ? increase event will increase the duty cycle by one ? decrease event will decrease the duty cycle by one ? one output peripheral event supported ? connected to channel 0 and ass erted when the common timeb ase counter is equal to the programmed duty cycle for channel 0 ? output pwm waveform for each channel ? open drain driving on selected pins for 5v pwm operation 24.2 overview the basic pulse width modulation controller (pwma) controls several pulse width modulation (pwm) channels. the number of channels is specif ic to the device. each channel controls one square output pwm waveform. characteristics of the output pwm waveforms such as period and duty cycle are configured through the user interface. all user interface registers are mapped on the peripheral bus. the duty cycle value for each channel can be set independently, while the period is determined by a common timebase counter (tc). the timebase for the counter is selected by using the allo- cated asynchronous generic clock (gclk). the user interface for the pwma contains handshake and synchronizing logic to ensure that no glitches occur on the output pwm wave- forms while changing the duty cycle values. pwma duty cycle values can be changed using two approaches, either an interlinked single- value mode or an interlinked multi-value mode. in the interlinked single-value mode, any set of channels, up to 32 channels, can be updated simultaneously with the same value while the other channels remain unchanged. in the interlinked multi-value mode, up to 4 selected channels can be updated with 4 different values while the other channels remain unchanged. some pins can be driven in open drain mode, allowing the pwma to generate a 5v waveform using an external pullup resistor.
547 32099a?avr32?06/09 at32uc3l 24.3 block diagram figure 24-1. pwma block diagram 24.4 i/o lines description each channel outputs one pwm waveform on one external i/o line. 24.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. pwm blocks channel m channel 1 channel 0 duty cycle register comp pwma[m:0] tclr interrupt handling irq pb top timebase counter spread adjust tofl busy channel_0 clk_pwma gclk domain pb clock domain spread spectrum counter sync gclk etv control duty cycle channel select table 24-1. i/o line description pin name pin description type pwma[n] output pwm waveform for one channel n output pwmmod[n] output pwm waveform for one channel n, open drain mode output
548 32099a?avr32?06/09 at32uc3l 24.5.1 i/o lines the pins used for interfacing the pwma may be multiplexed with i/o controller lines. the pro- grammer must first program the i/o controller to assign the desired pwma pins to their peripheral function. it is only required to enable the pwma outputs actually in use. 24.5.2 power management if the cpu enters a sleep mode that disables clocks used by the pwma, the pwma will stop functioning and resume operation after the system wakes up from sleep mode. 24.5.3 clocks the clock for the pwma bus interface (clk_pwma) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to dis- able the pwma before disabling the clock, to avoid freezing the pwma in an undefined state. additionally, the pwma depends on a dedicated ge neric clock (gclk). the gclk can be set to a wide range of frequencies and clock sources and must be enabled in the system control interface (scif) before the pwma can be used. 24.5.4 interrupts the pwma interrupt request lines are connected to the interrupt controller. using the pwma interrupts requires the interrupt controller to be programmed first. 24.5.5 peripheral events the pwma peripheral events are connected via the peripheral event system. refer to the peripheral event system chapter for details. 24.5.6 debug operation when an external debugger forces the cpu into debug mode, the pwma continues normal operation. if the pwma is configured in a way t hat requires it to be periodically serviced by the cpu through interrupts, improper operation or data loss may result during debugging. 24.6 functional description the pwma embeds a number of pwm channel submodules, each providing an output pwm waveform. each pwm channel contains a duty cycle register and a comparator. a common timebase counter for all channels determines the frequency and the period for all the pwm waveforms. 24.6.1 enabling the pwma once the gclk has been enabled, the pwma is enabled by writing a one to the en bit in the control register (cr). 24.6.2 timebase counter the top value of the timebase counter defines the period of the pwma output waveform. the timebase counter starts at zero when the pwma is enabled and counts upwards until it reaches its effective top value (etv). the effective top value is defined by specifying the desired number of gclk clock cycles in the top field of cr (cr.top) in normal operation (cr.spread is
549 32099a?avr32?06/09 at32uc3l zero). when the timebase counter reaches its effective top value, it restarts counting from zero. the period of the pwma output waveform is then: the timebase counter can be reset by writing a one to the timebase clear bit in cr (cr.tclr). note that this can cause a glitch to the output pwm waveforms in use. 24.6.3 spread spectrum counter the spread spectrum counter allows the generati on of constantly varying duty cycles on the out- put pwm waveforms. this is achieved by varying the effective top value of the timebase counter in a range defined by the spread spectrum counter value. when cr.spread is not zero, the spread spectrum counter is enabled. its range is defined by cr.spread. it starts to count from -cr.spr ead when the pwma is enabled or after reset and counts upwards. when it reaches cr.spread, it restarts to count from -cr.spread again. the spread spectrum coun ter will cause the effective top value (etv) to vary from top- spread to top+spread. figure 24-2 on page 549 illustrates this. this leads to a constantly varying duty cycle on the pwm output waveforms though the duty cycle values stored are unchanged. figure 24-2. pwma adjusting top value for timebase counter 24.6.3.1 special considerations the maximum value of the timebase counter is 255. if spread is written to a value that will cause the etv to exceed this va lue, the spread spectrum counte r?s range will be limited to pre- vent the timebase counter to exceed its maximum value. if spread is written to a value causing (top- spread) to be below zero, the spread specturm counter?s range will be limited to prevent the timebase c ounter to coun t below zero. in both cases, the spread valu e read from the control register will be the same value as writ- ten to the spread field. t pwma etv 1 + () t gclk ? = 0x0 0xff duty cycle -spread spread top adjusting top value range for the timerbase counter
550 32099a?avr32?06/09 at32uc3l when writing a one to cr.tclr, the timebase c ounter and the spread spectrum counter are reset at their lower limit values and the effective top value of the timebase counter will also be reset. 24.6.4 duty cycle and waveform properties each pwm channel has its own duty cycle value (dcv) which is write-only and cannot be read out. the duty cycle value can be changed in two approaches as described in section24.6.5 . when the duty cycle value is zero, the pwm output is zero. otherwise, the pwm output is set when the timebase counter is zero, and cleared when the timebase counter reaches the duty cycle value. this is summarized as: note that when increasing the duty cycle value for one channel from 0 to 1, the number of gclk cycles when the pwm waveform is high will jump from 0 to 2. when incrementing the duty cycle value by one for any other values, the number of gclk cycle when the waveform is high will increase by one. this is summarized in table 24-2 . every other output pwm waveform toggles on the negative edge of the gclk instead of the positive edge. this is to avoid too many i/o toggling simultaneously on the output i/o lines. 24.6.5 updating duty cycle values 24.6.5.1 interlinked single value pwm operation the pwm channels can be interlinked to allow multiple channels to be updated simultaneously with the same duty cycle value. this value must be written to the interlinked single value duty (isduty) register. each channel has a corresponding enabling bit in the interlinked single value channel set (ischset) register(s). when a bit is written to one in the ischset register, the duty cycle register for the corresponding channel will be updated with the value stored in the isduty register. it can only be updated when t he ready bit in the status register (sr.ready) is one, indicating that the pwma is ready for writing. figure 24-3 on page 551 shows the writing procedure. it is thus possible to update the duty cycle values for up to 32 pwm channels within one ischset register at a time. table 24-2. pmw waveform duty cycles duty cycle value #clock cycles when waveform is high #clock cycles when waveform is low 00 etv+1 12 etv-1 23 etv-2 ... ... ... etv-1 etv 1 etv etv+1 0 pwm waveform = low when dcv 0 or tc dcv > = high when tc dcv and dcv 0 ? ? ?
551 32099a?avr32?06/09 at32uc3l figure 24-3. interlinked single value pwm operation flow 24.6.5.2 interlinked multip le value pwm operation the interlinked multip le value pwm operation allows up to four channels to be updated simulta- neously with different duty cycle values. these duty cycle values must be written to the imduty register. the index number of the four channels to be updated is written to the four sel fields in the interlinked multiple value channel select (imchsel) register (imchsel.sel). when the imchsel register is written, the values stored in the imduty register are synchronized to the duty cycle registers for the channe ls selected by the sel fields. figure 24-4 on page 551 shows the writing procedure. note that only writes to the implemented channels will be ef fective. if one of the imchsel.sel fields points to a non-existing c hannel, the corresponding value in the imduty register will not be written. if the same channel is specified in multiple imchsel.sel fields, the channel will be updated with the value stored in the corresponding upper field of the imduty register. figure 24-4. interlinked multiple value pwm operation flow 24.6.6 open drain mode some pins can be used in open drain mode, allowing the pwma waveform to toggle between 0v and up to 5v on these pins. in this mode the pwma will drive th e pin to zero or leave the out- put open. an external pullup can be used to pull the pin up to the desired voltage. to enable open drain mode on a pin the pwmaod function must be selected instead of the pwma function in the i/o controller. please refer to the module configuration chapter for infor- mation about which pins are available in open drain mode. 24.6.7 synchronization both the timebase counter and the spread spectrum counter can be reset and the duty cycle registers can be written through the user interface of the module. this requires a synchroniza- tion between the pb and gclk clock domains, wh ich takes a few clock cycles of each clock domain. the busy bit in sr indicates when the synchronization is ongoing. writing to the mod- ule while the busy bit is set will re sult in discarding the new value. isduty ischset duty0 duty1 dutym ... write enable imduty imchsel duty0 duty1 dutym ... mux
552 32099a?avr32?06/09 at32uc3l note that the duty cycle regi sters will not be updated with the new values until the timebase counter reaches its top value, in order to avoid glitches. the busy bit in sr will always be set during this updating and synchronization period. 24.6.8 interrupts when the timebase counter overflows, the tim ebase overflow bit in the status register (sr.tofl) is set. if the corresponding bit in the interrupt mask register (imr) is set, an interrupt request will be generated. since the user needs to wait until the user inte rface is available between each write due to syn- chronization, a ready bit is provided in sr, which can be used to generate an interrupt request. the interrupt request will be generated if th e corresponding bit in imr is set. bits in imr are set by writing a one to the corresponding bit in the interrupt enable register (ier), and cleared by writing a one to the corresponding bit in the in terrupt disable register (idr). the interrupt request remains active until the corresponding bit in sr is cleared by writing a one to the corre- sponding bit in the status clear register (scr). 24.6.9 peripheral events 24.6.9.1 input peripheral events the pre-defined channels support input peripheral events from the peripheral event system. an increase event (event_incr) will increase the duty cycle val ue by one, and a decrease event (event_decr) will decrease the duty cycle value by one. if an increase event and a decrease event occur at the same time, the duty cycle value will not be changed. the number of channels supporting input peripheral events is device specific. please refer to the module configuration section at the end of this chapter for details. input peripheral events must be enabled by writ ing a one to the corresponding bit in the chanel event enable registers (cheers) before peripheral events can be used to control the duty cycle value. each bit in the register correspo nds to one channel, wh ere bit 0 corresponds to channel 0 and so on. both the increase and decrease events are enabled for the corresponding channel when a bit in the cheer register is set. 24.6.9.2 output peripheral event the pwma also supports one output peripheral event (event_ch0) to the peripheral event sys- tem. this output peripheral event is connec ted to channel 0 and will be asserted when the timebase counter reaches the duty cycle valu e for channel 0. this output event is always enabled.
553 32099a?avr32?06/09 at32uc3l 24.7 user interface note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. table 24-3. pwma register memory map offset register register name access reset 0x00 control register cr read/write 0x00000000 0x04 interlinked single value duty register isduty write-only 0x00000000 0x08 interlinked multiple value duty register imduty write-only 0x00000000 0x0c interlinked multiple value channel select imchsel write-only 0x00000000 0x10 interrupt enable register ier write-only 0x00000000 0x14 interrupt disable register idr write-only 0x00000000 0x18 interrupt mask register imr read-only 0x00000000 0x1c status register sr read-only 0x00000000 0x20 status clear register scr write-only 0x00000000 0x24 parameter register parameter read-only - (1) 0x28 version register version read-only - (1) 0x30+m*0x10 interlinked single value channel set m ischsetm write-only 0x00000000 0x38+m*0x10 channel event enable register m cheerm read/write 0x00000000
554 32099a?avr32?06/09 at32uc3l 24.7.1 control register name: cr access type: read/write offset :0x00 reset value: 0x00000000 ? spread: spread spectrum limit value the spread spectrum limit value, together with the top field, defines the range for the spread spectrum counter. it is introduc ed in order to achieve constant varying duty cycl es on the output pwm waveforms. refer to section24.6.3 for more information. ? top: timebase counter top value the top value for the timebase counter. the effective top value of the timebase count er is defined by both the top and the spread fields. refer to section24.6.2 for more information. ? tclr: timebase clear writing a zero to this bit has no effect. writing a one to this bit will clear the timebase counter. this bit is always read as zero. ? en: module enable 0: the pwma is disabled 1: the pwma is enabled 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - spread 15 14 13 12 11 10 9 8 top 76543210 ------tclren
555 32099a?avr32?06/09 at32uc3l 24.7.2 interlinked single value duty register name: isduty access type: write-only offset :0x04 reset value: 0x00000000 ? duty: duty cycle value the duty cycle value written to this field is written simultaneously to all channels selected in the ischset registers. if the value zero is written to duty all affected channels will be disabled. in this state the output waveform will be zero all the time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 duty
556 32099a?avr32?06/09 at32uc3l 24.7.3 interlinked multiple value duty register name: imduty access type: write-only offset :0x08 reset value: 0x00000000 ? dutyn: duty cycle the value written to duty field n will be written to the pwma channel selected by the corresponding sel field in the imchsel register. if the value zero is written to duty all affected channels will be disabled. in this state the output waveform will be zero all the time. 31 30 29 28 27 26 25 24 duty3 23 22 21 20 19 18 17 16 duty2 15 14 13 12 11 10 9 8 duty1 76543210 duty0
557 32099a?avr32?06/09 at32uc3l 24.7.4 interlinked multiple value channel select name: imchsel access type: write-only offset :0x0c reset value: 0x00000000 ? seln: channel select the duty cycle of the pwma channel seln will be updated with the value in the dutyn field of the imduty register when imchsel is written. if seln points to a non-i mplemented channel, the write will be discarded. note: the duty registers will be updated with the value stored in th e imduty register when the imchsel register is written. sync hro- nization takes place immeid ately when an imchsel register is written. the duty cycle register s will, however, not be updated until the synchronization is completed and the timebase c ounter reaches its top value in order to avoid glitches. 31 30 29 28 27 26 25 24 sel3 23 22 21 20 19 18 17 16 sel2 15 14 13 12 11 10 9 8 sel1 76543210 sel0
558 32099a?avr32?06/09 at32uc3l 24.7.5 interrupt enable register name: ier access type: write-only offset :0x10 reset value: 0x00000000 writing a zero to a bit in this register has no effect writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -----ready-tofl
559 32099a?avr32?06/09 at32uc3l 24.7.6 interrupt disable register name: idr access type: write-only offset :0x14 reset value: 0x00000000 writing a zero to a bit in this register has no effect writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -----ready-tofl
560 32099a?avr32?06/09 at32uc3l 24.7.7 interrupt mask register name: imr access type: read-only offset :0x18 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -----ready-tofl
561 32099a?avr32?06/09 at32uc3l 24.7.8 status register name: sr access type: read-only offset :0x1c reset value: 0x00000000 ? busy: interface busy this bit is automatically cleared when the interface is no longer busy. this bit is set when the user interface is busy and will not respond to new write operations. ? ready: interface ready this bit is cleared by writing a one to the corresponding bit in the scr register. this bit is set when the busy bit has a 1-to-0 transition. ? tofl: timebase overflow this bit is cleared by writing a one to corresponding bit in the scr register. this bit is set when the timebase counter has wrapped at its top value. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - busy ready - tofl
562 32099a?avr32?06/09 at32uc3l 24.7.9 status clear register name: scr access type: write-only offset :0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. this register always reads as zero. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 1 10 9 8 -------- 76543210 -----ready-tofl
563 32099a?avr32?06/09 at32uc3l 24.7.10 parameter register name: parameter access type: read-only offset :0x24 reset value: - ? channels: channels implemented this field contains the number of channels implemented on the device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 channels
564 32099a?avr32?06/09 at32uc3l 24.7.11 version register name: version access type: read-only offset :0x28 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 ---- version[11:8] 76543210 version[7:0]
565 32099a?avr32?06/09 at32uc3l 24.7.12 interlinked single value channel set name: ischsetm access type: write-only offset : 0x30+m*0x10 reset value: 0x00000000 ? set: single value channel set if the bit n in set is one, the duty cycle of pwma channel n will be updated with the va lue written to isduty. if more than one ischset register is present, ischset0 contro ls channels 31 to 0 and ischset1 controls channels 63 to 32. note: the duty registers will be updated with the value stored in the isduty register when any ischsetm register is written. syn - chronization takes place immeidately when an ischset register is written. the duty cycle r egisters will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches. 31 30 29 28 27 26 25 24 set 23 22 21 20 19 18 17 16 set 15 14 13 12 11 10 9 8 set 76543210 set
566 32099a?avr32?06/09 at32uc3l 24.7.13 channel event enable register name: cheerm access type: read/write offset : 0x38+m*0x10 reset value: 0x00000000 ? chee: channel event enable 0: the input peripheral event for the corresponding channel is disabled. 1: the input peripheral event for the corresponding channel is enabled. both increase and decrease events for channel n are enabled if bit n is one. if more than one cheer register is present, cheer0 controls channels 31-0 and cheer1 controls channels 64-32 and so on. 31 30 29 28 27 26 25 24 chee 23 22 21 20 19 18 17 16 chee 15 14 13 12 11 10 9 8 chee 76543210 chee
567 32099a?avr32?06/09 at32uc3l 24.8 module configuration the specific configuration for each pwma instan ce is listed in the following tables. the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 24-4. pwma configuration feature pwma number of pwm channels 36 channels supporting incoming peripheral events 0, 6, 8, 9, 11, 14, 19, and 20 pwma channels with open drain mode 21, 27, and 28 table 24-5. pwma clock name module name clock name pwma clk_pwma table 24-6. register reset values register reset value version 0x00000101 parameter 0x00000024
568 32099a?avr32?06/09 at32uc3l 25. timer/counter (tc) rev: 2.2.3.1.1 25.1 features ? three 16-bit timer counter channels ? a wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-conf igurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? internal interrupt signal ? two global registers that act on all three tc channels ? peripheral event input on all a lines in capture mode 25.2 overview the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the tc block has two global registers which act upon all three tc channels. the block control register (bcr) allows the th ree channels to be started simultaneously with the same instruction. the block mode register (bmr) defines the ex ternal clock inputs for each channel, allowing them to be chained.
569 32099a?avr32?06/09 at32uc3l 25.3 block diagram figure 25-1. tc block diagram 25.4 i/o lines description 25.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 25.5.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with i/o lines. the user must first program the i/o controller to assign the tc pins to their peripheral functions. i/o contr oller tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa1 interrupt controller clk0 clk1 clk2 a0 b0 a1 b1 a2 b2 timer count er tiob tioa tiob sync timer_clock1 tioa sync sync tioa tiob timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc1 xc0 xc0 xc2 xc1 xc0 xc1 xc2 timer/counter channel 2 timer/counter channel 1 timer/counter channel 0 tc1xc1s tc0xc0s tioa0 table 25-1. i/o lines description pin name description type clk0-clk2 external clock input input a0-a2 i/o line a input/output b0-b2 i/o line b input/output
570 32099a?avr32?06/09 at32uc3l when using the tioa lines as inputs the user must make sure that no peripheral events are gen- erated on the line. refer to the peripheral event system chapter for details. 25.5.2 power management if the cpu enters a sleep mode that disables cl ocks used by the tc, the tc will stop functioning and resume operation after the system wakes up from sleep mode. 25.5.3 clocks the clock for the tc bus interface (clk_tc) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the tc before disabling the clock, to avoid freezing the tc in an undefined state. 25.5.4 interrupts the tc interrupt request line is connected to the interrupt controller. using the tc interrupt requires the interrupt controller to be programmed first. 25.5.5 peripheral events the tc peripheral events are connected via the pe ripheral event system. refer to the periph- eral event system chapter for details. 25.5.6 debug operation the timer counter clocks are frozen du ring debug operation, unless the ocd system keeps peripherals running in debug operation. 25.6 functional description 25.6.1 tc description the three channels of the timer counter are independent and identical in operation. the regis- ters for channel programming are listed in figure 25-3 on page 585 . 25.6.1.1 channel i/o signals as described in figure 25-1 on page 569 , each channel has the following i/o signals. 25.6.1.2 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the counter overflow status bit in the channel n sta- tus register (srn.covfs) is set. table 25-2. channel i/o signals description block/channel sign al name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal
571 32099a?avr32?06/09 at32uc3l the current value of the counter is accessible in real time by reading the channel n counter value register (cvn). the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 25.6.1.3 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals a0, a1 or a2 for chaining by writing to the bmr register. see figure 25-2 on page 571 . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5. see the module configuration chapter for details about the connection of these clock sources. ? external clock signals: xc0, xc1 or xc2. see the module configuration chapter for details about the connection of these clock sources. this selection is made by the clock sele ction field in the channel n mode register (cmrn.tcclks). the selected clock can be inverted with the clock invert bit in cmrn (cmrn.clki). this allows counting on the opposite edges of the clock. the burst function allows the clock to be valida ted when an external signal is high. the burst signal selection field in the cmrn regi ster (cmrn.burst) defines this signal. note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the clk_tc period. the external clock frequency must be at least 2.5 times lower than the clk_tc. figure 25-2. clock selection timer_clock5 xc2 tcclks clki burst 1 selected clock xc1 xc0 timer_clock4 timer_clock3 timer_clock2 timer_clock1
572 32099a?avr32?06/09 at32uc3l 25.6.1.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 25-3 on page 572 . ? the clock can be enabled or disabled by the user by writing to the counter clock enable/disable command bits in the channel n clock contro l register (ccrn.clken and ccrn.clkdis). in capture mode it can be disabled by an rb load event if the counter clock disable with rb loading bit in cmrn is written to one (cmrn.ldbdis). in waveform mode, it can be disabled by an rc compare event if the counter clock disable with rc compare bit in cmrn is written to one (cmrn.cpcdis). when disabled, the start or the stop actions have no effect: only a clken command in ccrn can re-enable the clock. when the clock is enabled, the clock enabling status bit is set in srn (srn.clksta). ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. in capture mode the clock can be stopped by an rb load event if the counter clock stopped with rb loading bit in cmrn is written to one (cmrn.ldbstop). in waveform mode it can be stopped by an rc compare event if the counter clock stopped with rc compare bit in cmrn is written to one (cmrn.cpcstop). the start and the stop commands have effect only if the clock is enabled. figure 25-3. clock control 25.6.1.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode selection is done by writing to the wave bit in the ccrn register (ccrn.wave). in capture mode, tioa and tiob are configured as inputs. qs r s r q clksta clken clkdis stop event disable counter clock selected clock trigger event
573 32099a?avr32?06/09 at32uc3l in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 25.6.1.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: ? software trigger: each channel has a software trigger, available by writing a one to the software trigger command bi t in ccrn (ccrn.swtrg). ? sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing a one to the synchro command bit in the bcr register (bcr.sync). ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc value if the rc compare trigger enable bit in cmrn (cmrn.cpctrg) is written to one. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed to be one of the following si gnals: tiob, xc0, xc1, or xc2. this external event can then be programmed to perform a trigger by writing a one to the external event trig- ger enable bit in cmrn (cmrn.enetrg). if an external trigger is used, the duration of the pulses must be longer than the clk_tc period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 25.6.1.7 peripheral events on tioa inputs the tioa input lines are ored internally with peripheral events from the peripheral event sys- tem. to capture using events the user must ens ure that the corresponding pin functions for the tioa line are disabled. when capturing on the ex ternal tioa pin the user must ensure that no peripheral events are generated on this pin. 25.6.2 capture operating mode this mode is entered by writin g a zero to the cmrn.wave bit. capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 25-4 on page 575 shows the configuration of the tc channel when programmed in cap- ture mode. 25.6.2.1 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa.
574 32099a?avr32?06/09 at32uc3l the ra loading selection field in cmrn (cmrn.ldra) defines the tioa edge for the loading of the ra register, and the rb loading selection fi eld in cmrn (cmrn.ldrb) defines the tioa edge for the loading of the rb register. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the load overrun status bit in srn (srn.lovrs). in this case, the old value is overwritten. 25.6.2.2 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the tioa or tiob external trigger selection bit in cmrn (cmrn.abetrg) selects tioa or tiob input signal as an external trigger. the external trigger edge selection bit in cmrn (cmrn.etredg) defines the edge (rising, falling or both) detected to generate an external trig- ger. if cmrn.etrgedg is zero (none), the external trigger is disabled.
575 32099a?avr32?06/09 at32uc3l figure 25-4. capture mode timer_clock1 xc 0 xc 1 xc 2 tcclks clki qs r s r q clksta clken clkdis burst tiob capture register a compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg imr trig ldrbs ldras etrgs sr lovrs covfs sync 1 mtiob tioa mtioa l dra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int ed g e det ect or ldrb clk ovf reset timer/counter channel edge detector edge detector capture register b register c timer_clock2 timer_clock3 timer_clock4 timer_clock5
576 32099a?avr32?06/09 at32uc3l 25.6.3 waveform operating mode waveform operating mode is entered by writing a one to the cmrn.wave bit. in waveform operating mode the tc channel generates one or two pwm signals with the same frequency and independently programmable duty cy cles, or generates different types of one- shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event. figure 25-5 on page 577 shows the configuration of the tc channel when programmed in waveform operating mode. 25.6.3.1 waveform selection depending on the waveform se lection field in cmrn (cmrn. wavsel), the behavior of cvn varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
577 32099a?avr32?06/09 at32uc3l figure 25-5. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a compare rc = cpcstop 16-bit counter eevt eev t e d g sync swtrg en etr g wavsel imr tr i g acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs sr cpcs cpbs clk ovf reset output contr oller o utput cont r oller int 1 ed g e det ect o r timer/counter channel timer_clock1 xc 0 xc 1 xc 2 wavsel register b register c compare rb = compare ra = timer_clock2 timer_clock3 timer_clock4 timer_clock5
578 32099a?avr32?06/09 at32uc3l 25.6.3.2 wavsel = 0 when cmrn.wavsel is zero, the value of cv n is incremented fr om 0 to 0xffff. once 0xffff has been reached, the value of cvn is re set. incrementation of cvn starts again and the cycle continues. see figure 25-6 on page 578 . an external event trigger or a software trigger can reset the value of cvn. it is important to note that the trigger may occur at any time. see figure 25-7 on page 579 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cmrn.cpcstop = 1) and/or disable the counter clock (cmrn.cpcdis = 1). figure 25-6. wavsel= 0 without trigger time counter value rc rb ra tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
579 32099a?avr32?06/09 at32uc3l figure 25-7. wavsel= 0 with trigger 25.6.3.3 wavsel = 2 when cmrn.wavsel is two, the value of cvn is incremented from zero to the value of rc, then automatically reset on a rc compare. once the value of cvn has been reset, it is then incremented and so on. see figure 25-8 on page 580 . it is important to note that cvn can be reset at any time by an external event or a software trig- ger if both are programmed correctly. see figure 25-9 on page 580 . in addition, rc compare can stop the counter clock (cmrn.cpcstop) and/or disable the counter clock (cmrn.cpcdis = 1). time counter value rc rb ra tiob tioa counter cleared by co mpare match with 0xffff 0xffff waveform examples counter cleared by trigger
580 32099a?avr32?06/09 at32uc3l figure 25-8. wavsel = 2 without trigger figure 25-9. wavsel = 2 with trigger 25.6.3.4 wavsel = 1 when cmrn.wavsel is one, the value of cvn is incremented from 0 to 0xffff. once 0xffff is reached, the value of cvn is decremented to 0, then re-incremented to 0xffff and so on. see figure 25-10 on page 581 . time counter value rc rb ra tiob tioa counter cleared by compare match with rc 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
581 32099a?avr32?06/09 at32uc3l a trigger such as an external event or a software trigger can modify cvn at any time. if a trigger occurs while cvn is incrementing, cvn then decrements. if a trigger is received while cvn is decrementing, cvn then increments. see figure 25-11 on page 581 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cmrn.cpcstop = 1) and/or dis- able the counter clock (cmrn.cpcdis = 1). figure 25-10. wavsel = 1 without trigger figure 25-11. wavsel = 1 with trigger time counter value rc rb ra tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger rc rb ra counter incremented by trigger
582 32099a?avr32?06/09 at32uc3l 25.6.3.5 wavsel = 3 when cmrn.wavsel is three, the value of cvn is incremented from ze ro to rc. once rc is reached, the value of cvn is decremented to zero, then re-incremented to rc and so on. see figure 25-12 on page 582 . a trigger such as an external event or a software trigger can modify cvn at any time. if a trigger occurs while cvn is incrementing, cvn then decrements. if a trigger is received while cvn is decrementing, cvn then increments. see figure 25-13 on page 583 . rc compare can stop the counter clock (cmrn.cp cstop = 1) and/or disable the counter clock (cmrn.cpcdis = 1). figure 25-12. wavsel = 3 without trigger time counter value rc rb ra tiob tioa counter cleared by compare match with rc 0xffff waveform examples
583 32099a?avr32?06/09 at32uc3l figure 25-13. wavsel = 3 with trigger 25.6.3.6 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the external event selection field in cmrn (cmrn.eevt) selects the external trigger. the external event edge selection field in cmrn (cmrn.eevtedg) defines the trigger edge for each of the possible external triggers (rising, fa lling or both). if cmrn.eevtedg is written to zero, no external event is defined. if tiob is defined as an ex ternal event signal (cmrn.eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by writing a one to the cmrn.enetrg bit. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the cmrn.wavsel field. 25.6.3.7 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: ? software trigger ? external event ? rc compare ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the following fields in cmrn: ? rc compare effect on tiob (cmrn.bcpc) time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples rc rb ra counter decremented by trigger counter incremented by trigger
584 32099a?avr32?06/09 at32uc3l ? rb compare effect on tiob (cmrn.bcpb) ? rc compare effect on tioa (cmrn.acpc) ? ra compare effect on tioa (cmrn.acpa)
585 32099a?avr32?06/09 at32uc3l 25.7 user interface notes: 1. read-only if cmrn.wave is zero table 25-3. tc register memory map offset register register name access reset 0x00 channel 0 control register ccr0 write-only 0x00000000 0x04 channel 0 mode register cmr0 read/write 0x00000000 0x10 channel 0 counter value cv0 read-only 0x00000000 0x14 channel 0 register a ra0 read/write (1) 0x00000000 0x18 channel 0 register b rb0 read/write (1) 0x00000000 0x1c channel 0 register c rc0 read/write 0x00000000 0x20 channel 0 status register sr0 read-only 00x00000000 0x24 interrupt enable register ier0 write-only 0x00000000 0x28 channel 0 interrupt disable register idr0 write-only 0x00000000 0x2c channel 0 interrupt mask register imr0 read-only 0x00000000 0x40 channel 1 control register ccr1 write-only 0x00000000 0x44 channel 1 mode register cmr1 read/write 0x00000000 0x50 channel 1 counter value cv1 read-only 0x00000000 0x54 channel 1 register a ra1 read/write (1) 0x00000000 0x58 channel 1 register b rb1 read/write (1) 0x00000000 0x5c channel 1 register c rc1 read/write 0x00000000 0x60 channel 1 status register sr1 read-only 0x00000000 0x64 channel 1 interrupt enable register ier1 write-only 0x00000000 0x68 channel 1 interrupt disable register idr1 write-only 0x00000000 0x6c channel 1 interrupt mask register imr1 read-only 0x00000000 0x80 channel 2 control register ccr2 write-only 0x00000000 0x84 channel 2 mode register cmr2 read/write 0x00000000 0x90 channel 2 counter value cv2 read-only 0x00000000 0x94 channel 2 register a ra2 read/write (1) 0x00000000 0x98 channel 2 register b rb2 read/write (1) 0x00000000 0x9c channel 2 register c rc2 read/write 0x00000000 0xa0 channel 2 status register sr2 read-only 0x00000000 0xa4 channel 2 interrupt enable register ier2 write-only 0x00000000 0xa8 channel 2 interrupt disable register idr2 write-only 0x00000000 0xac channel 2 interrupt mask register imr2 read-only 0x00000000 0xc0 block control register bcr write-only 0x00000000 0xc4 block mode register bmr read/write 0x00000000
586 32099a?avr32?06/09 at32uc3l 25.7.1 channel control register name: ccr access type: write-only offset: 0x00 + n * 0x40 reset value: 0x00000000 ? swtrg: software trigger command 1: writing a one to this bit will perform a software tr igger: the counter is reset and the clock is started. 0: writing a zero to this bit has no effect. ? clkdis: counter cl ock disable command 1: writing a one to this bit will disable the clock. 0: writing a zero to this bit has no effect. ? clken: counter clock enable command 1: writing a one to this bit will enab le the clock if clkdis is not one. 0: writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - - swtrg clkdis clken
587 32099a?avr32?06/09 at32uc3l 25.7.2 channel mode register: capture mode name: cmr access type: read/write offset: 0x04 + n * 0x40 reset value: 0x00000000 ? ldrb: rb loading selection ? ldra: ra loading selection ?wave 1: capture mode is disabled (waveform mode is enabled). 0: capture mode is enabled. ? cpctrg: rc compare trigger enable 1: rc compare resets the counter and starts the counter clock. 0: rc compare has no effect on the counter and its clock. ? abetrg: tioa or tiob external trigger selection 1: tioa is used as an external trigger. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg - - - abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks ldrb edge 0 none 1 rising edge of tioa 2 falling edge of tioa 3 each edge of tioa ldra edge 0 none 1 rising edge of tioa 2 falling edge of tioa 3 each edge of tioa
588 32099a?avr32?06/09 at32uc3l 0: tiob is used as an external trigger. ? etrgedg: external trigger edge selection ? ldbdis: counter clock disable with rb loading 1: counter clock is disabled when rb loading occurs. 0: counter clock is not disabled when rb loading occurs. ? ldbstop: counter clock stopped with rb loading 1: counter clock is stopped when rb loading occurs. 0: counter clock is not stopped when rb loading occurs. ? burst: burst signal selection ? clki: clock invert 1: the counter is incremented on falling edge of the clock. 0: the counter is incremented on rising edge of the clock. ? tcclks: clock selection etrgedg edge 0 none 1 rising edge 2 falling edge 3 each edge burst burst signal selection 0 the clock is not gated by an external signal 1 xc0 is anded with the selected clock 2 xc1 is anded with the selected clock 3 xc2 is anded with the selected clock tcclks clock selected 0timer_clock1 1timer_clock2 2timer_clock3 3timer_clock4 4timer_clock5 5xc0 6xc1 7xc2
589 32099a?avr32?06/09 at32uc3l 25.7.3 channel mode register: waveform mode name: cmr access type: read/write offset: 0x04 + n * 0x40 reset value: 0x00000000 ? bswtrg: software trigger effect on tiob ? beevt: external event effect on tiob 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks bswtrg effect 0 none 1set 2clear 3 toggle beevt effect 0 none 1set 2clear 3 toggle
590 32099a?avr32?06/09 at32uc3l ? bcpc: rc compare effect on tiob ? bcpb: rb compare effect on tiob ? aswtrg: software trigger effect on tioa ? aeevt: external event effect on tioa ? acpc: rc compare effect on tioa bcpc effect 0 none 1set 2clear 3 toggle bcpb effect 0 none 1set 2clear 3 toggle aswtrg effect 0 none 1set 2clear 3 toggle aeevt effect 0 none 1set 2clear 3 toggle acpc effect 0 none 1set 2clear 3 toggle
591 32099a?avr32?06/09 at32uc3l ? acpa: ra compare effect on tioa ?wave 1: waveform mode is enabled. 0: waveform mode is disabled (capture mode is enabled). ? wavsel: waveform selection ? enetrg: external event trigger enable 1: the external event resets the counter and starts the counter clock. 0: the external event has no effect on the counter and its clock. in this case, the selected external event only controls the t ioa output. ? eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is conf igured as an input and no longer generates waveforms and subse- quently no irqs . ? eevtedg: external ev ent edge selection ? cpcdis: counter clock disable with rc compare 1: counter clock is disabled when counter reaches rc. 0: counter clock is not disabled when counter reaches rc. ? cpcstop: counter clock stopped with rc compare 1: counter clock is stopped when counter reaches rc. acpa effect 0 none 1set 2clear 3 toggle wavsel effect 0 up mode without automatic trigger on rc compare 1 updown mode without automat ic trigger on rc compare 2 up mode with automatic trigger on rc compare 3 updown mode with automatic trigger on rc compare eevt signal selected as exte rnal event tiob direction 0 tiob input (1) 1 xc0 output 2 xc1 output 3 xc2 output eevtedg edge 0none 1 rising edge 2 falling edge 3 each edge
592 32099a?avr32?06/09 at32uc3l 0: counter clock is not stopped when counter reaches rc. ? burst: burst signal selection ? clki: clock invert 1: counter is incremented on falling edge of the clock. 0: counter is incremented on rising edge of the clock. ? tcclks: clock selection burst burst signal selection 0 the clock is not gated by an external signal. 1 xc0 is anded with the selected clock. 2 xc1 is anded with the selected clock. 3 xc2 is anded with the selected clock. tcclks clock selected 0timer_clock1 1timer_clock2 2timer_clock3 3timer_clock4 4timer_clock5 5xc0 6xc1 7xc2
593 32099a?avr32?06/09 at32uc3l 25.7.4 channel counter value register name: cv access type: read-only offset: 0x10 + n * 0x40 reset value: 0x00000000 ?cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 cv[15:8] 76543210 cv[7:0]
594 32099a?avr32?06/09 at32uc3l 25.7.5 channel register a name: ra access type: read-only if cmrn.wave = 0, read/write if cmrn.wave = 1 offset: 0x14 + n * 0x40 reset value: 0x00000000 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ra[15:8] 76543210 ra[7:0]
595 32099a?avr32?06/09 at32uc3l 25.7.6 channel register b name: rb access type: read-only if cmrn.wave = 0, read/write if cmrn.wave = 1 offset: 0x18 + n * 0x40 reset value: 0x00000000 ? rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 rb[15:8] 76543210 rb[7:0]
596 32099a?avr32?06/09 at32uc3l 25.7.7 channel register c name: rc access type: read/write offset: 0x1c + n * 0x40 reset value: 0x00000000 ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 rc[15:8] 76543210 rc[7:0]
597 32099a?avr32?06/09 at32uc3l 25.7.8 channel status register name: sr access type: read-only offset: 0x20 + n * 0x40 reset value: 0x00000000 note: reading the status register will also clear th e interrupt bit for the co rresponding interrupts. ? mtiob: tiob mirror 1: tiob is high. if cmrn.wave is zero, this means that tiob pi n is high. if cmrn.wave is one, this means that tiob is driven high. 0: tiob is low. if cmrn.wave is zero, this means that tiob pi n is low. if cmrn.wave is one, this means that tiob is driven low. ? mtioa: tioa mirror 1: tioa is high. if cmrn.wave is zero, this means that tioa pin is high. if cmrn.wave is one, th is means that tioa is driven high. 0: tioa is low. if cmrn.wave is zero, this means that tioa pin is low. if cmrn.wave is one, this means that tioa is driven low. ? clksta: clock enabling status 1: this bit is set when the clock is enabled. 0: this bit is cleared when the clock is disabled. ? etrgs: external trigger status 1: this bit is set when an external trigger has occurred. 0: this bit is cleared when the sr register is read. ? ldrbs: rb loading status 1: this bit is set when an rb load has occurred and cmrn.wave is zero. 0: this bit is cleared when the sr register is read. ? ldras: ra loading status 1: this bit is set when an ra load has occurred and cmrn.wave is zero. 0: this bit is cleared when the sr register is read. ? cpcs: rc compare status 1: this bit is set when an rc compare has occurred. 0: this bit is cleared when the sr register is read. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - - mtiob mtioa clksta 15 14 13 12 11 10 9 8 -------- 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
598 32099a?avr32?06/09 at32uc3l ? cpbs: rb compare status 1: this bit is set when an rb compare has occurred and cmrn.wave is one. 0: this bit is cleared when the sr register is read. ? cpas: ra compare status 1: this bit is set when an ra compare has occurred and cmrn.wave is one. 0: this bit is cleared when the sr register is read. ? lovrs: load overrun status 1: this bit is set when ra or rb have been loaded at l east twice without any read of the corresponding register and cmrn.wave is zero. 0: this bit is cleared when the sr register is read. ? covfs: counter overflow status 1: this bit is set when a counter overflow has occurred. 0: this bit is cleared when the sr register is read.
599 32099a?avr32?06/09 at32uc3l 25.7.9 channel interrupt enable register name: ier access type: write-only offset: 0x24 + n * 0x40 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
600 32099a?avr32?06/09 at32uc3l 25.7.10 channel interrupt disable register name: idr access type: write-only offset: 0x28 + n * 0x40 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
601 32099a?avr32?06/09 at32uc3l 25.7.11 channel interrupt mask register name: imr access type: read-only offset: 0x2c + n * 0x40 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
602 32099a?avr32?06/09 at32uc3l 25.7.12 block control register name: bcr access type: write-only offset: 0xc0 reset value: 0x00000000 ? sync: synchro command 1: writing a one to this bit asserts the sync signal which generates a software trigger simultaneously for each of the channels . 0: writing a zero to this bit has no effect. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------sync
603 32099a?avr32?06/09 at32uc3l 25.7.13 block mode register name: bmr access type: read/write offset: 0xc4 reset value: 0x00000000 ? tc2xc2s: external clock signal 2 selection ? tc1xc1s: external clock signal 1 selection ? tc0xc0s: external cloc k signal 0 selection 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - tc2xc2s tc1xc1s tc0xc0s tc2xc2s signal connected to xc2 0tclk2 1none 2tioa0 3tioa1 tc1xc1s signal connected to xc1 0tclk1 1none 2tioa0 3tioa2 tc0xc0s signal connected to xc0 0tclk0
604 32099a?avr32?06/09 at32uc3l 1none 2tioa1 3tioa2
605 32099a?avr32?06/09 at32uc3l 25.8 module configuration 25.8.1 clock connections each timer/counter channel can independently select an internal or external clock source for its counter: table 25-4. timer/counter clock connections module source name connection tc0 internal timer_clock1 32 khz oscillator clock (clk_32k) timer_clock2 pba clock / 2 timer_clock3 pba clock / 8 timer_clock4 pba clock / 32 timer_clock5 pba clock / 128 external xc0 see table 3-1 on page 8 xc1 xc2 tc1 internal timer_clock1 32 khz oscillator clock (clk_32k) timer_clock2 pba clock / 2 timer_clock3 pba clock / 8 timer_clock4 pba clock / 32 timer_clock5 pba clock / 128 external xc0 see table 3-1 on page 8 xc1 xc2 tc2 internal timer_clock1 32 khz oscillator clock (clk_32k) timer_clock2 pba clock / 2 timer_clock3 pba clock / 8 timer_clock4 pba clock / 32 timer_clock5 pba clock / 128 external xc0 see table 3-1 on page 8 xc1 xc2
606 32099a?avr32?06/09 at32uc3l 26. adc interface (adcifb) rev.:1.0.1.0 26.1 features ? multi-channel analog-to-digital converter with up to 12-bit resolution ? enhanced resolution mode ? 11-bit resolution obtained by interpolating 4 samples ? 12-bit resolution obtained by interpolating 16 samples ? pseudorandom noise generator used for enhanced resolution mode ? glueless interface with resisti ve touch screen panel, allowing ? touch screen position measurement ? pen detection and pen loss detection ? integrated enhanced sequencer ? adc mode ?touch screen mode ? numerous trigger sources ? software ? embedded 16-bit timer for periodic trigger ? pen detect trigger ? continuous trigger ? external trigger, rising, falling or any-edge trigger ? peripheral event trigger ? adc sleep mode for low power adc applications ? programmable adc timings ? programmable adc clock ? programmable startup time 26.2 overview the adc interface (adcifb) converts analog input voltages to digital values. the adcifb is based on a successive approximation register (sar) 10-bit analog-to-digital converter (adc). the conversions extend from 0v to advref. the adcifb supports 8-bit, 10-bit, 11-bit, or 12-bit resolution mode, and conversion results are reported in a common register for all channels. the 11-bit and 12-bit resolution modes are obtained by interpolating multiple samples to acquire better accuracy. for 11-bit mode 4 samples are used, which gives an effective sample rate of 1/4 of the actual sample frequency. for 12-bit mode 16 samples are used, giving a effective sample rate of 1/16 of actual. this arrangement allows conversion speed to be traded for better accuracy. conversions can be started for all enabled channels, either by a software trigger, by detection of a level change on the external trigger pin (adtrg), or by an integrated programmable timer. when the touch screen adc mode is enabled, an integrated sequencer automatically config- ures the pad control signals and performs touch screen conversions. the adcifb also integrates an adc sleep mode, a pen-detect mode, and an analog compare mode, and connects with one peripheral dma controller channel. these features reduce both power consumption and processor intervention.
607 32099a?avr32?06/09 at32uc3l 26.3 block diagram figure 26-1. adcifb block diagram interrupt request adtrg vddana advref trigger adc control logic successive approximation register analog-to-digital converter timer user interface peripheral bus ad0 ad1 ad3 adn ad2 touch screen sequencer clk_adcifb .... analog multiplexer adcifb pseudorandom noise generator rnd dp0 dp1 dma request i/o controller
608 32099a?avr32?06/09 at32uc3l 26.4 i/o lines description 26.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 26.5.1 i/o lines the analog input pins can be multiplexed with i/o controller lines. the user must make sure the i/o controller is configured correctly to allow the adcifb access to the ad pins before the adcifb is instructed to start converting data. if the user fails to do this the converted data may be wrong. the number of analog inputs is device dependent, please refer to the adcifb module configu- ration chapter for the number of available ad inputs on the current device. the vddana and advref pins must be connecte d correctly prior to using the adcifb. failing to do so will result in invalid a dc operation. see the electrical c haracteristics chap ter for details. if the adtrg, rnd, dp0, and dp1 pins are to be used in the application, the user must config- ure the i/o controller to assign the needed pins to the adcifb function. 26.5.2 power management if the cpu enters a sleep mode that disables clocks used by the adcifb, the adcifb will stop functioning and resume operation after the system wakes up from sleep mode. if the periperhal event system is configur ed to send asynchronous peripheral events to the adcifb and the clock used by the adcifb is stopped, a local and tem porary clock will automat- ically be requested so the event can be processed. refer to section 26.6.14 , section 26.6.13 , and the peripheral event system chapter for details. before entering a sleep mode where the clock to the adcifb is stopped, make sure the analog- to-digital conver ter cell is put in an inactive state. refer to section 26.6.14 for more information. 26.5.3 clocks the clock for the adcifb bus interface (clk _adcifb) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the adcifb before disabling the clock, to avoid freezing the adcifb in an undefined state. table 26-1. i/o lines description pin name description type vddana analog power supply power advref reference voltage analog adtrg external trigger digital rnd a pseudorandom output digital dp0 drive pin 0 for touch screen top channel (xp) digital dp1 drive pin 1 for touch screen right channel (yp) digital ad0-adn analog input channels 0 to n analog
609 32099a?avr32?06/09 at32uc3l 26.5.4 interrupts the adcifb interrupt request line is connected to the interrupt controller. using the adcifb interrupt request functionality requires the interrupt controller to be programmed first. 26.5.5 peripheral events the adcifb peripheral events are connected via the peripheral event system. refer to the peripheral event system chapter for details 26.5.6 debug operation when an external debugger forces the cpu into debug mode, this module continues normal operation. if this module is configured in a way that requires it to be peri odically serviced by the cpu through interrupt requests or similar, improper operation or data loss may result during debugging. 26.6 functional description the adcifb embeds a successive approximation register (sar) analog-to-digital converter (adc). the adc supports 8-bit or 10-bit resolutions, which can be extended to 11 or 12 bits by the enhanced resolution mode. the conversion is performed on a full range between 0v and the reference voltage pin advref. analog inputs between these voltag es converts to digital val ues (codes) based on a linear con- version. this linear conversion is described in the expression below where m is the number of bits used to represent the analog value, vin is the voltage of the analog value to convert, vref is the maximum voltage, and code is the converted digital value. 26.6.1 initializing the adcifb the adc interface is enabled by writing a one to the enable bit in the control register (cr.en). after the adc interface is enabled, the adc timings needs to be configured by writing the cor- rect values to the res, prescal, and startu p fields in the adc configuration register (acr). see section 26.6.6 , and section 26.6.8 for details. before the adcifb can be used, the i/o controller must be configured correctly and the reference voltage (advref) signal must be connected. refer to section 26.5.1 for details. 26.6.2 basic operation to convert analog values to digital values the user must first initialize the adcifb as described in section 26.6.1 . when the adcifb is initialized the channels to convert must be enabled by writing a one the corresponding bits in the c hannel enable register (cher). enabling channel n instructs the adcifb to convert the analog voltage applied to ad pin n at each conversion sequence. multiple channels can be enabled resu lting in multiple ad pins being converted at each conversion sequence. to start converting data the user can either manually start a conversion sequence by writing a one to the start bit in the control register (cr.start) or configure an automatic trigger to initiate the conversions. the automatic trigger can be configured to trig on many different condi- tions. refer to section 26.8.1 for details. code 2 m v in ? v ref ------------------- - =
610 32099a?avr32?06/09 at32uc3l the result of the conversion is stored in the last converted data register (lcdr) as they become available, overwriting the result from the previous conversion. to avoid data loss if more than one channel is enabled, the user must read the conversion results as they become avail- able either by using an interrupt handler or by using a peripheral dma channel to copy the results to memory. failing to do so will result in an overrun er ror condition, indicated by the ovre bit in the status register (sr). to use an interrupt h andler the user must enable the data ready (drdy) interrupt request by writing a one to the corresponding bit in the interrupt enable register (ier). to clear the inter- rupt after the conversion result is read, the user must write a one to the corresponding bit in the interrupt clear register (icr). see section 26.6.12 for details. to use a peripheral dma controller channel the user must configure the peripheral dma con- troller appropriately. the peripheral dma controller will, when configured, automatically read converted data as they become available. ther e is no need to manually clear any bits in the interrupt status register as this is performed by the hardware. if an overrun error condition hap- pens during dma operat ion, the ovre bit in the sr will be set. 26.6.3 adc resolution the analog-to-digital converter cell supports 8-bit or 10-bit resolution natively which can be extended to 11-bit and 12-bit with the enhanced resolution mode. the resolution is selected by writing the selected resolution value to the res field in the adc confi guration register (acr). see section 26.9.3 . by writing a zero to the res field, the adc swit ches to the lowest resolution and the conversion results can be read in the eight lowest significa nt bits of the last converted data register (lcdr). the four highest bits of the last co nverted data (l data) field in the lcdr register reads as zero. writing a one to the res field enables 10-bit resolution, the optimal resolution for both sampling speed and accuracy. writing two or three automatically enables enhanced reso- lution mode with 11-bit or 12-bit resolution, see section 26.6.4 for details. when a peripheral dma controller channel is con nected to the adcifb in 10-bit, 11-bit, or 12- bit resolution mode, a transfer size of 16 bits must be used. by writing a zero to the res field, the destination buffers can be optimized for 8-bit transfers. 26.6.4 enhanced resolution mode the enhanced resolution mode is automatically enabled when 11-bit or 12-bit mode is selected in the adc configuration register (acr). in this mode the a dcifb will trade conversion perfor- mance for accuracy by aver aging multiple samples. to be able to increase the accuracy by averaging multiple samples it is important that some noise is present in the input signal. the noise level should be between one and two lsb peak- to-peak to get good averaging performance. the performance cost of enabling 11-bit mode is 4 adc samples, which reduces the effective adc performance by a factor 4. for 12-bit mode this factor is 16. for 12-bit mode the effective sample rate is maximum adc sample rate divided by 16. 26.6.5 pseudorandom noise generator the pseudorandom noise generator generates a random 1-bit signal (rnd) which can be used to add noise to the analog input signals. this signal can be muxed out to a pad using the i/o controller and added to analog input signals through a resistor. by varying the size of the resis- tor, the noise levels added can be adjusted for optimal performance.
611 32099a?avr32?06/09 at32uc3l the pseudorandom noise generator is always e nabled when a conversion is in progress, but the line can be multiplexed with other i/o controller lines. in this case, the user must make sure the i/o controller is configured correctly to allow the noise signal to propagate out to the rnd pin. 26.6.6 adc clock the adcifb generates an internal clock named clk_adc that is used by the analog-to-digital converter cell to perform conversions. the clk_ adc frequency is selected by writing to the prescal field in the adc configuration register (acr). the clk_adc range is between clk_adcifb/2, if prescal is 0, and clk_ adcifb/128, if prescal is 63 (0x3f). a sensible prescal value must be used in orde r to provide an adc clock frequency according to the maximum sampling rate parameter given in the electrical characteristics section. failing to do so may result in incorrect analog-to-digital converter operation. 26.6.7 adc sleep mode the adc sleep mode maximizes power saving by automatically deactivating the analog-to-dig- ital converter cell when it is not being used for conversions. the adc sleep mode is enabled by writing a one to the sleep bit in the adc configuration register (acr). when a trigger occurs while the adc sleep mode is enabled, the analog-to-digital converter cell is automatically activated. as the analog cell requires a startup time, the logic waits during this time and then starts the conversion of the enabled channels. when conversions of all enabled channels are complete, the adc is deactivated until the next trigger. 26.6.8 startup time the analog-to-digital converter cell has a minimal startup time when the cell is activated. this startup time is given in the electrical characteristics chapter and must be written to the startup field in the adc configuration register (acr) to get correct conversion results. the startup field expects the startup time to be represented as the number of clk_adc cycles between 8 and 1024 and in steps of 8 that is needed to cover the adc startup time as specified in the electrical characteristics chapter. the analog-to-digital converter cell is activated at the first conversion after reset and remains active if acr.sleep is zero. if acr.sleep is one , the analog-to-digital converter cell is auto- matically deactivated when idle and thus each conversion se quence will have a initial startup time delay. 26.6.9 sample and hold time a minimal sample and hold time is necessary for the adcifb to guarantee the best converted final value when switching between adc channels. this time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. the sample and hold time has to be programmed through the shtim field in the adc configu- ration register (acr). this field can def ine a sample and hold time between 1 and 16 clk_adc cycles. 26.6.10 adc conversion adc conversions are performed on all enabled c hannels when a trigger condition is detected. for details regarding trigger conditions see section 26.8.1 . the term channel is used to identify
612 32099a?avr32?06/09 at32uc3l a specific analog input pin so it can be included or excluded in an analog-to-digital conversion sequence and to identify which ad pin was used to convert the current value in the last con- verted data register (lcdr). channel number n corresponding to ad pin number n. channels are enabled by writing a one to the corresponding bit in the channel enable register (cher), and disabled by writing a one to the co rresponding bit in the channel disable register (chdr). active channels are listed in the channel status register (chsr). when a conversion sequence is started, all enabled channels will be c onverted in one sequence and the result will be placed in the last conv erted data register (l cdr) with the channel num- ber used to produce the result. it is important to read out the results while the conversion sequence is ongoi ng, as new values will auto matically overwrite any ol d value and the old value will be lost if not previously read by the user. if the analog-to-digital converter cell is inactive when starting a conversion sequence, the con- version logic will wait a configurable number of clk_adc cycles as defined in the startup time field in the adc configuration register (acr). af ter the cell is activated all enabled channels is converted one by one until no more enabled ch annels exist. the conversion sequence converts each enabled channel in order starting with the channel with the lowest channel number. if the acr.sleep bit is one, the analog- to-digital converter cell is d eactivated after the conversion sequence has finished. for each channel converted, the adcifb waits a sample and hold number of clk_adc cycles as defined in the shtim field in acr, and then instructs the analog-to-digital converter cell to start converting the analog voltage. the adc ce ll requires 10 clk_adc cycles to actually con- vert the value, so the total time to convert a channel i sample and hold + 10 clk_adc cycles. 26.6.11 analog compare mode the adcifb can test if the converted values, as they become availabl e, are below, above, or inside a specified range and generate interrupt requests based on this information. this is useful for applications where the user wants to moni tor some external analog signal and only initiate actions if the value is above, below, or inside some specified range. the analog compare mode is enabled by writing a one to the analog compare enable (ace) bit in the mode register (mr). the values to compare must be written to the low value (lv) field and the high value (hv) field in the compare value register (cvr). the analog compare mode will, when enabled, check all enabled channels against the pre-programmed high and low values and set status bits. to generate an interrupt request if a converted value is below a limit, write the limit to the cvr.lv field and enable interrupt request on th e compare lesser than (clt) bit by writing a one to the corresponding bit in the interrupt enable register (ier). to generate an interrupt request if a converted value is above a limit, writ e the limit to the cvr.hv field and enable inter- rupt for compare greater than (cgt) bit. to generate an interrupt request if a converted value is inside a range, write the low and high limit to the lv and hv fields and enable the compare else (celse) interrupt. to generate an interrupt request if a value is outside a range, write the lv and hv fields to the low and high limits of the range and enable cgt and clt interrupts. note that the values written to lv and hv must match the resolution selected in the adc config- uration register (acr).
613 32099a?avr32?06/09 at32uc3l 26.6.12 interrupt operation interrupt requests are enabled by writing a one to the corresponding bit in the interrupt enable register (ier) and disabled by writing a one to the corresponding bit in the interrupt disable register (idr). enabled interrupts can be read fr om the interrupt mask register (imr). active interrupt requests, but potentially masked, are visible in the interrupt status register (isr). to clear an active interrupt request, write a one to the corresponding bit in the interrupt clear reg- ister (icr). the source for the interrupt requests are the status bits in the status register (sr). the sr shows the adcifb status at the time the register is read. the interrupt status register (isr) shows the status since the last write to the interrupt clear register. the combination of isr and sr allows the user to react to status change co nditions but also allows the user to read the cur- rent status at any time. 26.6.13 peripheral events the peripheral event system can be used together with the adcifb to allow any peripheral event generator to be used as a trigger source. to enable peripheral events to trigger a conver- sion sequence the user must write the peripheral event trigger value (0x7) to the trigger mode (trgmod) field in the trigger register (trgr). refer to table 26-4 on page 625 . the user must also configure a peripheral event generator to emit peripheral events for the adcifb to trigger on. refer to the peripheral event system chapter for details. 26.6.14 sleep mode before entering sleep modes the user must make sure the adcifb is idle and that the analog- to-digital converter cell is inactive. to deactivate the analog-to-digital converter cell the sleep bit in the adc configuration register (acr) must be written to one and the adcifb must be idle. to make sure the adcifb is idle, write a zero the trigger mode (trgmod) field in the trigger register (trgr) and wait for the ready bit in the status register (sr) to be set. note that by deactivating the analog-to-digital converter cell, a startup time penalty as defined in the startup field in the adc configur ation register (acr) will apply on the next conversion. 26.6.15 conversion performances for performance and electrical characteristics of the adcifb, refer to the electrical characteris- tics chapter.
614 32099a?avr32?06/09 at32uc3l 26.7 resisitve touch screen the adcifb embeds an integrated resistive touc h screen sequencer that can be used to calcu- late contact coordinates on a resistive film touch screen. when instructed to start, the integrated touch screen sequencer automatically applies a sequence of voltage patterns to the touch screen films and the analog-to-digital conversion cell is used to measure the effects. the result- ing measurements can be used to calculate the horizontal and vertical contact coordinates. the touch screen film is connected to the adcifb using the ad and dp pins. see section 26.7.3 for details. touch screen adc mode is enabled by writing a one to the tsamod field in the mode register (mr). in this mode, channels tspo+0 though tspo+3 are automatically enabled where tspo refers to the touch screen pin offset field in the mode register. for each conversion sequence, all enabled channles before tspo+0 and after tspo+3 are converted as ordinary adc chan- nels, producing 1 conversion result each. when the sequencer enters the tspo+0 channel the touch screen sequencer will take over control and convert the next 4 channles as described in section 26.7.4 . 26.7.1 resistive touch screen principles a resistive touch screen is based on two resistive films, each one fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. between the two, there is a layer that acts as an insulator, but makes a connection when pressure is applied to the screen. this is illustrated in figure 26-2 on page 614 . figure 26-2. touch screen position measurement 26.7.2 position measurement method as shown in figure 26-2 on page 614 , to detect the position of a contact, voltage is first applied to x p (top) and x m (bottom) leaving y p and y m tristated. due to the linear resistance of the film, there is a voltage gradient from top to bottom on the first film. when a contact is performed on x m x p y m y p x p x m y p vdd gnd volt horizontal position detection y p y m x p vdd gnd volt vertical position detection pen contact
615 32099a?avr32?06/09 at32uc3l the screen, the voltage at the contact point propagates to the second film. if the input impedance on the y p (right) and y m (left) electrodes are high enough, no current will flow, allowing the volt- age at the contact point to be measured at y p . the value measured represents the vertical position component of the contact point. for the horizontal direction, the same method is used, but by applying voltage from y p (right) to y m (left) and measuring at x p . in an ideal world (linear, with no loss ), the vertical position is equal to: vy p / vdd to compensate for some of the real world imperfections, vx p and vx m can be measured and used to improve accuracy at the cost of two mo re conversions per axes. the new expression for the vertical position then becomes: (vy p - vx m ) / (vx p - vx m ) 26.7.3 touch screen pin connections the touch screen film signals connects to the adcifb using the ad and dp pins. the x p (top) and x m (bottom) film signals are connected to adtspo+0 and adtspo+1 pins, and the y p (right) and y m (left) signals are connected to adtspo+2 a nd adtspo+3 pins. the tspo index is configu- rable through the touch screen pin offset (tspo) field in the mode register (mr) and allows the user to configure which ad pins to use for touch screen applications. writing a zero to the tspo field instructs the adcifb to use ad0 through ad3, where ad0 is connected to x p , ad1 is connected to x m and so on. writing a one to the tspo field instructs the adcifb to use ad1 through ad4 for touch screen sequen cing, where ad1 is connected to x p and ad0 is free to be used as an ordinary adc channel. when the analog pin output enable (apoe) bit in the mode register (mr) is zero, the ad pins are used to measure input voltage and drive the gnd sequences, while the dp pins are used to drive the vdd sequences. this arrangement allows the user to reduce the voltage seen at the ad input pins by inserting external resistors between dp0 and x p and dp1 and y p signals which are again directly connected to the ad pins. it is important that the voltages observed at the ad pins are not higher than the maximum allowed adc input voltage. see figure 26-3 on page 617 for details regarding how to connect the touch screen films to the ad and dp pins. by adding a resistor between dp0 and x p , and dp1 and y p , the maximum voltage observed at the ad pins can be controlled by the following voltage divider expressions: table 26-2. touch screen pin connections adcifb pin ts signal, apoe == 0 ts signal, apoe == 1 dp0 xp through a resistor no connect dp1 yp through a resistor no connect adtspo+0 xp xp adtspo+1 xm xm adtspo+2 yp yp adtspo+3 ym ym
616 32099a?avr32?06/09 at32uc3l the rfilmx parameter is the film resistance obersved when measuring between x p and x m . the rresistorx parameter is the resistor size inserted between dp0 and x p . the definition of rfilmy and rresistory is the same but for dp1, y p , and y m instead. the dp pins are used by default, as the apoe bit is zero after reset. writing a one to the apoe bit instructs the adcifb touch screen sequencer to use the already connected adtspo+0 and adtspo+2 pins to drive vdd to x p and y p signals directly. in this mode the dp pins can be used as general purpose i/o pins. before writing a one to the apoe bit the user must make sure that the i/o voltage is compatible with the adc input voltage. if the i/o voltage is higher than the maximum input voltage of the adc, permanent damage may occur. refer to the electrical characteristics chapter for details. vad tspo 0 + () r filmx r filmx r resistorx + -------------------------------------------- - vdp 0 () ? = vad tspo 2 + () r filmy r filmy r resistory + --------------------------------------------- - vdp 1 () ? =
617 32099a?avr32?06/09 at32uc3l figure 26-3. touch screen pin connections 26.7.4 touch screen sequencer the touch screen sequencer is responsible for applying voltage to the resistive touch screen films as described in section 26.7.2 . this is done by controlling the output enable and the output value of the dp and ad pins. this allows the touch screen sequencer to add a voltage gradient on one film while keeping the other film floating so a touch can be measured. the touch screen se quencer will when measuring the vertic al position, apply vdd and gnd to the pins connected to x p and x m . the y p and y m pins are put in tristate mode so the measure- ment of y p can proceed without interference. to compansate for adc offset errors and non ideal pad drivers, the actual voltage of x p and x m is measured as well, so the real values for vdd and gnd can be used in the contact point calculation to increase accurcy. see second formula in section 26.7.2 . when the vertical values are converted the same setup is applies for the second axes, by setting x p and x m in tristate mode and applying vdd and gnd to y p and y m . refer to section 26.8.3 for details. ad tspo+1 x m x p y m y p ad tspo+0 dp 1 dp 0 ad tspo+3 ad tspo+2 analog pin o u tp u t ena b le (mr.apoe) == 0 ad tspo+1 x m x p y m y p ad tspo+0 dp 1 dp 0 ad tspo+3 ad tspo+2 analog pin o u tp u t ena b le (mr.apoe) == 1 n c n c
618 32099a?avr32?06/09 at32uc3l 26.7.5 pen detect if no contact is applied to the touch screen films, any touch screen conversion result will be undefined as the film being measured is floati ng. this can be avoided by enabling pen detect and only trigger touch screen conversions when t he pen contact (pencnt) status bit in the status register (sr) is one. pen detect is enabled by writing a one to the pen detect (pendet) bit in the mode register (mr) when pen detect is enabled, the adcifb gro unds the vertical panel by applying gnd to x p and x m and polarizes the horizontal panel by enabling pull-up on the pin connected to y p . the y m pin will in this mode be tris tated. since there is no contact, no current is flowin g and there is no related power consumption. as soon as a contact occurs, gnd will propagate to y m by pulling down y p , allowing the contact to be registered by the adcifb. a programmable debouncing filter can be used to filter out false pen detects because of noise. the debouncing filter is programmable from one clk_adc period and up to 2 15 clk_adc peri- ods. the debouncer length is set by writing to the pendbc field in mr. figure 26-4. touch screen pen detect the touch screen pen detect can be used to generate an adcifb interrupt request or it can be used to trig a conversion, so that a position c an be measured as soon as a contact is detected. the pen detect mode generates two types of status signals, reported in the status register (sr): ? the bit pencnt is set when current flows and remains set until current stops. ? the bit nocnt is set when no current flows and remains set until current flows. before a current change is reflected in the sr, the new status must be stable for the duration of the debouncing time. both status conditions can generate an interrupt request if the corresponding bit in the interrupt mask register (imr) is one. refer to section 26.6.12 on page 613 . x p x m y m y p tristate g n d p u ll u p to the adc pen interr u pt de b o u ncer pe n dbc to u ch screen se qu encer g n d
619 32099a?avr32?06/09 at32uc3l 26.8 operating modes the adcifb features two operating modes, eac h defining a separate conversion sequence: ? adc mode: at each trigger, all the enabled channels are converted. ? touch screen adc mode: at each trigger, all enabled channels plus the touch screen channels are converted as described in section 26.8.3 . if channels except the dedicated touch screen channels are enabled, they are converted normally before and after the touch screen channels are converted. the operating mode is selected by the tsamod field in the mode register (mr). 26.8.1 conversion triggers a conversion sequence is started either by a software or by a hardware trigger. when a conver- sion sequence is started, a ll enabled channels will be conver ted and made available in the shared last converted register (lcdr). the software trigger is asserted by writing a one to the start field in th e control register (cr). the hardware trigger can be selected by the trgmod field in the trigger register (trgr). dif- ferent hardware triggers exist: ? external trigger, either rising or falling or any, detected on the external trigger pin adtrg ? pen detect trigger, depending the pendet bit in the mode register (mr) ? continuous trigger, meaning the adcifb restarts the next sequence as soon as it finishes the current one ? periodic trigger, which is defined by the trgr.trgper field ? peripheral event trigger, allowing the peripheral event system to synchronize conversion with some configured peripheral event source. enabling a hardware trigger does not disable the software trigger functionality. thus, if a hard- ware trigger is selected, the star t of a conversion can still be in itiated by the so ftware trigger. 26.8.2 adc mode in the adc mode, the active channels are defi ned by the channel status register (chsr). a channel is enabled by writing a one to the corresponding bit in the channel enable register (cher), and disabled by writing a one to the co rresponding bit in the channel disable register (chdr). the conversion results are stored in the last converted data register (lcdr) as they become available, overwriting old conversions. at each trigger, the following sequence is performed: 1. if acr.sleep is one, wake up the adc and wait for the startup time. 2. if channel 0 is enabled, convert channel 0 and store result in lcdr. 3. if channel 1 is enabled, convert channel 1 and store result in lcdr. 4. if channel n is enabled, convert channel n and store result in lcdr. 5. if acr.sleep is one, place the adc cell in a low-power state. if the peripheral dma controller is enabled, all converted values are transferred continuously into the memory buffer. 26.8.3 touch screen adc mode writing a one to the tsamod field in the mode register (mr) enables touch screen adc mode. in this mode the channels tspo+0 to tspo+3, corresponding to the touch screen
620 32099a?avr32?06/09 at32uc3l inputs, are automatically activated. in addition, if any other channels are enabled, they will be converted before and after the touch screen conversion. at each trigger, the following sequence is performed: 1. if acr.sleep is one, wake up the a dc cell and wait for the startup time. 2. convert all enabled channels before t spo and store the results in the lcdr. 3. apply supply on the inputs x p and x m during the sample and hold time. 4. convert channel x m and store the result in tmp. 5. apply supply on the inputs x p and x m during the sample and hold time. 6. convert channel x p , subtract tmp from the result a nd store the subtracted result in lcdr. 7. apply supply on the inputs x p and x m during the sample and hold time. 8. convert channel y p , subtract tmp from the result a nd store the subtracted result in lcdr. 9. apply supply on the inputs y p and y m during the sample and hold time. 10. convert channel y m and store the result in tmp. 11. apply supply on the inputs y p and y m during the sample and hold time. 12. convert channel y p , subtract tmp from the result a nd store the subtracted result in lcdr. 13. apply supply on the inputs y p and y m during the sample and hold time. 14. convert channel x p , subtract tmp from the result a nd store the subtracted result in lcdr. 15. convert all enabled channels after tspo + 3 and store results in the lcdr. 16. if acr.sleep is one, place the adc cell in a low-power state. the resulting buffer structure stored in memory is: 1. x p - x m 2. y p - x m 3. y p - y m 4. x p - y m . the vertical position can be easily calculated by dividing the data at offset 1(x p - x m ) by the data at offset 2(y p - x m ). the horizontal position can be easily calculated by dividing the data at offset 3(y p - y m ) by the data at offset 4(x p - y m ).
621 32099a?avr32?06/09 at32uc3l 26.9 user interface note: 1. the reset values for these registers are device specific. please refer to the module configuration section at the end of this chapter. table 26-3. adcifb register memory map offset register name access reset 0x00 control register cr write-only - 0x04 mode register mr read/write 0x00000000 0x08 adc configuration register acr read/write 0x00000000 0x0c trigger register trgr read/write 0x00000000 0x10 compare value register cvr read/write 0x00000000 0x14 status register sr read-only 0x00000000 0x18 interrupt status register isr read-only 0x00000000 0x1c interrupt clear register icr write-only - 0x20 interrupt enable register ier write-only - 0x24 interrupt disable register idr write-only - 0x28 interrupt mask register imr read-only 0x00000000 0x2c last converted data register lcdr read-only 0x00000000 0x30 parameter register parameter read-only - (1) 0x34 version register version read-only - (1) 0x40 channel enable register cher write-only - 0x44 channel disable register chdr write-only - 0x48 channel status register chsr read-only 0x00000000
622 32099a?avr32?06/09 at32uc3l 26.9.1 control register register name: cr access type: write-only offset: 0x00 reset value: 0x00000000 ? dis: adcdifb disable writing a zero to this bit has no effect. writing a one to this bit disables the adcifb. note: disabling the adcifb effectively stop s all clocks in the module so the user must make sure the adcifb is idle before disabling the adcifb. ? en: adcifb enable writing a zero to this bit has no effect. writing a one to this bit enables the adcifb. note: the adcifb must be enabled before use. ? start: start conversion writing a zero to this bit has no effect. writing a one to this bit starts an analog-to-digital conversion. ? swrst: software reset writing a zero to this bit has no effect. writing a one to this bit resets the adcifb, simulating a hardware reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????disen 76543210 ??????startswrst
623 32099a?avr32?06/09 at32uc3l 26.9.2 mode register name: mr access type: read/write offset: 0x04 reset value: 0x00000000 ? pendbc: pen detect debouncing period period = 2 pendbc *t clk_adc ? tspo: touch screen pin offset the touch screen pin offset field is used to indicate which ad pins are connected to the resistive touch screen film edges. onl y an offset is specified and it is assumed that the touch screen films are connected s equentially from the specified offset pin a nd up to and including offset + 3 (4 pins). ? apoe: analog pin output enable 0: ad pins are not used to drive vdd in touch screen sequence. 1: ad pins are used to drive vdd in touch screen sequence. note : if the selected i/o voltage configuration is incompatible wit h the analog-to-digital converter cell voltage specification, th is bit must stay cleared to avoid damaging the adc. in this case the dp pins must be used to drive vdd instead, as described in section 26.7.3 . if the i/o and adc voltages are compatible, the ad pins can be used directly by writing a one to this bit. in this case the dp pins can be ignored. ? ace: analog compare enable 0: the analog compare functionality is disabled. 1: the analog compare functionality is enabled. ? pendet: pen detect 0: the pen detect functionality is disabled. 1: the pen detect functionality is enabled. ? tsamod: touch screen adc mode 0: touch screen mode is disabled. 1: touch screen mode is enabled. 31 30 29 28 27 26 25 24 pendbc ???? 23 22 21 20 19 18 17 16 tspo 15 14 13 12 11 10 9 8 ? ?? ????? 76543210 ? apoe ace pendet ? ? ? tsamod
624 32099a?avr32?06/09 at32uc3l 26.9.3 adc configuration register name: acr access type: read/write offset: 0x08 reset value: 0x00000000 ? shtim: sample & hold time for adc channels ? startup: startup time ? prescal: prescaler rate selection ? res: resolution selection 0: 8-bit resolution. 1: 10-bit resolution. 2: 11-bit resolution, interpolated. 3: 12-bit resolution, interpolated. ? sleep: adc sleep mode 0: adc sleep mode is disabled. 1: adc sleep mode is enabled. 31 30 29 28 27 26 25 24 ? ??? shtim 23 22 21 20 19 18 17 16 ?startup 15 14 13 12 11 10 9 8 ? ? prescal 76543210 - ? res ? ? ? sleep t sample & hold shtim t clk _ adc ? = t startup startup 8 ? t clk _ adc ? = t clk _ adc prescal 1 + () 2 ? = t clk _ adcifb ?
625 32099a?avr32?06/09 at32uc3l 26.9.4 trigger register name: trgr access type: read/write offset: 0x0c reset value: 0x00000000 ? trgper: trigger period effective only if trgmod defines a periodic trigger. defines the periodic trigger period, with the following equations: trigger period = trgper *t clk_adc ? trgmod: trigger mode 31 30 29 28 27 26 25 24 trgper[15:8] 23 22 21 20 19 18 17 16 trgper[7:0] 15 14 13 12 11 10 9 8 ???????? 76543210 ????? trgmod table 26-4. trigger modes trgmod selected trigger mode 0 0 0 no trigger, only software trigger can start conversions 0 0 1 external trigger rising edge 0 1 0 external trigger falling edge 0 1 1 external trigger any edge 100 pen detect trigger (shall be selected only if pendet is set and tsamod = touch screen mode) 1 0 1 periodic trigger (trgper shall be initiated appropriately) 1 1 0 continuous mode 1 1 1 peripheral event trigger
626 32099a?avr32?06/09 at32uc3l 26.9.5 compare value register name: cvr access type: read/write offset: 0x10 reset value: 0x00000000 ? hv: high value defines the high value used when comparing analog input. ? lv: l ow va l u e defines the low value used when comparing analog input. 31 30 29 28 27 26 25 24 ???? hv[11:8] 23 22 21 20 19 18 17 16 hv[7:0] 15 14 13 12 11 10 9 8 ???? lv[11:8] 76543210 lv[7:0]
627 32099a?avr32?06/09 at32uc3l 26.9.6 status register name: sr access type: read-only offset: 0x14 reset value: 0x00000000 ? en: enable status 0: the adcifb is disabled. 1: the adcifb is enabled. ? celse: compare else status 0: either clt or cgt detected or compare is disabled. 1: no clt or cgt detected on last converted data. ? cgt: compare greater than status 0: no compare greater than cvr.hv detected on last converted data or compare is disabled. 1: compare greater than cvr.hv detected on last converted data or compare is disabled. ? clt: compare lesser than status 0: no compare lesser than cvr. lv detected on last converted data or compare is disabled. 1: compare lesser than cvr. lv detected on last converted data or compare is disabled. ? busy: busy status 0: the adcifb is ready to perform a conversion sequence. 1: the adcifb is busy performing a convention sequence. ? ready: ready status 0: the adcifb is busy pe rforming a conversion sequence. 1: the adcifb is ready to perform a conversion sequence. ? nocnt: no contact status 0: no contact loss is detected or pen detect disabled. 1: contact loss is detected. ? pencnt: pen contact status 0: no contact is detected or pen detect disabled. 1: pen contact is detected. ? ovre: overrun error status 0: no overrun error has occurred sinc e the start of conversion sequence. 1: one or more overrun error has occurred since the start of conversion sequence. ? drdy: data ready status 0: no data has been converted since the start of conversion sequence. 1: one or more data has been converted since the start of conversion and is available in lcdr. 31 30 29 28 27 26 25 24 ???????en 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 celse cgt clt ? ? busy ready 76543210 ? ? nocnt pencnt ? ? ovre drdy
628 32099a?avr32?06/09 at32uc3l 26.9.7 interrupt status register name: isr access type: read-only offset: 0x18 reset value: 0x00000000 a bit in this register is cleared by writing a one to the corresponding bit in the interrupt clear register (isr). a bit in this register is set when the corresponding bit in the status register (sr) is set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? celse cgt clt ? ? busy ready 76543210 ? ? nocnt pencnt ? ? ovre drdy
629 32099a?avr32?06/09 at32uc3l 26.9.8 interrupt clear register name: icr access type: write-only offset: 0x1c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in isr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? celse cgt clt ? ? busy ready 76543210 ? ? nocnt pencnt ? ? ovre drdy
630 32099a?avr32?06/09 at32uc3l 26.9.9 interrupt enable register name: ier access type: write-only offset: 0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? celse cgt clt ? ? busy ready 76543210 ? ? nocnt pencnt ? ? ovre drdy
631 32099a?avr32?06/09 at32uc3l 26.9.10 interrupt disable register name : idr access type: write-only offset: 0x24 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? celse cgt clt ? ? busy ready 76 ? ? nocnt pencnt ? ? ovre drdy
632 32099a?avr32?06/09 at32uc3l 26.9.11 interrupt mask register name: imr access type: read-only offset: 0x28 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared by writing a one to the corresponding bit in interrupt disable register (idr). a bit in this register is set by writing a one to the corresponding bit in interrupt enable register (ier). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? celse cgt clt ? ? busy ready 76 ? ? nocnt pencnt ? ? ovre drdy
633 32099a?avr32?06/09 at32uc3l 26.9.12 last converted data register name: lcdr access type: read-only offset: 0x2c reset value: 0x00000000 ? lcch: last converted channel this field indicates what channel was last conv erted, i.e. what channel the ldata represents. ? ldata: last data converted the analog-to-digital conversion data is placed in this register at the end of a conversion on any analog channel and remains until a new conversion on any analog channel is completed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 lcch 15 14 13 12 11 10 9 8 ???? ldata[11:8] 76543210 ldata[7:0]
634 32099a?avr32?06/09 at32uc3l 26.9.13 parameter register name: parameter access type: read-only offset: 0x30 reset value: 0x00000000 ? chn: channel n implemented 0: the corresponding channel is not implemented. 1: the corresponding channel is implemented. 31 30 29 28 27 26 25 24 ch31 ch30 ch29 ch28 ch27 ch26 ch25 ch24 23 22 21 20 19 18 17 16 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ch16 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
635 32099a?avr32?06/09 at32uc3l 26.9.14 version register name: version access type: read-only offset: 0x34 reset value: 0x00000000 ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? variant 15 14 13 12 11 10 9 8 ???? version[11:8] 76543210 version[7:0]
636 32099a?avr32?06/09 at32uc3l 26.9.15 channel enable register name: cher access type: write-only offset: 0x40 reset value: 0x00000000 ? chn: channel n enable writing a zero to a bit in this register has no effect writing a one to a bit in this register enables the corresponding channel the number of available channels is device dependent. please re fer to the module cconfiguration section at the end of this chapter for information regardin g which channels are implemented. 31 30 29 28 27 26 25 24 ch31 ch30 ch29 ch28 ch27 ch26 ch25 ch24 23 22 21 20 19 18 17 16 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ch16 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
637 32099a?avr32?06/09 at32uc3l 26.9.16 channel disable register name: chdr access type: write-only offset: 0x44 reset value : 0x00000000 ? chn: channel n disable writing a zero to a bit in this register has no effect. writing a one to a bit in this register disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion, or if it is disabled and then re-enabled during a conversion, its associated data and its corresponding drdy and ovre bits in sr are unpredictable. the number of available channels is device dependent. please re fer to the modulecconfiguration section at the end of this chapter for information regarding how many channels are implemented. 31 30 29 28 27 26 25 24 ch31 ch30 ch29 ch28 ch27 ch26 ch25 ch24 23 22 21 20 19 18 17 16 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ch16 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
638 32099a?avr32?06/09 at32uc3l 26.9.17 channel status register name: chsr access type: read-only offset: 0x48 reset value: 0x00000000 ? chn: channel n status 0: the corresponding channel is disabled. 1: the corresponding channel is enabled. a bit in this register is cleared by writing a one to the corresponding bit in channel disable register (chdr). a bit in this register is set by writing a one to the corresponding bit in channel enable register (cher). the number of available channels is device dependent. please re fer to the modulecconfiguration section at the end of this chapter for information regarding how many channels are implemented. 31 30 29 28 27 26 25 24 ch31 ch30 ch29 ch28 ch27 ch26 ch25 ch24 23 22 21 20 19 18 17 16 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ch16 15 14 13 12 11 10 9 8 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
639 32099a?avr32?06/09 at32uc3l 26.10 module configuration the specific configuration for each adcifb inst ance is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 26-5. module configuration feature adcifb number of adc channels 10 (9 + 1) table 26-6. module clock name module name clock name adcifb clk_adcifb table 26-7. register reset values register reset value version 0x00000101 parameter 0x000003ff table 26-8. adc input channels channel input ch0 ad0 ch1 ad1 ch2 ad2 ch3 ad3 ch4 ad4 ch5 ad5 ch6 ad6 ch7 ad7 ch8 ad8 ch9 temperature sensor
640 32099a?avr32?06/09 at32uc3l 27. analog comparator interface (acifb) rev: 2.0.2.1 27.1 features ? controls an array of analog comparators ? low power option ? single shot mode support ? selectable settings for filter option ? filter length and hysteresis ? window mode ? detect inside/outside window ? detect above/below window ? interrupt ? on comparator result rising edge, falling edge, toggle ? inside window, outside window, toggle ? when startup time has passed ? can generate events to the peripheral event system 27.2 overview the analog comparator interface (acifb) is able to control a number of analog comparators (ac) with identical behavior. an analog compar ator compares two voltages and gives a com- pare output depending on this comparison. the acifb can be configured in normal mode using each comparator independently or in win- dow mode using defined comparator pairs to observe a window. the number of channels implemented is device specific. refer to the module configuration sec- tion at the end of this chapter for details.
641 32099a?avr32?06/09 at32uc3l 27.3 block diagram figure 27-1. acifb block diagram 27.4 i/o lines description 27.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 27.5.1 i/o lines the acifb pins are multiplexed with other peripherals. the user must first program the i/o con- troller to give control of the pins to the acifb. 27.5.2 power management if the cpu enters a sleep mode that disables cl ocks used by the acifb, the acifb will stop functioning and resume operation after the system wakes up from sleep mode. ?????... trigger events irq gclk peripheral bus acifb analog comparators peripheral event generation - + ac inn inp ac0_inseln - + ac inn inp acn_inseln filter filter interrupt generation clk_acifb actest actestn actest0 acn0 a c p 0 acpn acnn a c r e f n acout0 acoutn table 27-1. i/o line description pin name pin description type acpn positive reference pin for analog comparator n analog acnn negative reference pin for analog comparator n analog acrefn reference voltage for all com parators selectable for inn analog
642 32099a?avr32?06/09 at32uc3l 27.5.3 clocks the clock for the acifb bus interface (clk_acifb) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to dis- able the acifb before disabling the clock, to avoid freezing the acifb in an undefined state. the acifb uses a gclk as clock source for the analog comparators. the user must set up this gclk at the right frequency. the clk_acifb cloc k of the interface must be at least 4x the gclk frequency used in the comparators. the gc lk is used both for measuring the startup time of a comparator, and to give a frequency for the comparations done in continuous mea- surement mode, see section 27.6 . refer to the electrical characteristics chapter for gclk frequency limitations. 27.5.4 interrupts the acifb interrupt request line is connected to the interrupt controller. using the acifb inter- rupt requires the interrupt controller to be programmed first. 27.5.5 peripheral events the acifb peripheral events are connected via the peripheral event system. refer to the peripheral event system chapter for details. 27.5.6 debug operation when an external debugger forces the cpu into debug mode, the acifb continues normal operation. if the acifb is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 27.6 functional description the acifb is enabled by writing a one to the co ntrol register enable bi t (ctrl.en). addition- ally, the comparators must be individually enabled by programming the mode field in the ac configuration register (confn.mode). the results from the individual comparators can either be used directly (normal mode), or the results from two comparators can be grouped to generate a comparison window (window mode). all comparators need not be in the same mode, some comparators may be in normal mode, while others are in window mode. there are restrictions on which ac channels that can be grouped together in a window pair, see section 27.6.3 . 27.6.1 analog comparator operation each ac channel can be in one of four different modes, determined by confn.mode: ?off ? continuous measurement mode (cm) ? user triggered single measurement mode (ut) ? event triggered single measurement mode (et) after being enabled, a startup time defined in ctrl.sut is required before the result of the comparison is ready. the gclk is used for measuring the startup time of a comparator, during the startup time the ac output is not available. when the acn ready bit in the status register (sr.acrdyn) is one, the output of ac n is ready. in window mode the result is avail- able when both the compar ator outputs are ready (sr. acrdyn=1 and sr.acrdyn+1=1).
643 32099a?avr32?06/09 at32uc3l 27.6.1.1 continuous measurement mode in cm, the analog comparator is continuously enabled and performing comparisons. this ensures that the result of the latest comparison is always available in the acn current compari- son status bit in the status register (sr. accsn). comparisons are done on every positive edge of gclk. cm is enabled by writing confn. mode to 1. after the startup time has passed, a comparison is done and sr is updated. appropriate peripheral events and interrupts are also generated. new comparisons are performed continuously until the confn.mode field is written to 0. 27.6.1.2 user triggered single measurement mode in the ut mode, the user starts a single comparison by writing a one to the user start single conversion bit (ctrl.ustart). this mode is enabled by writing confn.mode to 2. after the startup time has passed, a single comparison is done and sr is updated. appropriate peripheral events and interrupts are also generated. no new comparisons will be performed. ctrl.ustart is cleared automatically by hardware when the single comparison has been done. 27.6.1.3 event triggered single measurement mode this mode is enabled by writing confn.mode to 3 and peripheral event trigger enable (ctrl.eventen) to one. the et mode is similar to the ut mode, the difference is that a peripheral event from another hardware module causes the hardware to automatically set the peripheral event start single conversion bit (ctrl.estart). after the startup time has passed, a single comparison is done and sr is updated. appropriate peripheral events and interrupts are also generated. no new compar isons will be perf ormed. ctrl.estart is cleared automatically by hardware when the single comparison has been done. 27.6.1.4 selecting comparator inputs each analog comparator has one positive (i np) and one negative (inn) input. the positive input is fed from an external input pin (acp n). the negative input can either be fed from an external input pin (acnn) or from a reference voltage common to all acs (acrefn). the user selects the in put source as follows: ? in normal mode with the negative input select and positive input select fields (confn.inseln and confn.inselp). ? in window mode with confn.inseln, confn.inselp and confn+1.inseln, confn+1,inselp. the user must configure confn.inseln and confn+1.inselp to the same source. 27.6.2 normal mode in normal mode all analog comparators are operating independently. 27.6.2.1 normal mode output each analog comparator generates one output acout according to the input voltages on inp (ac positive input) and inn (ac negative input): ? acout = 1 if v inp > v inn ? acout = 0 if v inp < v inn ? acout = 0 if the ac output is not available (sr.acrdy = 0) the output can optionally be filtered, as described in section 27.6.4 .
644 32099a?avr32?06/09 at32uc3l 27.6.2.2 normal mode interrupt the ac channels can generate interrupts. the inte rrupt settings field in the configuration regis- ter (confn.is) can be configured to select when the ac will generate an interrupt: ? when v inp > v inn ? when v inp < v inn ? on toggle of the ac output (acout) ? when comparison has been done 27.6.2.3 normal mode events the acifb can generate peripheral events according to the configuration of confn.evenn and confn.evenp. ? when v inp > v inn or ? when v inp < v inn or ? on toggle of the ac output (acout) 27.6.3 window mode in window mode, two acs (an even and the following odd build up a pair) are grouped. the negative input of acn (even) and the positive input of acn+1 (odd) has to be connected together externally to the device and are controlled by the input select fields in the ac configu- ration registers (confn.inseln and confn+1.in selp). the positive input of acn (even) and the negative inpu t of acn+1 (odd) can still be configur ed independently by confn.inselp and confn+1.inseln, respectively. figure 27-2. analog comparator interface in window mode comparator pair - + ac interrupt generator window module acoutn peripheral event generator window window event - + ac filter filter sr[accsn] sr[wfcsn] acpn acnn acpn+1 common acwout acnn+1 irq acoutn+1
645 32099a?avr32?06/09 at32uc3l 27.6.3.1 window mode output when operating in window mode, each channel generates the same acout outputs as in nor- mal mode, see section 27.6.2.1 . additionally, the acifb generates a window mode signal (acwout) according to the common input voltage to be compared: ? acwout = 1 if the common input voltage is inside the window, v acn(n+1) < v common < v acp(n) ? acwout = 0 if the common input voltage is outside the window, v common < v acn(n+1) or v common > v acp(n) ? acwout = 0 if the window mode output is not available (sr.acrdy n =0 or sr.acrdy n+1=0) 27.6.3.2 window mode interrupts when operating in window mode, each channel can generate the same interrupts as in normal mode, see section 27.6.2.2 . additionally, when channels operate in window mode, programming window mode interrupt set- tings in the window mode configuration register (confwn.wis) can cause interrupts to be generated when: ? as soon as the common inpu t voltage is inside the window. ? as soon as the common input voltage is outside the window. ? on toggle of the window compare output (acwout). ? when the comparison in both channels in the window pair are ready. 27.6.3.3 window mode events when operating in window mode, each channel can generate the same events as in normal mode, see section 27.6.2.3 . additionally, when channels operate in window mode, programming window mode event selec- tion source (confwn.wevsrc) can caus e events to be generated when: ? as soon as v acn(n+1) < v common < v acp(n) ? as soon as v common < v acn(n+1) or v common > v acp(n) ? on toggle of the window compare output (acwout) 27.6.4 filtering the output of the comparator can be filtered to reduce noise. the filter length is determined by the filter length field in the confn register (confn.flen). the filter samples the analog comparator output at the gclk frequency for 2 confn.flen samples. a separa te counter (cnt) counts the number of cycles the ac output was one. this filter is deactivated if confn.flen equals 0. if the filter is enabled, the hysteresis value field hys in the confn register (confn.hys) can be used to define a hysteresis value. the hysteresis value should be chosen so that: 2 flen 2 ---------------- hys
646 32099a?avr32?06/09 at32uc3l the filter function is defined by: the filtering algorithm is explained in figure 27-3 . 2 flen measurements are sampled. if lthe number of measurements that are zero is less than (2 flen /2 - hys), the filtered result is zero. if lthe number of measurements that are one is more than (2 flen /2 + hys), the filtered result is one. otherwise, the result is unchanged. figure 27-3. the filtering algorithm 27.6.5 interrupt generation the interrupt request will be generated if the corresponding bit in the interrupt mask register (imr) is set. bits in imr are set by writing a one to the corresponding bit in the interrupt enable register (ier), and cleared by writing a one to the corresponding bit in the interrupt disable register (idr). the interrupt request remains acti ve until the corresponding bit in isr is cleared by writing a one to the corresponding bit in the interrupt status clear register (icr). 27.6.6 peripheral event generation the acifb can be set up so that certain conversion results notify other parts of the device via the peripheral event system. refer to section 27.6.2.3 and section 27.6.3.3 for information on which conversion results can generate events, a nd how to configure the acifb to achieve this. zero or one event will be generated per conversion. 27.7 peripheral event triggers peripheral events from other modules can trigge r conversions in the acifb. all channels that are set up in event triggered single measurement mode will be started si multaneously when a peripheral event is received. channels that are operating in continuous measurement mode or user triggered single measurement mode will be unaffected by the received event. the soft- ware can still operate these channels indepen dently of channels in event triggered single measurement mode. cnt 2 flen 2 --------------- - hys + ?? ?? comp ? 1 = 2 flen 2 ---------------- hys + ?? ?? cnt 2 flen 2 --------------- - h ? ys ?? ?? > comp unchanged ? cnt 2 flen 2 ---------------- h ? ys ?? ?? comp ? < 0 = 2 flen 2 flen 2 hys hys ?result=0" ?result=1" result = unchanged 0
647 32099a?avr32?06/09 at32uc3l a peripheral event will trigger one or more conversions, in normal or window mode. 27.8 ac test mode by writing the analog comparator test mode (cr.actest) bit to one, the outputs from the acs are overridden by the value in the test register (tr), see figure 27-1 . this is useful for software development.
648 32099a?avr32?06/09 at32uc3l 27.9 user interface note: 1. the reset values for these registers are device specific. please refer to the module configuration section at the end of this chapter. table 27-2. acifb register memory map offset register register name access reset 0x00 control register ctrl read/write 0x00000000 0x04 status register sr read-only 0x00000000 0x10 interrupt enable register ier write-only 0x00000000 0x14 interrupt disable register idr write-only 0x00000000 0x18 interrupt mask register imr read-only 0x00000000 0x1c interrupt status register isr read-only 0x00000000 0x20 interrupt status clear register icr write-only 0x00000000 0x24 test register tr read/write 0x00000000 0x30 parameter register parameter read-only - (1) 0x34 version register version read-only - (1) 0x80 window0 configuration register confw0 read/write 0x00000000 0x84 window1 configuration register confw1 read/write 0x00000000 0x88 window2 configuration register confw2 read/write 0x00000000 0x8c window3 configuration regi ster confw3 read/write 0x00000000 0xd0 ac0 configuration register conf0 read/write 0x00000000 0xd4 ac1 configuration register conf1 read/write 0x00000000 0xd8 ac2 configuration register conf2 read/write 0x00000000 0xdc ac3 configuration register conf3 read/write 0x00000000 0xe0 ac4 configuration register conf4 read/write 0x00000000 0xe4 ac5 configuration register conf5 read/write 0x00000000 0xe8 ac6 configuration register conf6 read/write 0x00000000 0xec ac7 configuration register conf7 read/write 0x00000000
649 32099a?avr32?06/09 at32uc3l 27.9.1 control register name: ctrl access type: read/write offset: 0x00 reset value: 0x00000000 ? sut: startup time analog comparator startup time = . each time an ac is enabled, the ac comparison will be enabled after the startup time of the ac. ? actest: analog comparator test mode 0: the analog comparator outputs feeds the channel logic in acifb. 1: the analog comparator outputs ar e bypassed with the ac test register. ? estart: peripheral event start single conversion writing a zero to this bit has no effect. writing a one to this bit starts a conversion and can be used for test purposes. this bit is cleared when conversion is done. this bit is set when an enabled peripheral event is received. ? ustart: user start single conversion writing a zero to this bit has no effect. writing a one to this bit starts a single measurement mode conversion. this bit is cleared when conversion is done. ? eventen: peripheral event trigger enable 0: a peripheral event will not trigger a conversion. 1: enable conversion triggered by a peripheral event. ? en: acifb enable 0: the acifb is disabled. 1: the acifb is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ------ sut[9:8] 15 14 13 12 11 10 9 8 sut[7:0] 76543210 actest - estart ustart - - eventen en sut f gclk ---------------- -
650 32099a?avr32?06/09 at32uc3l 27.9.2 status register name: sr access type: read-only offset: 0x04 reset value: 0x00000000 ? wfcsn: window mode current status this bit is cleared when the common input voltage is outside the window. this bit is set when the common input voltage is inside the window. ? acrdyn: acn ready this bit is cleared when the ac output (acout) is not ready. this bit is set when the ac output (acout) is ready, ac is enabled and its startup time is over. ? accsn: acn current comparison status this bit is cleared when v inp is currently lower than v inn this bit is set when v inp is currently greater than v inn. 31 30 29 28 27 26 25 24 ----wfcs3wfcs2wfcs1wfcs0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 acrdy7 accs7 acrdy6 accs6 acrdy5 accs5 acrdy4 accs4 76543210 acrdy3 accs3 acrdy2 accs2 acrdy1 accs1 acrdy0 accs0
651 32099a?avr32?06/09 at32uc3l 27.9.3 interrupt enable register name: ier access type: write-only offset: 0x10 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 - - - - wfint3 wfint2 wfint1 wfint0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 sutint7 acint7 sutint6 acint6 sutint5 acint5 sutint4 acint4 76543210 sutint3 acint3 sutint2 acint2 sutint1 acint1 sutint0 acint0
652 32099a?avr32?06/09 at32uc3l 27.9.4 interrupt disable register name: idr access type: write-only offset: 0x14 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 - - - - wfint3 wfint2 wfint1 wfint0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 sutint7 acint7 sutint6 acint6 sutint5 acint5 sutint4 acint4 76543210 sutint3 acint3 sutint2 acint2 sutint1 acint1 sutint0 acint0
653 32099a?avr32?06/09 at32uc3l 27.9.5 interrupt mask register name: imr access type: read-only offset: 0x18 reset value: 0x00000000 ?wfint n: window mode interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. ?sutint n: ac n startup time interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. ? acint n: ac n interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. this bit is cleared when the corresponding bit in idr is written to one. this bit is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 - - - - wfint3 wfint2 wfint1 wfint0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 sutint7 acint7 sutint6 acint6 sutint5 acint5 sutint4 acint4 76543210 sutint3 acint3 sutint2 acint2 sutint1 acint1 sutint0 acint0
654 32099a?avr32?06/09 at32uc3l 27.9.6 interrupt status register name: isr access type: read-only offset: 0x1c reset value: 0x00000000 ? wfintn: window mode interrupt status 0: no window mode interrupt is pending. 1: window mode interrupt is pending. this bit is cleared when the corresponding bit in icr is written to one. this bit is set when the corresponding channel pair operating in window mode generated an interrupt. ? sutintn: acn startup time interrupt status 0: no startup time interrupt is pending. 1: startup time interrupt is pending. this bit is cleared when the corresponding bit in icr is written to one. this bit is set when the startup time of the corresponding ac has passed. ? acintn: acn interrupt status 0: no normal mode interrupt is pending. 1: normal mode interrupt is pending. this bit is cleared when the corresponding bit in icr is written to one. this bit is set when the corresponding channel generated an interrupt. 31 30 29 28 27 26 25 24 - - - - wfint3 wfint2 wfint1 wfint0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 sutint7 acint7 sutint6 acint6 sutint5 acint5 sutint4 acint4 76543210 sutint3 acint3 sutint2 acint2 sutint1 acint1 sutint0 acint0
655 32099a?avr32?06/09 at32uc3l 27.9.7 interrupt status clear register name: icr access type: write-only offset: 0x20 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bitin this register will clear the corresponding bit in isr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 - - - - wfint3 wfint2 wfint1 wfint0 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 sutint7 acint7 sutint6 acint6 sutint5 acint5 sutint4 acint4 76543210 sutint3 acint3 sutint2 acint2 sutint1 acint1 sutint0 acint0
656 32099a?avr32?06/09 at32uc3l 27.9.8 test register name: tr access type: read/write offset: 0x24 reset value: 0x00000000 ? actestn: ac output override value if ctrl.actest is set, the acn output is overridden with the value of actestn. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 actest7 actest6 actest5 actest4 a ctest3 actest2 actest1 actest0
657 32099a?avr32?06/09 at32uc3l 27.9.9 parameter register name: parameter access type: read-only offset: 0x30 reset value: - ? wimpln: window pair n implemented 0: window pair not implemented. 1: window pair implemented. ? acimpln: analog comparator n implemented 0: analog comparator not implemented. 1: analog comparator implemented. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - - - wimpl3 wimpl2 wimpl1 wimpl0 15 14 13 12 11 10 9 8 -------- 76543210 acimpl7 acimpl6 acimpl5 acimpl4 acimpl3 acimpl2 acimpl1 acimpl0
658 32099a?avr32?06/09 at32uc3l 27.9.10 version register name: version access type: read-only offset: 0x34 reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
659 32099a?avr32?06/09 at32uc3l 27.9.11 window configuration register name: confwn access type: read/write offset: 0x80,0x84,0x88,0x8c reset value: 0x00000000 ? wfen: window mode enable 0: the window mode is disabled. 1: the window mode is enabled. ? weven: window event enable 0: event from awout is disabled. 1: event from awout is enabled. ? wevsrc: event source sel ection for window mode 00: event on acwout rising edge. 01: event on acwout falling edge. 10: event on awout rising or falling edge. 11: reserved. ? wis: window mode interrupt settings 00: window interrupt as soon as the input voltage is inside the window. 01: window interrupt as soon as the input voltage is outside the window. 10: window interrupt on toggle of window compare output. 11: window interrupt when evaluation of input voltage is done. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------wfen 15 14 13 12 11 10 9 8 - - - - - weven wevsrc 7654321 0 ------ wis
660 32099a?avr32?06/09 at32uc3l 27.9.12 ac configuration register name: confn access type: read/write offset: 0xd0,0xd4,0xd8,0xdc,0xe0,0xe4,0xe8,0xec reset value: 0x00000000 ? flen: filter length 000: filter off. n: number of samples to be averaged =2 n . ? hys: hysteresis value 0000: no hysteresis. 1111: max hysteresis. ? evenn: event enable negative 0: do not output event when acout is zero. 1: output event when acout is zero. ? evenp: event enable positive 0: do not output event when acout is one. 1: output event when acout is one. ? inselp: positive input select 00: acpn pin selected. 01: reserved. 10: reserved. 11: reserved. ? inseln: negative input select 00: acnn pin selected. 01: acrefn pin selected. 10: reserved. 11: reserved. ?mode: mode 00: off. 01: continuous measurement mode. 10: user triggered single measurement mode. 11: event triggered single measurement mode. 31 30 29 28 27 26 25 24 -flen hys 23 22 21 20 19 18 17 16 - - - - - - evenn evenp 15 14 13 12 11 10 9 8 - - - - inselp inseln 7654321 0 -- mode -- is
661 32099a?avr32?06/09 at32uc3l ? is: interrupt settings 00: comparator interrupt when as v inp > v inn . 01: comparator interrupt when as v inp < v inn . 10: comparator interrupt on toggle of analog comparator output. 11: comparator interrupt when comparison of v inp and v inn is done.
662 32099a?avr32?06/09 at32uc3l 27.10 module configuration the specific configuration for each acifb instan ce is listed in the fo llowing tables.the module bus clocks listed here are conn ected to the system bus clocks. refer to the power manager chapter for details. table 27-3. acifb configuration feature acifb number of channels 8 table 27-4. module clock name module name clock name acifb clk_acifb table 27-5. register reset values register reset value version 0x00000202 parameter 0x000f00ff
663 32099a?avr32?06/09 at32uc3l 28. capacitive touch module (cat) rev: 2.0.0.0 28.1 features ? qtouch? method allows n touch sensors to be implemented using 2n physical pins ? qmatrix? method allows x by y matrix of sensors to be implemented using (x+2y) physical pins ? one autonomous qtouch? sensor operates without cpu intervention ? interfaced with peripheral dma cont roller to reduce processor overhead ? external synchronization to reduce 50 or 60 hz mains interference ? spread spectrum sensor drive capability 28.2 overview the capacitive touch module (cat) senses touc h on external capacitive touch sensors. capac- itive touch sensors use no external mechan ical components, and therefore demand less maintenance in the user application. the module implements the qtouch method of capturing signals from capacitive touch sensors. the qtouch method is generally suitable for small numbers of sensors since it requires 2 physi- cal pins per sensor. the module also implements the qmatrix method, which is more appropriate for large numbers of sensors since it allows an x by y matrix of sensors to be imple- mented using only (x+2y) physical pins. the module allows methods to function together, so n touch sensors and an x by y matrix of sensors can be implemented us ing (2n+x+2y) physical pins. in addition, the module allows sensors using the qtouch method to be divided into two groups. each qtouch group can be configured with different properties. this eases the implementation of multiple kinds of controls such as push buttons, wheels, and sliders. the module also implements one autonomous qtouch sensor that is capable of detecting touch or proximity without cpu interventio n. this allows proximity or ac tivation detection in low-power sleep modes.
664 32099a?avr32?06/09 at32uc3l 28.3 block diagram figure 28-1. cat block diagram interface registers peripheral bus finite state machi ne capacitor charge and di scharge sequence generator counters csan smp i/o control l er pi ns di scharge current sources di s yn analog comparators peripheral event system clk_cat analog comparator interface sync capacitive touch module (cat) csbn gclk_cat vdiven note: italicized signals and blocks are used only for qmat ri x operation
665 32099a?avr32?06/09 at32uc3l 28.4 i/o lines description 28.5 product dependencies in order to use the cat module, other parts of the system must be configured correctly, as described below. 28.5.1 i/o lines the cat pins may be multiplexed with other peripherals. the user must first program the i/o controller to give control of the pins to the cat module. in qmatrix mode, the y lines must be driven by the cat and analog comparators sense the voltage on the y lines. thus, the cat (not the analog comparator interface) must be the selected function for the y lines in the i/o controller. by writing ones and zeros to bits in the pin mode registers (pinmodex), most of the cat pins can be individually selected to implement the qtouch method or the qmatrix method. each pin has a different name and function depending on whether it is implementing the qtouch method or the qmatrix method. the following table shows the pin names for each method and the bits in the pinmodex registers which control the selection of the qtouch or qmatrix method. table 28-1. i/o lines description name description type csan capacitive sense a line n i/o csbn capacitive sense b line n i/o dis discharge current control (only used for qmatrix) analog smp smp line (only used for qmatrix) output sync synchronize signal input vdiven voltage divider enable (only used for qmatrix) output table 28-2. pin selection guide cat module pin name qtouch method pin name qmatrix method pin name selection bit in pinmodex register csa0 sns0 x0 sp0 csb0 snsk0 x1 sp0 csa1 sns1 y0 sp1 csb1 snsk1 yk0 sp1 csa2 sns2 x2 sp2 csb2 snsk2 x3 sp2 csa3 sns3 y1 sp3 csb3 snsk3 yk1 sp3 csa4 sns4 x4 sp4 csb4 snsk4 x5 sp4 csa5 sns5 y2 sp5
666 32099a?avr32?06/09 at32uc3l 28.5.2 clocks the clock for the cat module, clk_cat, is gen erated by the power manager (pm). this clock is turned on by default, and can be enabled and disabled in the pm. the user must ensure that clk_cat is enabled befo re using the cat module. qmatrix operations also require the cat generic clock, gclk_cat. this generic clock is gener- ated by the system control interface (scif), and is shared between the cat and the analog comparator interface. the user must ensure that the gclk_cat is enabled in the scif before using qmatrix functionality in the cat module. for proper qmatrix operation, the frequency of gclk_cat must be less than half the frequency of clk_cat. if only qtouch functionality is used, then gclk_cat is unnecessary. 28.5.3 interrupts the cat interrupt request line is connected to the interrupt controller. using cat interrupts requires the interrupt controller to be programmed first. csb5 snsk5 yk2 sp5 csa6 sns6 x6 sp6 csb6 snsk6 x7 sp6 csa7 sns7 y3 sp7 csb7 snsk7 yk3 sp7 csa8 sns8 x8 sp8 csb8 snsk8 x9 sp8 csa9 sns9 y4 sp9 csb9 snsk9 yk4 sp9 csa10 sns10 x10 sp10 csb10 snsk10 x11 sp10 csa11 sns11 y5 sp11 csb11 snsk11 yk5 sp11 csa12 sns12 x12 sp12 csb12 snsk12 x13 sp12 csa13 sns13 y6 sp13 csb13 snsk13 yk6 sp13 csa14 sns14 x14 sp14 csb14 snsk14 x15 sp14 csa15 sns15 y7 sp15 csb15 snsk15 yk7 sp15 csa16 sns16 x16 sp16 csb16 snsk16 x17 sp16 table 28-2. pin selection guide cat module pin name qtouch method pin name qmatrix method pin name selection bit in pinmodex register
667 32099a?avr32?06/09 at32uc3l 28.5.4 peripheral events the cat peripheral events are connected via the peripheral event system. refer to the periph- eral event system chapter for details. 28.5.5 peripheral direct memory access the cat module provides handshake capability for a peripheral dma controller. one hand- shake controls transfers from the acquired count register (acount) to memory. a second handshake requests burst lengths for each (x,y ) pair to the matrix burst length register (mblen) when using the qmatrix acquisition method. the peripheral dma controller must be configured properly and enabled in order to perform direct memory access transfers to/from the cat module. 28.5.6 analog comparators when the cat module is performing qmatrix acquisiti on, it requires that on-chip analog compar- ators be used as part of the process. these analog comparators are not controlled directly by the cat module, but by a separate analog comparator (ac) interface. this interface must be configured properly and enabled before the cat module is used. this includes configuring the generic clock input for the analog comparators to the proper sampling frequency. the cat will automatically use the ne gative peripheral events from the ac interface on every y pin in qmatrix mode. when qmatrix acquisition is used the analog comparator corresponding to the selected y pins must be enabled and converting continuously, using the y pin as the positive reference and the acrefn as negative reference. 28.5.7 debug operation when an external debugger forces the cpu into debug mode, the cat continues normal opera- tion. if the cat is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper operation or data loss may result during debugging. 28.6 functional description 28.6.1 acquisition types the cat module can perform three types of qtouc h acquisition from capacitive touch sensors: autonomous qtouch (one sensor only), qtouch group a, and qtouch group b. the cat mod- ule can also perform qmatrix acquisition. each ty pe of acquisition has an associated set of pin selection and configuratio n registers that allow a large degree of flexibility. the following schematic diagrams show typica l hardware connections for qtouch and qmatrix sensors, respectively:
668 32099a?avr32?06/09 at32uc3l figure 28-2. cat touch connections figure 28-3. cat matrix connections in order to use the autonomous qtouch detection capability, the user must first set up the autonomous touch pin select register (atpin s) and autonomous touch configuration regis- ters (atcfg0 through 3) with appropriate va lues. the module can then be enabled using the control register (ctrl). after the module is enabled, the module will acquire data from the autonomous qtouch sensor and use it to dete rmine whether the sensor is activated. the active/inactive status of the autonomous qtouch sensor is reported in the status register (sr), and it is also possible to configure the cat to generate an interrupt whenever the status changes. the module will continue acquiring autonomous qtouch sensor data and updating autonomous qtouch status until the module is disabled or reset. in order to use the qmatrix, qtouch group a, or qtouch group b acquisi tion capabilities, it is first necessary to set up the appropriate pin mode registers (pinmode0 and pinmode1) and avr32 chip qtouch sensor cs (sense capacitor) snskn snsn avr32 chip cs0 (sense capacitor) x3 yk0 qmatrix sensor array x6 x7 x2 y0 yk1 y1 cs1 (sense capacitor) smp rsmp1 rsmp0 vdiven dis rdis acrefn ra rb note: if the cat internal current sources will be enabled, the smp signal and rsmp resistors should not be included in the design. if the cat internal current sources will not be enabled, the dis signal and rdis resistor should not be included in the design.
669 32099a?avr32?06/09 at32uc3l configuration registers (mgcfg0, mgcfg1, tgacfg0, tgacfg1, tgbcfg0, and tgbcfg1). the module must then be enabled using the ctrl register. in order to initiate acquisition, it is necessary to perform a write to the acquisition initiation and selection register (aisr). the specific value written to aisr det ermines which type of acquisition will be per- formed: qmatrix, qtouch group a, or qtouch group b. the cpu can initiate acquisition by writing to the aisr. while qmatrix, qtouch group a, or qtouch group b acquisition is in progress, the module col- lects count values from the sensors and buffers them. availability of acquired count data is indicated by the acquisition read y (acready) bit in the status register (sr). the cpu or the peripheral dma controller can then read the acquired counts from the acount register. because the cat module is config ured with peripheral dma contro ller capability that can trans- fer data from memory to mblen and from acount to memory, the peripheral dma controller can perform long acquisition sequences and stor e results in memory wit hout cpu intervention. 28.6.2 prescaler and charge length each qtouch acquisition type (autonomous qtouch, qtouch group a, and qtouch group b) has its own prescaler. each qtouch prescaler divides down the clk_cat clock to an appropri- ate sampling frequency for its particular acquisition type. typical frequencies are 1mhz for qtouch acquisition and 4mhz for qmatrix burst timing control. each qtouch prescaler is controlled by the div field in the appropriate configuration register 0 (atcfg0, tgacfg0, or tgbcfg0). the qmatrix bur st timing prescaler is controlled by the div field in mgcfg0. each prescaler uses the following formula to generate the sampling clock: sampling clock = clk_cat / (2(div+1)) the capacitive sensor charge length, discharge length, and settle length can be determined for each acquisition type using the ch len, dilen, and selen fields in configuration registers 0 and 1. the lengths are specified in terms of prescaler clocks. in addition, the qmatrix cx dis- charge length can be determined using the cxdilen field in mgcfg2. for qmatrix acquisition, the duration of chlen should not be set to the same value as the period of any periodic signal on any other pin. if the duration of chlen is the same as the period of a signal on another pin, it is likely that the other sig nal will significantly affect measure- ments due to stray capacitive coupling. for exam ple, if a 1 mhz signal is generated on another pin of the chip, then chlen should not be 1 microsecond. for the qmatrix method, burst and capture lengths are set for each (x,y) pair by writing the desired length values to the mblen register. the write must be done before each x line can start its acquisition and is indi cated by the status bit mblreq in the status register (sr). a dma handshake interface is also connected to this status bit to reduce cpu overhead during qmatrix acquisitions. four burst lengths (burst0..3) can be written at one time into the mblen register. if the cur- rent configuration uses y lines larger than y3 the register has to be written a second time. the first write to mblen specifies the burst length for y lines 0 to 3 in the burst0 to burst3 fields, respectively. the seco nd write specifies the burst length fo r y lines 4 to 7 in fields burst0 to burst3, respectively, and so on. the y and yk pins remain clamped to ground apart from the specified number of burst pulses, when charge is transferred and captured into the sampling capacitor.
670 32099a?avr32?06/09 at32uc3l 28.6.3 capacitive count acquisition for the qmatrix, qtouch group a, and qtouch group b types of acquisition, the module acquires count values from the sensors, buffers them, and makes them available for reading in the acount register. further processing of the count values must be performed by the cpu. when the module performs qmatrix acquisition us ing multiple y lines, it starts the capture for each y line at the appropriate time in the burst sequence so that all captures finish simultane- ously. for example, suppose that an acquisiti on is performed on y0 and y1 with burst0=53 and burst1=60. the module will first toggle the x line 7 times while capturing on y1 while y0 and yk0 are clamped to ground. th e module will then toggle the x line 53 times while capturing on both y1 and y0. 28.6.4 autonomous qtouch for autonomous qtouch, a complete detection algorithm is implemented within the cat mod- ule. the additional parameters needed to control the autonomous qtouch detection algorithm must be specified by the user in the atcfg2 and atcfg3 registers. autonomous qtouch sensitivity and out-of-touch sensitivity can be adjusted with the sense and outsens fields, respectively, in atcfg2. each field accepts values from one to 255 where 255 is the least sensitive setting. the value in the outsens field should be smaller than the value in the sense field. to avoid false positives a detect integration filtering technique can be used. the number of suc- cessive detects required is specified in the filter field of the atcfg2 register. to compensate for changes in capacitance the cat can recalibrate the autonomous qtouch sensor periodically. the timing of this calibration is done with the ndrift and pdrift fields in the configuration register, atcfg3. it is recommended that the pdrift value is smaller than the ndrift value. the autonomous qtou ch sensor will also recalibrate if the count value goes too far positive beyond a threshold. this positive recalibration th reshold is specified by the pthr field in the atcfg3 register. the following block diagram shows the sequence of acquisition and processing operations used by the cat module. the aisr written bit is in ternal and not visible in the user interface.
671 32099a?avr32?06/09 at32uc3l figure 28-4. cat acquisition and processing sequence 28.6.5 spread spectrum sensor drive to reduce electromagnetic comp atibility issues, the capacitive sensors can be driven with a spread spectrum signal. to enable spread spectr um drive for a specific acquisition type, the user must write a one to the spread bit in the appropriate configuration register 1 (mgcfg1, atcfg1, tgacfg1, or tgbcfg1). during spread spectrum operation, the length of each pulse within a burst is varied in a deter- ministic pattern, so that the exact same burst pattern is used for a specific burst length. the maximum spread is determined by the maxdev field in the spread spectrum configuration register (sscfg) register. the prescaler divisor is varied in a sawtooth pattern from (div- maxdev) to (div+maxdev) and then back to (div-maxdev). for example, if div is 8 and maxdev is 3, the prescaler divisor will have the following sequence: 8,9,10,11,5,6,7,8,9,10,11,5,6,etc. idle acquire autonomous touch count acquire counts update autonomous touch detection algorithm wait for all acquired counts to be transferred aisr written flag set? yes no clear aisr written flag no yes autonomous touch enabled (aten)?
672 32099a?avr32?06/09 at32uc3l 28.6.6 synchronization to prevent interference from the 50 or 60 hz mains line the cat can trigger acquisition on the sync signal. the sync signal s hould be derived from the mains line. the acquisition will trig- ger on a falling edge of this signal. to enable sy nchronization for a specif ic acquisition type, the user must write a one to the sync bit in the appropriate configuration register 1 (mgcfg1, atcfg1, tgacfg1, or tgbcfg1). for qmatrix acquisition, all x lines must be sampled at a specific phase of the noise signal for the synchronization to be effective. this can be accomplished by the synchronization timer, which is enabled by writing a non-zero value to the synctim field in the mgcfg2 register. this ensures that the start of the acquisition of eac h x line is spaced at regular intervals, defined by the synctim field. 28.6.7 resistive drive by default, the cat pins are driven with normal i/o drive properties. some of the csa and csb pins can optionally drive with a 1k output resi stance for improved emc. the pins that have this capability are listed in the m odule configuration section. 28.6.8 discharge current source the device integrates a discharge current source , which can be used to discharge the sampling capacitors during the qmatrix measurement phase. the discharge current source is enabled by writing the en bits in the discharge current s ource (dics) register to one. this enables an internal reference voltage, which can be the internal 1.1v band gap voltage or vddio/2, as selected by the intvrefsel bit in the dics regi ster. if the dics.intrefsel bit is one, the ref- erence voltage is applied across an internal resistor. otherwise the voltage is applied to the dis pin, and an external resistor must be connected between dis and ground. this allows the dis- charge current to be programmed between 2 and 20 ua. the reference current is mirrored to each y-pin if the corresponding bit is written to one in the dics.sources field. the reference current can be fine-tuned by writin g the trim value to the dics.trim field, allow- ing the user to compensate e.g. for temperature gradients in the resistance value.
673 32099a?avr32?06/09 at32uc3l 28.7 user interface table 28-3. cat register memory map offset register register name access reset 0x00 control register ctrl read/write 0x00000000 0x04 autonomous touch pin selection register atpins read/write 0x00000000 0x08 pin mode register 0 pinmode0 read/write 0x00000000 0x0c pin mode register 1 pinmode1 read/write 0x00000000 0x10 autonomous touch configuration register 0 atcfg0 read/write 0x00000000 0x14 autonomous touch configuration register 1 atcfg1 read/write 0x00000000 0x18 autonomous touch configuration register 2 atcfg2 read/write 0x00000000 0x1c autonomous touch configuration register 3 atcfg3 read/write 0x00000000 0x20 touch group a configuration register 0 tgacfg0 read/write 0x00000000 0x24 touch group a configuration register 1 tgacfg1 read/write 0x00000000 0x28 touch group b configuration register 0 tgbcfg0 read/write 0x00000000 0x2c touch group b configuration register 1 tgbcfg1 read/write 0x00000000 0x30 matrix group configuration register 0 mgcfg0 read/write 0x00000000 0x34 matrix group configuration register 1 mgcfg1 read/write 0x00000000 0x38 matrix group configuration register 2 mgcfg2 read/write 0x00000000 0x3c status register sr read-only 0x00000000 0x40 status clear register scr write-only - 0x44 interrupt enable register ier write-only - 0x48 interrupt disable register idr write-only - 0x4c interrupt mask register imr read-only 0x00000000 0x50 acquisition initiation and select ion register aisr read/write 0x00000000 0x54 acquired count register acount read-only 0x00000000 0x58 matrix burst length register mblen write-only - 0x5c discharge current source register dics read/write 0x00000000 0x60 spread spectrum configuration register sscfg read/write 0x00000000 0x64 csa resistor control register csares read/write 0x00000000 0x68 csb resistor control register csbres read/write 0x00000000 0x6c autonomous touch base count register atbase read-only 0x00000000 0x70 autonomous touch current count register atcurr read-only 0x00000000 0x80 analog comparator shift offset register 0 acshi0 read/write 0x00000000 0x84 analog comparator shift offset register 1 acshi1 read/write 0x00000000 0x88 analog comparator shift offset register 2 acshi2 read/write 0x00000000 0x8c analog comparator shift offset register 3 acshi3 read/write 0x00000000 0x90 analog comparator shift offset register 4 acshi4 read/write 0x00000000 0x94 analog comparator shift offset register 5 acshi5 read/write 0x00000000
674 32099a?avr32?06/09 at32uc3l 0x98 analog comparator shift offset register 6 acshi6 read/write 0x00000000 0x9c analog comparator shift offset register 7 acshi7 read/write 0x00000000 0xf8 parameter register parameter read-only 0xfc version register version read-only table 28-3. cat register memory map offset register register name access reset
675 32099a?avr32?06/09 at32uc3l 28.7.1 control register name: ctrl access type: read/write offset: 0x00 reset value: 0x00000000 ? swrst: software reset writing a zero to this bit has no effect. writing a one to this bit resets the module. the module will be disabled after the reset. this bit always reads as zero. ? en: module enable 0: module is disabled. 1: module is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 swrst------en
676 32099a?avr32?06/09 at32uc3l 28.7.2 autonomous touch pin selection register name: atpins access type: read/write offset: 0x04 reset value: 0x00000000 ? aten: autonomous touch enable 0: autonomous qtouch acquisitio n and detection is disabled. 1: autonomous qtouch acquisition and detection is enabled using the sense pair specified in atsp. ? atsp: autonomous touch sense pair selects the sense pair that will be used by the autonomous qtouch sensor. a value of n will select sense pair n (csan and csbn pins). 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------aten 76543210 --- atsp
677 32099a?avr32?06/09 at32uc3l 28.7.3 pin mode registers 0 and 1 name: pinmode0 and pinmode1 access type: read/write offset: 0x08, 0x0c reset value: 0x00000000 ? sp: sense pair mode selection each sp[n] bit determines the operation mode of sens e pair n (csan and csbn pi ns). the (pinmode1.sp[n] pinmode0.sp[n]) bits have the following definitions: 00: sense pair n disabled. 01: sense pair n is assigned to qtouch group a. 10: sense pair n is assigned to qtouch group b. 11: sense pair n is assigned to the qmatrix group. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - sp[16] 15 14 13 12 11 10 9 8 sp[15:8] 76543210 sp[7:0]
678 32099a?avr32?06/09 at32uc3l 28.7.4 autonomous touch configuration register 0 name: atcfg0 access type: read/write offset: 0x10 reset value: 0x00000000 ? div: clock divider the prescaler is used to ensure that the clk_cat clock is divided to around 1 mhz to produce the sampling clock.the prescaler uses the following formula to generate the sampling clock: sampling clock = clk_cat / (2(div+1)) ? chlen: charge length for the autonomous qtouch sensor, specifies how many sample clock cycles should be used for transferring charge to the sense capacitor. ? selen: settle length for the autonomous qtouch sensor, specifies how many sample cl ock cycles should be used for settling after charge transfer. 31 30 29 28 27 26 25 24 div[15:8] 23 22 21 20 19 18 17 16 div[7:0] 15 14 13 12 11 10 9 8 chlen 76543210 selen
679 32099a?avr32?06/09 at32uc3l 28.7.5 autonomous touch configuration register 1 name: atcfg1 access type: read/write offset: 0x14 reset value: 0x00000000 ? dishift: discharge shift for the autonomous qtouch sensor, specifies how many bits the dilen field should be shifted before using it to determine the discharge time. ? sync: sync pin for the autonomous qtouch sensor, specifie s that acquisition shall begin when a falling edge is received on the sync line. ? spread: spread spectrum sensor drive for the autonomous qtouch sensor, specifies that spread spectrum sensor drive shall be used. ? dilen: discharge length for the autonomous qtouch sensor, specifies how many sample clock cycles the cat s hould use to discharge the capacitors before charging them. ? max: maximum count for the autonomous qtouch sensor, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - dishift - sync spread 23 22 21 20 19 18 17 16 dilen 15 14 13 12 11 10 9 8 max[15:8] 76543210 max[7:0]
680 32099a?avr32?06/09 at32uc3l 28.7.6 autonomous touch configuration register 2 name: atcfg2 access type: read/write offset: 0x18 reset value: 0x00000000 ? filter: autonomous touch filter setting for the autonomous qtouch sensor, specifies how many positive detects in a row the cat needs to have on the autonomous qtouch sensor before reporting it as a touch. a filter val ue of 0 is not allowed and will result in undefined behavior. ? outsens: out-of-touch sensitivity for the autonomous qtouch sensor, specifies how s ensitive the out-of-touch detector should be. ? sense: sensitivity for the autonomous qtouch sensor, specifies how sensitive the touch detector should be. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 -filter 15 14 13 12 11 10 9 8 outsens 76543210 sense
681 32099a?avr32?06/09 at32uc3l 28.7.7 autonomous touch configuration register 3 name: atcfg3 access type: read/write offset: 0x1c reset value: 0x00000000 ? pthr: positive recalibration threshold for the autonomous qtouch sensor, specifies how far a sensor?s signa l must move in a positive direction from the reference in order to cause a recalibration. ? pdrift: positive drift compensation for the autonomous qtouch sensor, specifies how often a positive drift compensation shou ld be performed. when this field is zero, positive drift compensation will never be performed. when this field is non-zero, the positive drift compensation time interval is given by the following formula: tpdrift = pdrift * 65536 * (sample clock period) ? ndrift: negative drift compensation for the autonomous qtouch sensor, specifies how often a negative drift compensation should be performed. when this field is zero, negative drift compensation will never be performed. when this field is non-zero, the negative drift compensation time interval is given by the following formula: tndrift = ndrift * 65536 * (sample clock period) with the typical sample clock frequency of 1 mhz, p drift and ndrift can be set from 0.066 seconds to 16.7 seconds with 0.066 second resolution. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 pthr 15 14 13 12 11 10 9 8 pdrift 76543210 ndrift
682 32099a?avr32?06/09 at32uc3l 28.7.8 touch group x configuration register 0 name: tgxcfg0 access type : read/write offset: 0x20, 0x28 reset value: 0x00000000 ? div: clock divider the prescaler is used to ensure that the clk_cat clock is divided to around 1 mhz to produce the sampling clock.the prescaler uses the following formula to generate the sampling clock: sampling clock = clk_cat / (2(div+1)) ? chlen: charge length for the qtouch method, specifies how many sample clock cycles sh ould be used for transferring charge to the sense capacitor. ? selen: settle length for the qtouch method, specifies how many sample clock cycles should be used for se ttling after charge transfer. 31 30 29 28 27 26 25 24 div[15:8] 23 22 21 20 19 18 17 16 div[7:0] 15 14 13 12 11 10 9 8 chlen 76543210 selen
683 32099a?avr32?06/09 at32uc3l 28.7.9 touch group x configuration register 1 name: tgxcfg1 access type: read/write offset: 0x24, 0x2c reset value: 0x00000000 ? dishift: discharge shift for the sensors in qtouch group x, specif ies how many bits the dilen field should be shifted before using it to determine the discharge time. ? sync: sync pin for sensors in qtouch group x, specifies that acquisition shall begin when a falling edge is received on the sync line. ? spread: spread spectrum sensor drive for sensors in qtouch group x, specifies that spread spectrum sensor drive shall be used. ? dilen: discharge length for sensors in qtouch group x, specifies how many clock cycl es the cat should use to discharge the capacitors before charging them. ? max: touch maximum count for sensors in qtouch group x, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - - dishift - - sync spread 23 22 21 20 19 18 17 16 dilen 15 14 13 12 11 10 9 8 max[15:8] 76543210 max[7:0]
684 32099a?avr32?06/09 at32uc3l 28.7.10 matrix group configuration register 0 name: mgcfg0 access type: read/write offset: 0x30 reset value: 0x00000000 ? div: clock divider the prescaler is used to ensure that the clk_cat clock is divided to around 4 mhz to produce the burst timing clock.the prescaler uses the following formula to generate the burst timing clock: burst timing clock = clk_cat / (2(div+1)) ? chlen: charge length for qmatrix sensors, specifies how many burst prescaler cloc k cycles should be used for transferring charge to the sense capacitor. ? selen: settle length for qmatrix sensors, specifies how many burst prescaler cloc k cycles should be used for settling after charge transfer. 31 30 29 28 27 26 25 24 div[15:8] 23 22 21 20 19 18 17 16 div[7:0] 15 14 13 12 11 10 9 8 chlen 76543210 selen
685 32099a?avr32?06/09 at32uc3l 28.7.11 matrix group configuration register 1 name: mgcfg1 access type: read/write offset: 0x34 reset value: 0x00000000 ? dishift: discharge shift for qmatrix sensors, specifies how many bits the dilen field shou ld be shifted before using it to determine the discharge time. ? sync: sync pin for qmatrix sensors, specifies that acquisition shall begin when a falling edge is received on the sync line. ? spread: spread spectrum sensor drive for qmatrix sensors, specifies that spre ad spectrum sensor drive shall be used. ? dilen: discharge length for qmatrix sensors, specifies how many burst prescaler clock cycles the cat should use to discharge the capacitors at the beginning of a burst sequence. ? max: maximum count for qmatrix sensors, specifies how many counts the maximum acquisition should be. 31 30 29 28 27 26 25 24 - dishift - sync spread 23 22 21 20 19 18 17 16 dilen 15 14 13 12 11 10 9 8 max[15:8] 76543210 max[7:0]
686 32099a?avr32?06/09 at32uc3l 28.7.12 matrix group configuration register 2 name: mgcfg2 access type: read/write offset: 0x38 reset value: 0x00000000 ? acctrl: analog co mparator control when written to one, allows the cat to disable the analog co mparators when they are not needed. when written to zero, the analog comparators are always enabled. ? consen: consensus filter length for qmatrix sensors, specifies that disc harge will be terminated when consen out of the most recent 5 comparator samples are positive. for example, a value of 3 in the consen field will terminate discharge when 3 out of the most recent 5 comparator samples are positive. when consen has the default value of 0, discharge will be terminated immediately when the comparator output goes positive. ? cxdilen: cx capacitor discharge length for qmatrix sensors, specifies how many burst prescaler clock cy cles the cat should use to disc harge the cx capacitor at the end of each burst cycle. ? synctim: sync time interval when non-zero, determines the number of prescaled clock cycles between the start of the acquisition on each x line for qmatrix acquisition. 31 30 29 28 27 26 25 24 acctrl consen - 23 22 21 20 19 18 17 16 cxdilen 15 14 13 12 11 10 9 8 - synctim[11:8] 76543210 synctim[7:0]
687 32099a?avr32?06/09 at32uc3l 28.7.13 status register name: sr access type: read-only offset: 0x3c reset value: 0x00000000 ? acqdone: acquisition done 0: acquisition is not done (still in progress). 1: acquisition is complete. ? acready: acquired count data is ready 0: acquired count data is not available in the acount register. 1: acquired count data is available in the acount register. ? mblreq: matrix burst length required 0: the qmatrix acquisition does not require any burst lengths. 1: the qmatrix acquisition requires burst lengths for the current x line. ? atstate: autonomous touch sensor state 0: the autonomous qtouch sensor is not active. 1: the autonomous qtouch sensor is active. ? atsc: autonomous touch sensor status interrupt 0: no status change in t he autonomous qtouch sensor. 1: status change in the autonomous qtouch sensor. ? atcal: autonomous touch calibration ongoing 0: the autonomous qtouch sensor is not calibrating. 1: the autonomous qtouch sensor is calibrating. ? enabled: module enabled 0: the module is disabled. 1: the module is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------acqdoneacready 76543210 - - - mblreq atstate atsc atcal enabled
688 32099a?avr32?06/09 at32uc3l 28.7.14 status clear register name: scr access type: write-only offset: 0x40 reset value: - writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------acqdoneacready 76543210 - - - - - atsc atcal -
689 32099a?avr32?06/09 at32uc3l 28.7.15 interrupt enable register name: ier access type: write-only offset: 0x44 reset value: - writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------acqdoneacready 76543210 - - - - - atsc atcal -
690 32099a?avr32?06/09 at32uc3l 28.7.16 interrupt disable register name: idr access type: write-only offset: 0x48 reset value: - writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------acqdoneacready 76543210 - - - - - atsc atcal -
691 32099a?avr32?06/09 at32uc3l 28.7.17 interrupt mask register name: imr access type: read-only offset: 0x4c reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------acqdoneacready 76543210 - - - - - atsc atcal -
692 32099a?avr32?06/09 at32uc3l 28.7.18 acquisition initiation and selection register name: aisr access type: read/write offset: 0x50 reset value: 0x00000000 ? acqsel: acquisition type selection a write to this register initiates an acquisition of the following type: 00: qtouch group a. 01: qtouch group b. 10: qmatrix group. 11: undefined behavior. a read of this register will return the value that was previously written. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - 76543210 -acqsel
693 32099a?avr32?06/09 at32uc3l 28.7.19 acquired count register name: acount access type: read-only offset: 0x54 reset value: 0x00000000 ?y: y index the y index (for qmatrix method) associated with this count value. ? sporx: sensor pair or x index the sensor pair index (for qtouch method) or x index (for qmatrix method) associated with this count value. ? count: count value the signal (number of counts) acquired on the channel specified in the sporx and y fields. when multiple acquired count values are read from a qtouch acquisition, the y field will always be 0 and the sporx value will increase monotonically. for example, suppose a qtouch acqui sition is performed using sensor pairs sp1, sp4, and sp9. the first count read will have sporx=1, the second read will have sporx=4, and the third read will have sporx=9. when multiple acquired count values are read from a qmatri x acquisition, the sporx value will stay the same while y increases monotonically through all y values in the group. then sporx will increase to the next x value in the group. for example, a qmatrix acquisition with x=2,3 and y=4,7 would provid e count values in the following order: x=2 and y=4, then x=2 and y=7, then x=3 and y=4, and finally x=3 and y=7. 31 30 29 28 27 26 25 24 y 23 22 21 20 19 18 17 16 sporx 15 14 13 12 11 10 9 8 count[15:8] 76543210 count[7:0]
694 32099a?avr32?06/09 at32uc3l 28.7.20 matrix burst length register name: mblen access type: write-only offset: 0x58 reset value: - ? burstx: burst length x for qmatrix sensors, specifies how many times the switching se quence should be repeated before acquisition begins for each channel. each count in the burstx field sp ecifies 1 repeat of the switching sequence, so the actual burst length will be burst. before doing a qmatrix acquisition on one x line this register has to be written with the burst values for the current xy pairs . for each x line this register needs to be programmed with all the y va lues. if y values larger than 3 are used the register has to be written several times in order to specify all burst lengths. the status register bit mblreq is set to 1 when the cat is waiting for values to be written into this register. 31 30 29 28 27 26 25 24 burst0 23 22 21 20 19 18 17 16 burst1 15 14 13 12 11 10 9 8 burst2 76543210 burst3
695 32099a?avr32?06/09 at32uc3l 28.7.21 discharge current source register name: dics access type: read/write offset: 0x5c reset value: 0x00000000 ? fsources: force discharge current sources when fsources[n] is 0, the corres ponding discharge current source behavior depends on sources[n]. when fsources[n] is 1, the corresponding di scharge current source is forced to be enabled continuously. this is useful for testing or debugging but should not be done during normal acquisition. ? glen: global enable 0: the current source module is globally disabled. 1: the current source module is globally enabled. ? intvrefsel: internal vo ltage reference select 0: the voltage for the referenc e resistor is generated from the internal band gap circuit. 1: the voltage for the refere nce resistor is vddio/2. ? intrefsel: internal reference select 0: the reference current flows through an external resistor on the dis pin. 1: the reference current flows through the internal reference resistor. ? trim: reference current trimming this field is used to trim the discharge current. 0x00 corresponds to the minimum current value, and 0x1f corresponds to the maximum current value. ? sources: enable discharge current sources when sources[n] is 0, the corresponding discharge current source is disabled. when sources[n] is 1, the corresponding discharge current s ource is enabled at appropriate times during acquisition. 31 30 29 28 27 26 25 24 fsources[7:0] 23 22 21 20 19 18 17 16 glen----- intvrefsel intrefsel 15 14 13 12 11 10 9 8 --- trim 76543210 sources[7:0]
696 32099a?avr32?06/09 at32uc3l 28.7.22 spread spectrum configuration register name: sscfg access type: read/write offset: 0x60 reset value: 0x00000000 ? maxdev: maximum deviation when spread spectrum burst is enabled, maxdev indicates the maxi mum number of prescaled clock cycles the burst pulse will be extended or shortened. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 maxdev
697 32099a?avr32?06/09 at32uc3l 28.7.23 csa resistor control register name: csares access type: read/write offset: 0x64 reset value: 0x00000000 ? res: resistive drive enable when res[n] is 0, csa[n] has the same drive properties as normal i/o pads. when res[n] is 1, csa[n] has a nominal outpu t resistance of 1kohm during the burst phase. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - res[16] 15 14 13 12 11 10 9 8 res[15:8] 76543210 res[7:0]
698 32099a?avr32?06/09 at32uc3l 28.7.24 csb resistor control register name: csbres access type: read/write offset: 0x68 reset value: 0x00000000 ? res: resistive drive enable when res[n] is 0, csb[n] has the same drive properties as normal i/o pads. when res[n] is 1, csb[n] has a nominal outpu t resistance of 1kohm during the burst phase. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - res[16] 15 14 13 12 11 10 9 8 res[15:8] 76543210 res[7:0]
699 32099a?avr32?06/09 at32uc3l 28.7.25 autonomous touch base count register name: atbase access type: read-only offset: 0x6c reset value: 0x00000000 ? count: count value the base count currently stored by the autonomous touch sens or. this is useful for autonomous touch debugging purposes. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 count[15:8] 76543210 count[7:0]
700 32099a?avr32?06/09 at32uc3l 28.7.26 autonomous touch current count register name: atcurr access type: read-only offset: 0x70 reset value: 0x00000000 ? count: count value the current count acquired by the autonomous touch sensor. this is useful for autonomous touch debugging purposes. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 count[15:8] 76543210 count[7:0]
701 32099a?avr32?06/09 at32uc3l 28.7.27 analog comparator shift offset register x name: acshix access type: read/write offset: 0x80, 0x84, 0x88, 0x8c, 0x 90, 0x94, 0x98, and 0x9c reset value: 0x00000000 ? shival: shift offset value specifies the amount to shift the count value from each comparator. this al lows the offset of each comparator to be compensated. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 - shival[11:8] 76543210 shival[7:0]
702 32099a?avr32?06/09 at32uc3l 28.7.28 parameter register name: parameter access type: read-only offset: 0xf8 reset value: - ? sp[n]: sensor pair implemented 0: the corresponding sensor pair is not implemented 1: the corresponding sensor pair is implemented. 31 30 29 28 27 26 25 24 - 23 22 21 20 19 18 17 16 sp[23:16] 15 14 13 12 11 10 9 8 sp[15:8] 76543210 sp[7:0]
703 32099a?avr32?06/09 at32uc3l 28.7.29 version register name: version access type: read-only offset: 0xfc reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
704 32099a?avr32?06/09 at32uc3l 28.8 module configuration the specific configuration the cat module is listed in the following tables.the module bus clocks listed here are connecte d to the system bus clocks. pleas e refer to the power manager chapter for details. 28.8.1 resistive drive by default, the cat pins are driven with normal i/o drive properties. some of the csa and csb pins can optionally drive with a 1k output resistance for improved emc. to enable resistive drive on a pin, the user must write a one to the corresponding bit in the csa resistor control register (csares) or csb resistor control register (csbres) register. table 28-4. module clock name module name clock name cat clk_cat table 28-5. register reset values register reset value version 0x00000200 parameter 0x0001ffff
705 32099a?avr32?06/09 at32uc3l 29. glue logic controller (gloc) rev.: 1.0.0.0 29.1 features ? glue logic for general purpose pcb design ? programmable lookup table ? up to four inputs supported per lookup table ? optional filtering of output 29.2 overview the glue logic controller (gloc) contains programmable logic which can be connected to the device pins. this allows the user to eliminate logic gates for simple glue logic functions on the pcb. the gloc consists of a number of lookup tabl e (lut) units. each lut can generate an output as a user programmable logic expression with fo ur inputs. inputs can be individually masked. the output can be combinatorially generated from the inputs, or filtered to remove spikes. 29.3 block diagram figure 29-1. gloc block diagram lut peripheral bus truth filter out[0] ... out[n] filten in[3:0] ? in[(4n+3):4n] aen
706 32099a?avr32?06/09 at32uc3l 29.4 i/o lines description each lut have 4 inputs and one output. the inputs and outputs for the luts are mapped sequentially to the inputs and outputs. this means that lut0 is connected to in0 to in3 and out0. lut1 is connected to in4 to in7 and out1. in general, lutn is connected to in[4n] to in[4n+3] and outn. 29.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 29.5.1 i/o lines the pins used for interfacing the gloc may be multiplexed with i/o controller lines. the pro- grammer must first program the i/o controller to assign the desired gloc pins to their peripheral function. if i/o lines of the gloc are no t used by the application, they can be used for other purposes by the i/o controller. it is only required to enable the gloc input and outputs actually in use. 29.5.2 clocks the clock for the gloc bus interface (clk_gloc) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to dis- able the gloc before disabling the clock, to avoid freezing the module in an undefined state. additionally, the gloc depends on a dedicated generic clock (gclk). the gclk can be set to a wide range of frequencies and clock sources, and must be enabled by the system control interface (scif) before the gloc filter can be used. 29.5.3 debug operation when an external debugger forces the cpu into debug mode, the gloc continues normal operation. 29.6 functional description 29.6.1 enabling the lookup table inputs since the inputs to each lookup table (lut) unit can be multiplexed with other peripherals, each input must be explicitly enabled by writing a one to the corresponding enable bit (aen) in the corresponding lookup table control register ( lutcr). if no inputs are enabled, the output outn will be the least signif icant bit in the truthn register. table 29-1. i/o lines description pin name pin description type in0-inm inputs to lookup tables input out0-outn output from lookup tables output
707 32099a?avr32?06/09 at32uc3l 29.6.2 configuring the lookup table the lookup table in each lut unit can generate any logic expression out as a function of up to four inputs, in[3:0]. the truth table for the expression is written to the truth register for the lut. table 29-2 shows the truth table for lut0. the truth table for lutn is written to truthn, and the corresponing input and outputs will be in[4n] to in[4n+3] and outn. 29.6.3 output filter by default, the output outn is a combinatorial func tion of the inputs in[4n] to in[4n+3]. this may cause some short glitches to occur when the inputs change value. it is also possible to clock the output through a fi lter to remove glitches. this requires that the corresponding generic clock (gclk) has been enabled before use. the filter can then be enabled by writing a one to the filter enable (filten) bit in lutcrn. the outn output will be delayed by three to four gclk cycles when the filter is enabled. table 29-2. truth table for the lookup table in lut0 in[3] in[2] in[1] in[0] out[0] 0 0 0 0 truth0[0] 0 0 0 1 truth0[1] 0 0 1 0 truth0[2] 0 0 1 1 truth0[3] 0 1 0 0 truth0[4] 0 1 0 1 truth0[5] 0 1 1 0 truth0[6] 0 1 1 1 truth0[7] 1 0 0 0 truth0[8] 1 0 0 1 truth0[9] 1 0 1 0 truth0[10] 1 0 1 1 truth0[11] 1 1 0 0 truth0[12] 1 1 0 1 truth0[13] 1 1 1 0 truth0[14] 1 1 1 1 truth0[15]
708 32099a?avr32?06/09 at32uc3l 29.7 user interface note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. table 29-3. gloc register memory map offset register register name access reset 0x00+n*0x08 lookup table control register n lutcrn read/write 0x00000000 0x04+n*0x08 truth table register n truthn read/write 0x00000000 0x38 parameter register parameter read-only - (1) 0x3c version register version read-only - (1)
709 32099a?avr32?06/09 at32uc3l 29.7.1 lookup table control register n name: lutcrn access type: read/write offset : 0x00+n*0x08 reset value: 0x00000000 ? filten: filter enable 1: the output is glitch filtered 0: the output is not glitch filtered ? aen: enable in inputs input in[n] is enabled when aen[n] is one. input in[n] is disabled when aen[n] is zero, and will not affect the out value. 31 30 29 28 27 26 25 24 filten------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ---- aen
710 32099a?avr32?06/09 at32uc3l 29.7.2 truth table register n name: truthn access type: read/write offset : 0x04+n*0x08 reset value: 0x00000000 ? truth: truth table value this value defines the output ou t as a function of inputs in: out = truth[in] 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 truth[15:8] 76543210 truth[7:0]
711 32099a?avr32?06/09 at32uc3l 29.7.3 parameter register name: parameter access type: read-only offset :0x38 reset value: - ? luts: lookup table units implemented this field contains the number of lookup table units implemented in this device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 luts
712 32099a?avr32?06/09 at32uc3l 29.7.4 version register name: version access type: read-only offset :0x3c reset value: - ? variant: variant number reserved. no functionality associated. ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- variant 15 14 13 12 11 10 9 8 ---- version[11:8] 76543210 version[7:0]
713 32099a?avr32?06/09 at32uc3l 29.8 module configuration the specific configuration for each gloc instance is listed in the following tables.the gloc bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 29-4. gloc configuration feature gloc number of lut units 2 table 29-5. gloc clock name gloc name clock name gloc clk_gloc table 29-6. register reset values register reset value version 0x00000100 parameter 0x00000002
714 32099a?avr32?06/09 at32uc3l 30. awire uart (aw) rev.: 2.1.0.0 30.1 features ? asynchronous receiver or transmitter when the awire system is not used for debugging. ? one- or two-pin operation supported. 30.2 overview if the aw is not used for debugging, the awire ua rt can be used by the user to send or receive data with one stop bit, eight data bits, no parity bits, and one stop bit. this can be controlled through the awire uart user interface. this chapter only describes the awire uart user interface. for a description of the awire debug interface, please see the programming and debugging chapter.
715 32099a?avr32?06/09 at32uc3l 30.3 block diagram figure 30-1. awire debug interface block diagram 30.4 i/o lines description 30.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. table 30-1. i/o lines description name description type data awire data multiplexed wit h the reset_n pin. input/output uart reset filter external reset aw_enable reset_n baudrate detector rw sz addr data crc aw control aw user interface sab interface reset command power manager cpu halt command flash controller chip_erase command awire debug interface pb sab
716 32099a?avr32?06/09 at32uc3l 30.5.1 i/o lines the pin used by aw is multiple xed with the reset_n pi n. the reset function ality is the default function of this pin. to enable the awire func tionality on the reset_n pin the user must enable the awire uart user interface. 30.5.2 power management if the cpu enters a sleep mode that disables clocks used by the awire uart user interface, the awire uart user interface will stop functioning and resume operation af ter the system wakes up from sleep mode. 30.5.3 clocks the awire uart uses the internal 120 mhz rc oscillator (rc120m) as clock source for its operation. when using the awire uart user interface rc120m must enabled using the clock request register (see section 30.6.1 ). the clock for the awire uart user interface (clk_aw) is generated by the power manager. this clock is enabled at reset, and can be disabled in the power manager. it is recommended to disable the awire uart user interface before di sabling the clock, to avoid freezing the awire uart user interface in an undefined state. 30.5.4 interrupts the awire uart user interface interrupt request line is connected to the interrupt controller. using the awire uart user interface interrupt requires the interrupt controller to be pro- grammed first. 30.5.5 debug operation if the aw is used for debug ging the awire uart user interface will not be usable. when an external debugger forces the cpu into debug mode, the awire uart user interface continues normal operation. if the awire uart user interface is configured in a way that requires it to be periodically serviced by the cpu through interrupts or similar, improper opera- tion or data loss may result during debugging. 30.5.6 external components the aw needs an external pullup on the reset_n pin to ensure that the pin is pulled up when the bus is not driven. 30.6 functional description the awire uart user interface can be used as a spare asynchronous receiver or transmitter when aw is not used for debugging. 30.6.1 how to initialize the module to initialize the awire uart user interface the user must first enable the clock by writing a one to the clock enable bit in the clock request r egister (clkr.clken) and wait for the clock enable bit in the status register (sr.cenabl ed) to be set. after doing this either receive, transmit or receive with resync must be selected by writing th e corresponding value into the mode field of the control (ctrl.mode) register. due to the rc120m being asynchronous the with the system clock values must be allowed to propagate in the system. during this time the awire master will set the busy bit in the status register (sr.busy).
717 32099a?avr32?06/09 at32uc3l after the sr.busy bit is cleared the baud rate field in the baud rate register (brr.br) can be written with the wanted baudrate ( ) according to the following formula ( is the rc120m clock frequency): after this operation the user must wait until the sr.busy is clea red. the interface is now ready to be used. 30.6.2 basic asynchronous receiver operation the awire uart user interface must be initialized according to the sequence above, but the ctrl.mode field must be written to one (receive mode). when a data byte arrives the awire uart user interface will indicate this by setting the data ready interrupt bit in the status register (sr.dreadyint). the user must read the data in the receive holding register (rhr.rxdata) and clear the interrupt bit by writing a one to the data ready interrupt clear bit in the status clear register (scr.dreadyint). the interface is now ready to receive another byte. 30.6.3 basic asynchronous transmitter operation the awire uart user interface must be initialized according to the sequence above, but the ctrl.mode field must be written to two (transmit mode). to transmit a data byte the user must write the data to the transmit holding register (the.txdata). before the next byte can be written the sr.busy must be cleared. 30.6.4 basic asynchronous receiver with resynchronization by writing three into ctrl.mode the awire uart user interface will assume that the first byte it receives is a sync byte (0x55) and set brr. br according to this. all subsequent transfers will assume this baudrate, unless brr.br is rewritten by the user. to make the awire uart user interface accept a new sync resynchronization the awire uart user interface must be disabled by writing zero to ctrl.mode and then reenable the interface. 30.6.5 overrun in receive mode an overrun can occur if the user has not read the previous received data from the rhr.rxdata when the newest data should be pl aced there. such a condition is flagged by setting the overrun bit in the status register (sr.overrun). if sr.overrun is set the new- est data received is placed in rhr.rxdata and the data that was there before is overwritten. 30.6.6 interrupts to make the cpu able to do other things while wa iting for the awire uart user interface to fin- ish its operations the awire uart user interface supports generating interrupts. all status bits in the status register can be used as interrupt sources, except the sr.busy and sr.cenabled bits. to enable an interrupt the user must write a one to the corresponding bit in the interrupt enable register (ier). upon the next zero to one transition of this sr bit the awire uart user interface will flag this interrupt to the cpu. to clear the interrupt the user must write a one to the corre- sponding bit in the status clear register (scr). f br f aw f br 8 f aw br ----------- =
718 32099a?avr32?06/09 at32uc3l interrupts can be disabled by writing a one to th e corresponding bit in the interrupt disable reg- ister (idr). the interrupt mask register (imr) can be read to check if an interrupt is enabled or disabled. 30.6.7 using the peripheral dma controller to relieve the cpu of data transfers the awire uart user interface support using the peripheral dma controller. to transmit using the peripheral dma controller do the following: 1. setup the awire uart user interface in transmit mode. 2. setup the peripheral dma controller with buffer address and length, use byte as trans- fer size. 3. enable the peripheral dma controller. 4. wait until the peripheral dma controller is done. to receive using the peripheral dma controller do the following: 1. setup the awire uart user interface in receive mode 2. setup the peripheral dma controller with buffer address and length, use byte as trans- fer size. 3. enable the peripheral dma controller. 4. wait until the peripheral dma controller is ready.
719 32099a?avr32?06/09 at32uc3l 30.7 user interface note: 1. the reset values are device specific. please refer to the module configuration section at the end of this chapter. table 30-2. awire uart user interface register memory map offset register register name access reset 0x00 control register ctrl read/write 0x00000000 0x04 status register sr read-only 0x00000000 0x08 status clear register scr write-only - 0x0c interrupt enable register ier write-only - 0x10 interrupt disable register idr write-only - 0x14 interrupt mask register imr read-only 0x00000000 0x18 receive holding register rhr read-only 0x00000000 0x1c transmit holding register thr read/write 0x00000000 0x20 baud rate register brr read/write 0x00000000 0x24 version register version read-only - (1) 0x28 clock request register clkr read/write 0x00000000
720 32099a?avr32?06/09 at32uc3l 30.7.1 control register name: ctrl access type: read/write offset: 0x00 reset value: 0x00000000 ? mode: awire uart user interface mode 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------ mode table 30-3. awire uart user interface modes mode mode description 0 disabled 1receive 2 transmit 3 receive with resync.
721 32099a?avr32?06/09 at32uc3l 30.7.2 status register name: sr access type: read-only offset: 0x04 reset value: 0x00000000 ? trmis: transmit mismatch 0: no transfers mismatches. 1: the transceiver was active when receiving. this bit is set when the transce iver is active when receiving. this bit is cleared when corresponding bit in scr is written to one. ? overrun: data overrun 0: no data overwritten in rhr. 1: data in rhr has been overwritten before it has been read. this bit is set when data in rhr is overwritten before it has been read. this bit is cleared when corresponding bit in scr is written to one. ? dreadyint: data ready interrupt 0: no new data in the rhr. 1: new data received and placed in the rhr. this bit is set when new data is received and placed in the rhr. this bit is cleared when corresponding bit in scr is written to one. ? readyint: ready interrupt 0: the interface has not generated an ready interrupt. 1: the interface has had a transition from busy to not busy. this bit is set when the interface has transition from busy to not busy. this bit is cleared when corresponding bit in scr is written to one. ? cenabled: clock enabled 0: the awire clock is not enabled. 1: the awire clock is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - trmis - - overrun dreadyint readyint 76543210 - - - - - cenabled - busy
722 32099a?avr32?06/09 at32uc3l this bit is set when the clock is disabled. this bit is cleared when the clock is enabled. ? busy: synchronizer busy 0: the asynchronous interface is ready to accept more data. 1: the asynchronous interface is busy and will block writes to ctrl, brr, and thr. this bit is set when the asynchronous interface becomes busy. this bit is cleared when the asynchronous interface becomes ready.
723 32099a?avr32?06/09 at32uc3l 30.7.3 status clear register name: scr access type: write-only offset: 0x08 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in sr and the corresponding interrupt request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - trmis - - overrun dreadyint readyint 76543210 --------
724 32099a?avr32?06/09 at32uc3l 30.7.4 interrupt enable register name: ier access type: write-only offset: 0x0c reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will set the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - trmis - - overrun dreadyint readyint 76543210 --------
725 32099a?avr32?06/09 at32uc3l 30.7.5 interrupt disable register name: idr access type: write-only offset: 0x10 reset value: 0x00000000 writing a zero to a bit in this register has no effect. writing a one to a bit in this register will clear the corresponding bit in imr. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - trmis - - overrun dreadyint readyint 76543210 --------
726 32099a?avr32?06/09 at32uc3l 30.7.6 interrupt mask register name: imr access type: read-only offset: 0x14 reset value: 0x00000000 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. a bit in this register is cleared when the corresponding bit in idr is written to one. a bit in this register is set when the corresponding bit in ier is written to one. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - trmis - - overrun dreadyint readyint 76543210 --------
727 32099a?avr32?06/09 at32uc3l 30.7.7 receive holding register name: rhr access type: read-only offset: 0x18 reset value: 0x00000000 ? rxdata: received data the last byte received. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rxdata
728 32099a?avr32?06/09 at32uc3l 30.7.8 transmit holding register name: thr access type: read/write offset: 0x1c reset value: 0x00000000 ? txdata: transmit data the data to send. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 txdata
729 32099a?avr32?06/09 at32uc3l 30.7.9 baud rate register name: brr access type: read/write offset: 0x20 reset value: 0x00000000 ? br: baud rate the baud rate ( ) of the transmission, calculated us ing the following formula ( is the rc120m frequency): br should not be set to a value smaller than 32. writing a value to this field will update the baud rate of the transmission. reading this field will give the current baud rate of the transmission. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 br[15:8] 76543210 br[7:0] f br f aw f br 8 f aw br ----------- =
730 32099a?avr32?06/09 at32uc3l 30.7.10 version register name: version access type: read-only offset: 0x24 reset value: 0x00000200 ? version: version number version number of the module. no functionality associated. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - version[11:8] 76543210 version[7:0]
731 32099a?avr32?06/09 at32uc3l 30.7.11 clock request register name: clkr access type: read/write offset: 0x28 reset value: 0x00000000 ? clken: clock enable 0: the awire clock is disabled. 1: the awire clock is enabled. writing a zero to this bit will disable the awire clock. writing a one to this bit will enable the awire clock. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------clken
732 32099a?avr32?06/09 at32uc3l 30.8 module configuration the specific configuration for each awire instan ce is listed in the following tables.the module bus clocks listed here are connected to the syst em bus clocks. please refer to the power man- ager chapter for details. table 30-4. module clock name module name clock name awire clk_aw table 30-5. register reset values register reset value version 0x00000210
733 32099a?avr32?06/09 at32uc3l 31. programming and debugging 31.1 overview the at32uc3l supports programming and debugging through two interfaces, jtag or awire ? . jtag is an industry standard interface and allows boundary scan for pcb testing, as well as daisy-chaining of multiple devices on the pcb. awire is an atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved. either interface provides access to the internal service access bus (sab), which offers a bridge to the high speed bus, giving access to memories and peripherals in the device. by using this bridge to the bus system, the flas h and fuses can thus be programmed by access- ing the flash controller in the same manner as the cpu. the sab also provides access to the nexus-compliant on-chip debug (ocd) system in the device, which gives the user non-intrusive run-time control of the program execution. addition- ally, trace information can be output on the auxiliary (aux) deb ug port or buff ered in internal ram for later retrieval by jtag or awire. 31.2 service access bus the avr32 architecture offers a common interface for access to on-chip debug, programming, and test functions. these are mapped on a common bus called t he service acce ss bus (sab), which is linked to the jtag and awire port th rough a bus master module, which also handles synchronization between th e debugger and sab clocks. when accessing the sab through th e debugger ther e are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the sab accesses to complete. if the system clock is swit ched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. this ratio can be measured with debug protocol specific instructions. the service access bus uses 36 address bits to address memory or registers in any of the slaves on the bus. the bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). all accesses must be aligned to the size of th e access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. 31.2.1 sab address map the service access bus (sab) gives the user access to the internal address space and other features through a 36 bits address space. the 4 msbs identify the slave number, while the 32 lsbs are decoded within the slave?s addres s space. the sab slaves are shown in table 31-1 . table 31-1. sab slaves, addresses and descriptions slave address [35:32] description unallocated 0x0 intentionally unallocated ocd 0x1 ocd registers hsb 0x4 hsb memory space, as seen by the cpu
734 32099a?avr32?06/09 at32uc3l 31.2.2 sab security restrictions the service access bus can be restricted by internal security measures. a short description of the security measures are found in the table below. 31.2.2.1 security measure and control location a security measure is a mechanism to either block or a llow sab access to a certain address or address range. a security measure is enabled or disabled by one or several control signals. this is called the control location for the security measure. these security measures can be used to prevent an end user from reading out the code pro- grammed in the flash, for instance. below follows a more in depth description of what locations are accessible when the security measures are active. hsb 0x5 alternative mapping for hsb space, for compatibility with other avr32 devices. memory service unit 0x6 memory service unit registers reserved other unused table 31-1. sab slaves, addresses and descriptions slave address [35:32] description table 31-2. sab security measures security measure control location description secure mode flashcdw secure bits set allocates a portion of the flash for secure code. this code cannot be read or debugged. security bit flashcdw security bit set programming and debugging not possible, very restricted access. user code programming flashcdw uprot + security bit set restricts all access except parts of the flash and the flash controller for programming user code. debugging is not possible unless an os running from the secure part of the flash supports it. table 31-3. secure mode sab restrictions name address start address end access secure flash area 0x580000000 0x580000000 + (userrow[15:0] << 10) blocked secure ram area 0x500000000 0x500000000 + (userrow[31:16] << 10) blocked other accesses - - as normal
735 32099a?avr32?06/09 at32uc3l table 31-4. security bit sab restrictions name address start address end access ocd dccpu, ocd dcemu, ocd dcsr 0x100000110 0x100000118 read/write user page 0x580800000 0x581000000 read other accesses - - blocked table 31-5. user code programming sab restrictions name address start address end access ocd dccpu, ocd dcemu, ocd dcsr 0x100000110 0x100000118 read/write user page 0x580800000 0x581000000 read flashcdw pb interface 0x5fffe0000 0x5fffe0400 read/write flash pages outside bootprot 0x580000000 + bootprot size 0x580000000 + flash size read/write other accesses - - blocked
736 32099a?avr32?06/09 at32uc3l 31.3 on-chip debug rev: 2.1.0.0 31.3.1 features ? debug interface in compli ance with ieee-isto 5001- 2003 (nexus 2.0) class 2+ ? jtag or awire access to all on-chip debug functions ? advanced program, data, ownership, and watchpoint trace supported ? nanotrace awire- or jtag-based trace access ? auxiliary port for high-speed trace information ? hardware support for 6 prog ram and 2 data breakpoints ? unlimited number of softw are breakpoints supported ? automatic crc check of memory regions 31.3.2 overview debugging on the at32uc3l is facilitated by a powerful on-c hip debug (ocd) system. the user accesses this through an external debug tool which connects to the jtag or awire port and the auxiliary (aux) po rt. the aux port is prim arily used for trace functions, and an awire- or jtag-based debugger is sufficient for basic debugging. the debug system is based on the nexus 2.0 standard, class 2+, which includes: ? basic run-time control ? program breakpoints ? data breakpoints ?program trace ? ownership trace ? data trace in addition to the mandatory nexus debug features, the at32uc3l implements several useful ocd features, such as: ? debug communication channel between cpu and debugger ? run-time pc monitoring ? crc checking ? nanotrace ? software quality assurance (sqa) support the ocd features are controlled by ocd registers, which can be accessed by the debugger, for instance when the nexus_access jtag inst ruction is loaded. the cpu can also access ocd registers directly using mtdr/mfdr instructions in any privileged mode. the ocd registers are implemented based on the recommendations in the nexus 2.0 standard, and are detailed in the avr32uc technical reference manual. 31.3.3 i/o lines description the ocd aux trace port contains a number of pins, as shown in table 31-6 on page 737 . these are multiplexed with i/o co ntroller lines, and must explicit ly be enabled by writing ocd registers before the debug session starts. the aux port is mapped to two different locations,
737 32099a?avr32?06/09 at32uc3l selectable by ocd registers, minimizing the chance that the aux port will need to be shared with an application. 31.3.4 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. 31.3.4.1 power management the ocd clock operates independently of the cpu clock. if enabled in the power manager, the ocd clock (clk_ocd) will continue running even if the cpu enters a sleep mode that disables the cpu clock. 31.3.4.2 clocks the ocd has a clock (clk_ocd) running synchronou sly with the cpu clock. this clock is gen- erated by the power manager. the clock is enabled at reset, and can be disabled by writing to the power manager. 31.3.4.3 interrupt the ocd system interrupt request lines are connected to the interrupt controller. using the ocd interrupts requires the interrupt controller to be programmed first. table 31-6. auxiliary port signals pin name pin description direction active level type mcko trace data output clock output digital mdo[5:0] trace data output output digital mseo[1:0] trace frame control output digital evti_n event in input low digital evto_n event out output low digital
738 32099a?avr32?06/09 at32uc3l 31.3.5 block diagram figure 31-1. on-chip debug block diagram 31.3.6 sab-based debug features a debugger can control all ocd fe atures by writing ocd register s over the sab interface. many of these do not depend on output on the aux port, allowing an awire- or jtag-based debugger to be used. a jtag-based debugger should connect to the device through a standard 10-pin idc connector as described in the avr32uc technical reference manual. an awire-based deb ugger should connect to the device through the reset_n pin. on-chip debug jtag debug pc debug instruction cpu breakpoints program trace data trace ownership trace watchpoints transmit queue aux jtag internal sram s e r v i c e a c c e s s b u s memory service unit hsb bus matrix memories and peripherals awire awire
739 32099a?avr32?06/09 at32uc3l figure 31-2. jtag-based debugger figure 31-3. awire-based debugger 31.3.6.1 debug communication channel the debug communication channel (d cc) consists of a pair ocd registers with associated handshake logic, accessible to both cpu and debugger. the registers can be used to exchange data between the cpu and the debugmaster, both runtime as well as in debug mode. avr32 jtag-based debug tool pc jtag 10-pin idc avr32 awire-based debug tool pc awire
740 32099a?avr32?06/09 at32uc3l the ocd system can generate an interrupt to the cpu when dccpu is read and when dcemu is written. this enables the user to build a cust um debug protocol using only these registers. the dccpu and dcemu registers are available even when the security bit in the flash is active. for more information refer to the avr32uc technical reference manual. 31.3.6.2 breakpoints one of the most fundamental debug features is the abilit y to halt the cpu, to examine registers and the state of the system. this is accomplish ed by breakpoints, of which many types are available: ? unconditional breakpoints are set by writing ocd registers by the debugger, halting the cpu immediately. ? program breakpoints halt the cpu when a specific address in the program is executed. ? data breakpoints halt the cpu when a specific memory address is read or written, allowing variables to be watched. ? software breakpoints halt the cpu when the breakpoint instruction is executed. when a breakpoint triggers, the cpu enters debug mode, and the d bit in the status register is set. this is a privileged mode with dedicated return address and return status registers. all privi- leged instructions are permitted. debug mode can be entered as either ocd mode, running instructions from the debugger, or monitor mode, running instructions from program memory. 31.3.6.3 ocd mode when a breakpoint triggers, the cpu enters ocd mode, and instructions are fetched from the debug instruction ocd register. each time this register is written by the debugger, the instruc- tion is executed, allowing the debugger to execut e cpu instructions directly. the debug master can e.g. read out the register file by issuing mtdr instructions to the cpu, writing each register to the debug communication channel ocd registers. 31.3.6.4 monitor mode since the ocd registers are directly accessible by the cpu, it is possible to build a software- based debugger that runs on the cpu itself. setting the monitor mode bit in the development control register causes the cpu to enter monitor mode instead of ocd mode when a breakpoint triggers. monitor mode is similar to ocd mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by the debug master. 31.3.6.5 program counter monitoring normally, the cpu would need to be halted for a debugger to examine the current pc value. however, the at32uc3l also proves a debug program counter ocd register, where the debugger can continuously read the current pc without affecting the cpu. this allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization. 31.3.7 memory service unit the memory service unit (msu) is a block dedicated to test and debug functionality. it is con- trolled through a dedicated set of registers addressed through the service access bus.
741 32099a?avr32?06/09 at32uc3l 31.3.7.1 cyclic redundancy check (crc) the msu can be used to automatically calculate the crc of a block of data in memory. the msu will then read out each word in the specif ied memory block and re port the crc32-value in an msu register. 31.3.7.2 nanotrace the msu additionally supports nanotrace. this is an avr32-specific feature, in which trace data is output to memory instead of the aux port . this allows the trace data to be extracted by the debugger through the sab, enabling trace features for awire- or jtag-based debuggers. the user must write msu registers to configure the address and size of the memory block to be used for nanotrace. the nanotrace buffer can be anywhere in the physical address range, including internal and external ram, through an ebi, if present. this area may not be used by the application running on the cpu. 31.3.8 aux-based debug features utilizing the auxiliary (aux) port gives a ccess to a wide range of advanced debug features. of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the cpu. additionally, event in and event out pins allow external events to be correlated with the program flow. debug tools utilizing the aux port should connec t to the device throug h a nexus-compliant mic- tor-38 connector, as described in the avr32uc technical reference manual. this connector includes the jtag signals and the reset_n pin, giving full access to the programming and debug features in the device.
742 32099a?avr32?06/09 at32uc3l figure 31-4. aux+jtag based debugger 31.3.8.1 trace operation trace features are enabled by writing ocd re gisters by the debugger. the ocd extracts the trace information from the cpu, compresses this information and formats it into variable-length messages according to the nexus standard. the messages are buffered in a 16-frame transmit queue, and are output on the aux port one frame at a time. the trace features can be configured to be very selective, to reduce the bandwidth on the aux port. in case the transmit queue overflows, er ror messages are produced to indicate loss of data. the transmit queue module can optionally be configured to halt the cpu when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 31.3.8.2 program trace program trace allows the debugger to continuously monitor the program execution in the cpu. program trace messages are generated for every branch in the program, and contains com- pressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address. 31.3.8.3 data trace data trace outputs a message every time a specific location is read or written. the message contains information about the type (read/write) and size of the access, as well as the address and data of the accessed location. the at32uc3l contains two data trace channels, each of avr32 aux+jtag debug tool jtag aux high speed mictor38 trace buffer pc
743 32099a?avr32?06/09 at32uc3l which are controlled by a pair of ocd registers which determine the range of addresses (or sin- gle address) which should produce data trace messages. 31.3.8.4 ownership trace program and data trace operate on virtual addresses. in cases where an operating system runs several processes in overlapping virtual memory segments, the ownership trace feature can be used to identify th e process switch. when the o/s activates a process, it will write the process id number to an ocd register, which produces an ownership trace message, allowing the debug- ger to switch context for the subsequent progra m and data trace messages. as the use of this feature depends on the software running on the cpu, it can also be used to extract other types of information from the system. 31.3.8.5 watchpoint messages the breakpoint modules normally used to generate program and data breakpoints can also be used to generate watchpoint messages, allowing a debugger to monitor program and data events without halting the cpu. watchpoints can be enabled independently of breakpoints, so a breakpoint module can optionally halt the cpu w hen the trigger condition occurs. data trace modules can also be configured to produce watc hpoint messages instead of regular data trace messages. 31.3.8.6 event in and event out pins the aux port also contains an event in pin (evti_n) and an event out pin (evto_n). evti_n can be used to trigger a breakpoint when an external event occurs. it can also be used to trigger specific program and data trace synchronization messages, allowing an external event to be correlated to the program flow. when the cpu enters debug mode, a debug status message is transmitted on the trace port. all trace messages can be timestamped when they are received by the debug tool. however, due to the latency of the trans mit queue buffering, the timest amp will not be 100% accurate. to improve this, evto_n can toggle every time a message is inserted into the transmit queue, allowing trace messages to be timestamped prec isely. evto_n can also toggle when a break- point module triggers, or when the cpu enters debug mode, for any reason. this can be used to measure precisely when the respective internal event occurs. 31.3.8.7 software quality analysis (sqa) software quality analysis (sqa) deals with two important issues regarding embedded software development. code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized. program trace must be used to accomplish these tasks without instrumenting (altering) the code to be examined. however, traditional program trace cannot reconstruct the current pc value without correlating the trace information with the source code, which cannot be done on-the-fly. this limits program trace to a relatively short time segment, determined by the size of the trace buffer in the debug tool. the ocd system in at32uc3l extends program trace with sqa capabilities, allowing the debug tool to reconstruct the pc value on-the-f ly. code coverage and performance analysis can thus be reported for an unlimited execution sequence.
744 32099a?avr32?06/09 at32uc3l 31.4 jtag and boundary-scan (jtag) rev: 2.2.1.3 31.4.1 features ? ieee1149.1 compli ant jtag interface ? boundary-scan chain for board-level testing ? direct memory access and programming capabilities through jtag interface 31.4.2 overview the jtag interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. figure 31-5 on page 745 shows how the jtag is connected in an avr32 device. the tap con- troller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi-input and tdo-output. the instruction register holds jt ag instructions controlling the be havior of a data register. the device identification register, bypass register , and the boundary-scan chain are the data reg- isters used for board-level testing. the reset register can be used to keep the device reset during test or programming. the service access bus (sab) interface cont ains address and data registers for the service access bus, which gives access to on-chip debug, programming, and other functions in the device. the sab offers se veral modes of access to the addr ess and data regist ers, as described in section 31.4.11 . section 31.5 lists the supported jtag instructions, wit h references to the description in this document.
745 32099a?avr32?06/09 at32uc3l 31.4.3 block diagram figure 31-5. jtag and boundary-scan access 31.4.4 i/o lines description 31.4.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. table 31-7. i/o line description pin name pin description type active level reset_n external reset pin. used when enabling and disabling the jtag. input low tck test clock input. fully asynchronous to system clock frequency. input tms test mode select, sampled on rising tck. input tdi test data in, sampled on rising tck. input tdo test data out, driven on falling tck. output avr32 device jtag data registers tap controller instruction register device identification register by-pass register reset register service access bus interface boundary scan chain pins and analog blocks data register scan enable jtag pins boundary scan enable 2nd jtag device jtag master tdi tdo part specific registers ... tdo tdi tms tms tck tck instruction register scan enable sab internal i/o lines jtag tms tdi tdo tck
746 32099a?avr32?06/09 at32uc3l 31.4.5.1 i/o lines the tms, tdi, tdo, and tck pins are multiplexed with i/o lines. when the jtag is used the associated pins must be enabled. to enable the jtag pins, refer to section 31.4.7 . while using the multiplexed jtag lines all norma l peripheral activity on these lines is disabled. the user must make sure that no external peripheral is blocking the jtag lines while debugging. 31.4.5.2 power management when an instruction that accesses the sab is loaded in the instruction register, before entering a sleep mode, the system clocks are not switched off to a llow debugging in sleep modes. this can lead to a program behaving differently when debugging. 31.4.5.3 clocks the jtag interface uses the external tck pin as clock source. this clock must be provided by the jtag master. instructions that use the sab bus requires the internal main clock to be running. 31.4.6 jtag interface the jtag interface is accessed through the dedicated jtag pins shown in table 31-7 on page 745 . the tms control line navigates the tap controller, as shown in figure 31-6 on page 747 . the tap controller manages the serial access to the jtag instruction and data registers. data is scanned into the selected instruction or data register on tdi, and out of the register on tdo, in the shift-ir and shift-dr states, respectively. th e lsb is shifted in and out first. tdo is high- z in other states than shift-ir and shift-dr. the device implements a 5-bit instruction regist er (ir). a number of public jtag instructions defined by the jtag standard are supported, as described in section 31.5.2 , as well as a num- ber of avr32-specific private jtag instructions described in section 31.5.3 . each instruction selects a specific data register for the shift-dr path, as described for each instruction.
747 32099a?avr32?06/09 at32uc3l figure 31-6. tap controller state diagram test-logic- reset run-test/ idle select-dr scan select-ir scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 0 1
748 32099a?avr32?06/09 at32uc3l 31.4.7 how to initialize the module to enable the jtag pins the tck pin must be held low while the reset_n pin is released. after enabling the jtag interface the halt bit is set automatically to prevent the system from run- ning code after the interface is enabled. to make the cpu run again set halt to zero using the halt command.. jtag operation when reset_n is pulled low is not possible. independent of the initial state of the tap controller, the test-logic-reset state can always be entered by holding tms high for 5 tck clock periods. this sequence should always be applied at the start of a jtag session and after enabling the jtag pins to bring the tap controller into a defined state before applying jtag commands. applying a 0 on tms for 1 tck period brings the tap controller to the run-test/idle state, which is the starting point for jtag operations. 31.4.8 how to disable the module to disable the jtag pins the tck pin must be held high while reset _n pin is released. 31.4.9 typical sequence assuming run-test/idle is the present state, a typical scenario for using the jtag interface follows. 31.4.9.1 scanning in jtag instruction at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register (shift-ir) state. while in this state, shift the 5 bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. during shifting, the jtag outputs status bits on tdo, refer to section 31.5 for a description of these. the tms input must be held low during input of the 4 lsbs in order to remain in the shift-ir state. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding th e selected data register. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. figure 31-7. scanning in jtag instruction 31.4.9.2 scanning in/out data at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register (shift-dr) state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge tck tap state tlr rti seldr selir capir shir ex1ir updir rti tms tdi instruction tdo impldefined
749 32099a?avr32?06/09 at32uc3l of tck. in order to remain in the shift-dr state, the tms input must be held low. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data registers. 31.4.10 boundary-scan the boundary-scan chain has the c apability of driving an d observing the logic levels on the digi- tal i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities ar e connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the 4 tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode, bypass, sample/pre- load, and extest can be used for testing the printed circuit board. initial scanning of the data register path will show th e id-code of the device, sinc e idcode is the default jtag instruction. it may be desirable to have the avr32 device in reset during test mode. if not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the device. the device can be set in the reset state either by pu lling the external resetn pin low, or issuing the avr_reset instruction with appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. when using the jtag interface for boundary-scan, the jtag tck clock is independent of the internal chip clock. the internal chip clock is not required to run during boundary-scan operations. note: for pins connected to 5v lines care should be taken to not drive the pins to a logic one using boundary-scan, as this will create a current fl owing from the 3,3v driver to the 5v pull-up on the line. optionally a series resistor can be added between the line and the pin to reduce the current. details about the boundary-scan chain can be found in the bsdl file for the device. this can be found on the atmel website. 31.4.11 service access bus the avr32 architecture offers a common interface for access to on-chip debug, programming, and test functions. these are mapped on a common bus called t he service acce ss bus (sab),
750 32099a?avr32?06/09 at32uc3l which is linked to the jtag through a bus master module, which also handles synchronization between the tck and sab clocks. for more information about the sab and a list of sab slaves see the service access bus chapter. 31.4.11.1 sab address mode the memory_sized_access instruction allows a sized read or write to any 36-bit address on the bus. memory_word_access is a shorthand instruction for 32-bit accesses to any 36-bit address, while the nexus_access instruct ion is a nexus-compliant shorthand instruc- tion for accessing the 32-bit ocd registers in the 7-bit address space reserved for these. these instructions require two passes through the shift-dr tap state: one for the address and control information, and one for data. 31.4.11.2 block transfer to increase the transfer rate, consecutive me mory accesses can be accomplished by the memory_block_access instruction, which only r equires a single pass through shift-dr for data transfer only. the address is automatically incremented according to the size of the last sab transfer. 31.4.11.3 canceling a sab access it is possible to abort an ongoing sab access by the cancel_access instruction, to avoid hanging the bus due to an extremely slow slave. 31.4.11.4 busy reporting as the time taken to perform an access may vary depending on system activity and current chip frequency, all the sab access jtag instructions can return a busy indicator. this indicates whether a delay needs to be inserted, or an operation needs to be repeated in order to be suc- cessful. if a new acce ss is requested while the sab is busy, the request is ignored. the sab becomes busy when: ? entering update-dr in the address phase of any read operation, e.g., after scanning in a nexus_access address wit h the read bit set. ? entering update-dr in the data phase of any write operation, e.g., after scanning in data for a nexus_access write. ? entering update-dr during a memory_block_access. ? entering update-dr after scanning in a counter value for sync. ? entering update-ir af ter scanning in a memory_block _access if the previous access was a read and data was scanned after scanning the address. the sab becomes ready again when: ? a read or write operation completes. ? a sync countdown completed. ? a operation is cancelled by the cancel_access instruction. what to do if the busy bit is set: ? during shift-ir: the new instruction is selected, but the previous operation has not yet completed and will continue (u nless the new instruction is cancel_access). you may
751 32099a?avr32?06/09 at32uc3l continue shifting the same instruction until the busy bit clears, or start shifting data. if shifting data, you must be prepared that the data shift may also report busy. ? during shift-dr of an address: the new address is ignored. the sab stays in address mode, so no data must be shifted. repeat the address until the busy bit clears. ? during shift-dr of read data: the read data is invalid. the sab stays in data mode. repeat scanning until the busy bit clears. ? during shift-dr of write data: the write data is ignored. the sab stays in data mode. repeat scanning until the busy bit clears. 31.4.11.5 error reporting the service access bus may not be able to comp lete all accesses as requested. this may be because the address is invalid, the addressed area is read-only or cannot handle byte/halfword accesses, or because the chip is set in a protected mode where only limited accesses are allowed. the error bit is updated when an access complete s, and is cleared when a new access starts. what to do if the error bit is set: ? during shift-ir: the new instruction is selected. the last operation performed using the old instruction did not complete successfully. ? during shift-dr of an address: the previous operation failed. the new address is accepted. if the read bit is set, a read operation is started. ? during shift-dr of read data: the read operation failed, and the read data is invalid. ? during shift-dr of write data: the previous write operation failed. the new data is accepted and a write operation started. this should only occur during block writes or stream writes. no error can occur between scanning a write address and the following write data. ? while polling with cancel_access: the previous access was cancelled. it may or may not have actually completed. ? after power-up: the error bit is set after power up, but there has been no previous sab instruction so this error can be discarded. 31.4.11.6 protected reporting a protected status may be reported during shift-ir or shift-dr. this indicates that the security bit in the flash controller is set and that the chip is locked for access, according to section 31.5.1 . the protected state is reported when: ? the flash controller is under reset. this can be due to the avr_reset command or the reset_n line. ? the flash controller has not read the security bit from the flash yet (this will take a a few ms). happens after the flash controller reset has been released. ? the security bit in the flash controller is set. what to do if the protected bit is set: ? release all active avr_ reset domains, if any. ? release the reset_n line. ? wait a few ms for the security bit to clear. it can be set temporarily due to a reset.
752 32099a?avr32?06/09 at32uc3l ? perform a chip_erase to clear the security bit. note : this will erase all the contents of the non-volatile memory. 31.5 jtag instruction summary the implemented jtag instructions in the avr32 are shown in the table below. 31.5.1 security restrictions when the security fuse in the flash is programmed, the following jtag instructions are restricted: ? nexus_access ? memory_word_access ? memory_block_access ? memory_sized_access for description of what memory locations remain accessible, please refer to the sab address map. table 31-8. jtag instruction summary instruction opcode instruction description page 0x01 idcode select the 32-bit device ident ification register as data register. 754 0x02 sample_preload take a snapshot of external pi n values without affecting system operation. 755 0x03 extest select boundary-scan chain as data register for testing circuitry external to the device. 755 0x04 intest select boundary-scan chain for internal testing of the device. 756 0x06 clamp bypass device through bypass register, while driving outputs from boundary-scan register. 756 0x0c avr_reset apply or remove a static reset to the device 764 0x0f chip_erase erase the device 765 0x10 nexus_access select the sab address and data registers as data register for the tap. the registers are accessed in nexus mode. 758 0x11 memory_word_access select the sab address and data registers as data register for the ta p. 761 0x12 memory_block_access select the sab data register as data register for the tap. the address is auto-incremented. 762 0x13 cancel_access cancel an ongoing nexus or memory access. 763 0x14 memory_service select the sab address and data registers as data register for the tap. the registers are accessed in memory service mode. 758 0x15 memory_sized_access select the sab address and data registers as data register for the ta p. 759 0x17 sync synchronization counter 763 0x1c halt halt the cpu for safe programming. 765 0x1f bypass bypass this device through the bypass register. 757 others n/a acts as bypass
753 32099a?avr32?06/09 at32uc3l full access to these instructions is re-enabled when the security fuse is erased by the chip_erase jtag instruction. note that the security bit will read as programmed and block these instructions also if the flash controller is statically reset. other security mechanisms can also restrict these functions. if such mechanisms are present they are listed in the sab address map section. 31.5.1.1 notation table 31-10 on page 754 shows bit patterns to be shifted in a format like " peb01 ". each charac- ter corresponds to one bit, and eight bits are grouped together for readability. the least significantbit is always shifted first, and the mo st significant bit shifted last. the symbols used are shown in table 31-9 . in many cases, it is not required to shift all bits through the data register. bit patterns are shown using the full width of the shift register, but the suggested or required bits are emphasized using bold text. i.e. given the pattern " aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is 34 bits, but the test or debug unit may choose to shift only 8 bits " aaaaaaar ". table 31-9. symbol description symbol description 0 constant low value - always reads as zero. 1 constant high value - always reads as one. a an address bit - always scanned with the least significant bit first b a busy bit. reads as one if the sab was busy, or zero if it was not. see section 31.4.11.4 for details on how the busy reporting works. d a data bit - always scanned with the least significant bit first. e an error bit. reads as one if an error occurred, or zero if not. see section 31.4.11.5 for details on how the error reporting works. p the chip protected bit. some devices may be se t in a protected state where access to chip internals are severely restricted. see the docum entation for the specific device for details. on devices without this possibility, this bit always reads as zero. r a direction bit. set to one to request a read, set to zero to request a write. s a size bit. the size encoding is described where used. x a don?t care bit. any value can be shifted in, and output data should be ignored.
754 32099a?avr32?06/09 at32uc3l the following describes how to interpret the fields in the instruction description tables: 31.5.2 public jtag instructions the jtag standard defines a number of public jtag instructions. these instructions are described in the sections below. 31.5.2.1 idcode this instruction selects the 32 bit device identification register (did) as data register. the did register consists of a version number, a device number, and the manufacturer code chosen by jedec. this is the default instruction after a jtag reset. details about the did register can be found in the module configuration section at the end of this chapter. starting in run-test/idle, the device identification register is accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in capture-dr: the idcode value is latched into the shift register. 7. in shift-dr: the idcode scan ch ain is shifted by the tck input. 8. return to run-test/idle. table 31-10. instruction description instruction description ir input value shows the bit pattern to shift into ir in t he shift-ir state in order to select this instruction. the pattern is show both in binary and in hexadecimal form for convenience. example: 10000 (0x10) ir output value shows the bit pattern shifted out of ir in t he shift-ir state when this instruction is active. example: peb01 dr size shows the number of bits in the data register chain when this instruction is active. example: 34 bits dr input value shows which bit pattern to shift into the data register in the shift-dr state when this instruction is active. multiple such line s may exist, e.g., to distinguish between reads and writes. example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx dr output value shows the bit pattern shifted out of the dat a register in the sh ift-dr state when this instruction is active. multiple such line s may exist, e.g., to distinguish between reads and writes. example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb table 31-11. idcode details instructions details ir input value 00001 (0x01) ir output value p0001
755 32099a?avr32?06/09 at32uc3l 31.5.2.2 sample_preload this instruction takes a snap-shot of the input/ output pins without affect ing the system operation, and pre-loading the scan chain without updating the dr-latch. the boundary-scan chain is selected as data register. starting in run-test/idle, the device identification register is accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in capture-dr: the data on the external pins are sampled into the boundary-scan chain. 7. in shift-dr: the boundary-scan chain is shifted by the tck input. 8. return to run-test/idle. 31.5.2.3 extest this instruction selects the boundary-scan chain as data register for testing circuitry external to the avr32 package. the contents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. starting in run-test/idle, the extest instruction is accessed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the output pins. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: the data on the external pins is sampled into the boundary-scan chain. 8. in shift-dr: the boundary-scan chain is shifted by the tck input. 9. in update-dr: the data from the scan chain is applied to the output pins. dr size 32 dr input value xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dr output value device identification register table 31-11. idcode details (continued) instructions details table 31-12. sample_preload details instructions details ir input value 00010 (0x02) ir output value p0001 dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file.
756 32099a?avr32?06/09 at32uc3l 10. return to run-test/idle. 31.5.2.4 intest this instruction selects the boundary-scan chain as data register for testing internal logic in the device. the logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. the device output pins are driven from the boundary-scan chain. starting in run-test/idle, the intest instruction is access ed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the internal logic inputs. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: the data on the internal logic is sampled into the boundary-scan chain. 8. in shift-dr: the boundary-scan chain is shifted by the tck input. 9. in update-dr: the data from the boundary-scan chain is applied to internal logic inputs. 10. return to run-test/idle. 31.5.2.5 clamp this instruction selects the bypass register as data register. the device output pins are driven from the boundary-scan chain. starting in run-test/idle, the clamp instruction is acce ssed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. table 31-13. extest details instructions details ir input value 00011 (0x03) ir output value p0001 dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file. table 31-14. intest details instructions details ir input value 00100 (0x04) ir output value p0001 dr size depending on boundary-scan chain, see bsdl-file. dr input value depending on boundary-scan chain, see bsdl-file. dr output value depending on boundary-scan chain, see bsdl-file.
757 32099a?avr32?06/09 at32uc3l 3. in shift-ir: the instruction register is shifted by the tck input. 4. in update-ir: the data from the boundary-scan chain is applied to the output pins. 5. return to run-test/idle. 6. select the dr scan path. 7. in capture-dr: a logic ?0? is loaded into the bypass register. 8. in shift-dr: data is scanned from tdi to tdo through the bypass register. 9. return to run-test/idle. 31.5.2.6 bypass this instruction selects the 1-bit bypass register as data register. starting in run-test/idle, the clamp instruction is acce ssed the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in capture-dr: a logic ?0? is loaded into the bypass register. 7. in shift-dr: data is scanned from tdi to tdo through the bypass register. 8. return to run-test/idle. 31.5.3 private jtag instructions the avr32 defines a number of private jtag instructions, not defined by the jtag standard. each instruction is briefly described in text, with details follo wing in table form. table 31-15. clamp details instructions details ir input value 00110 (0x06) ir output value p0001 dr size 1 dr input value x dr output value x table 31-16. bypass details instructions details ir input value 11111 (0x1f) ir output value p0001 dr size 1 dr input value x dr output value x
758 32099a?avr32?06/09 at32uc3l 31.5.3.1 nexus_access this instruction allows nexus-compliant access to the on-chip debug registers through the sab. the 7-bit register index, a read/write co ntrol bit, and the 32-bit data is accessed through the jtag port. the data register is alternately interpreted by the sab as an address register and a data regis- ter. the sab starts in addre ss mode after the nexus_access instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. note : the polarity of the direction bit is inverse of the nexus standard. starting in run-test/idle, ocd registers are accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in shift-dr: scan in the direction bit (1=read, 0=write) and the 7-bit address for the ocd register. 7. go to update-dr and re-enter select-dr scan. 8. in shift-dr: for a read operation, scan out the contents of the addressed register. for a write operation, scan in the new contents of the register. 9. return to run-test/idle. for any operation, the full 7 bits of the address must be provided. for write operations, 32 data bits must be provided, or the result will be undefined. for read ope rations, shifting may be termi- nated once the required number of bits have been acquired. 31.5.3.2 memory_service this instruction allows access to registers in an optional memory service unit. the 7-bit register index, a read/write control bit, and the 32-bit data is accessed through the jtag port. the data register is alternately interpreted by the sab as an address register and a data regis- ter. the sab starts in addres s mode after the memory_service instruction is selected, and table 31-17. nexus_access details instructions details ir input value 10000 (0x10) ir output value peb01 dr size 34 bits dr input value (address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx dr input value (data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dr input value (data write phase) dddddddd dddddddd dddddddd dddddddd xx dr output value (address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb dr output value (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr output value (data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
759 32099a?avr32?06/09 at32uc3l toggles between address and data mode each time a data scan completes with the busy bit cleared. starting in run-test/idle, memory service registers are accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in shift-dr: scan in the direction bit (1=read, 0=write) and the 7-bit address for the memory service register. 7. go to update-dr and re-enter select-dr scan. 8. in shift-dr: for a read operation, scan out the contents of the addressed register. for a write operation, scan in the new contents of the register. 9. return to run-test/idle. for any operation, the full 7 bits of the address must be provided. for write operations, 32 data bits must be provided, or the result will be undefined. for read ope rations, shifting may be termi- nated once the required number of bits have been acquired. 31.5.3.3 memory_sized_access this instruction allows access to the entire service access bus data area. data is accessed through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. not all units mapped on the sab bus may support all sizes of accesses, e.g., some may only support word accesses. the data register is alternately interpreted by the sab as an address register and a data regis- ter. the sab starts in address mode after the memory_sized_access instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. table 31-18. memory_service details instructions details ir input value 10100 (0x14) ir output value peb01 dr size 34 bits dr input value (address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx dr input value (data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx dr input value (data write phase) dddddddd dddddddd dddddddd dddddddd xx dr output value (address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb dr output value (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr output value (data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
760 32099a?avr32?06/09 at32uc3l the size field is encoded as i table 31-19 . starting in run-test/idle, sab data is accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in shift-dr: scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit address of the data to access. 7. go to update-dr and re-enter select-dr scan. 8. in shift-dr: for a read operation, scan out the contents of the addressed area. for a write operation, scan in the new contents of the area. 9. return to run-test/idle. for any operation, the full 36 bits of the address must be provided. for write operations, 32 data bits must be provided, or the result will be undefined. for read ope rations, shifting may be termi- nated once the required number of bits have been acquired. table 31-19. size field semantics size field value access size data alignment 00 byte (8 bits) address modulo 4 : data alignment 0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx 2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx 3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd 01 halfword (16 bits) address modulo 4 : data alignment 0: dddddddd dddddddd xxxxxxxx xxxxxxxx 1: not allowed 2: xxxxxxxx xxxxxxxx dddddddd dddddddd 3: not allowed 10 word (32 bits) address modulo 4 : data alignment 0: dddddddd dddddddd dddddddd dddddddd 1: not allowed 2: not allowed 3: not allowed 11 reserved n/a table 31-20. memory_sized_access details instructions details ir input value 10101 (0x15) ir output value peb01 dr size 39 bits dr input value (address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr dr input value (data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx dr input value (data write phase) dddddddd dddddddd dddddddd dddddddd xxxxxxx
761 32099a?avr32?06/09 at32uc3l 31.5.3.4 memory_word_access this instruction allows access to the entire service access bus data area. data is accessed through the 34 msb of the sab addr ess, a direction bit, and 32 bits of data. this instruction is identical to memory_sized_access except that it always does word sized accesses. the size field is implied, and the two lowest address bits are removed and not scanned in . note: this instruction was previously known as memory_access, and is provided for back- wards compatibility. the data register is alternately interpreted by the sab as an address register and a data regis- ter. the sab starts in address mode after the memory_word_access instruction is selected, and toggles between address and data mode each time a data scan completes with the busy bit cleared. starting in run-test/idle, sab data is accessed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in shift-dr: scan in the direction bit (1=read, 0=write) and the 34-bit address of the data to access. 7. go to update-dr and re-enter select-dr scan. 8. in shift-dr: for a read operation, scan out the contents of the addressed area. for a write operation, scan in the new contents of the area. 9. return to run-test/idle. for any operation, the full 34 bits of the address must be provided. for write operations, 32 data bits must be provided, or the result will be undefined. for read ope rations, shifting may be termi- nated once the required number of bits have been acquired. dr output value (address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb dr output value (dat a read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd dr output value (d ata write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb table 31-20. memory_sized_access details (continued) instructions details table 31-21. memory_word_access details instructions details ir input value 10001 (0x11) ir output value peb01 dr size 35 bits dr input value (address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar dr input value (data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx dr input value (data write phase) dddddddd dddddddd dddddddd dddddddd xxx
762 32099a?avr32?06/09 at32uc3l 31.5.3.5 memory_block_access this instruction allows ac cess to the entire sab data area. up to 32 bits of data is accessed at a time, while the address is sequentially incr emented from the previously used address. in this mode, the sab a ddress, size, and access direction is not provided with each access. instead, the previous address is auto-incremente d depending on the specified size and the pre- vious operation repeated. the address must be set up in advance with memory_size_access or memory_word_acce ss. it is allowed, but not required, to shift data after shifting the address. this instruction is primarily intended to speed up large quantities of sequential word accesses. it is possible to use it also for byte and halfword accesses, but the overhead in this is case much larger as 32 bits must still be shifted for each access. the following sequence should be used: 1. use the memory_size_access or memory_word_access to read or write the first location. 2. return to run-test/idle. 3. select the ir scan path. 4. in capture-ir: the ir output value is latched into the shift register. 5. in shift-ir: the instruction register is shifted by the tck input. 6. return to run-test/idle. 7. select the dr scan path. t he address will now have increment ed by 1, 2, or 4 (corre- sponding to the next byte, halfword, or word location). 8. in shift-dr: for a read operation, scan out the contents of the next addressed location. for a write operation, scan in the new contents of the next addressed location. 9. go to update-dr. 10. if the block access is not complete, return to select-dr scan and repeat the access. 11. if the block access is complete, return to run-test/idle. for write operations, 32 data bits must be pr ovided, or the result will be undefined. for read operations, shifting may be terminated once the required number of bits have been acquired. dr output value (address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb dr output value (data read phase) xeb dddddddd dddddddd dddddddd dddddddd dr output value (d ata write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb table 31-21. memory_word_access details (continued) instructions details table 31-22. memory_block_access details instructions details ir input value 10010 (0x12) ir output value peb01 dr size 34 bits dr input value (data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
763 32099a?avr32?06/09 at32uc3l the overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% trans- fer efficiency, or 2.1 mbytes per second with a 20 mhz tck frequency. 31.5.3.6 cancel_access if a very slow memory location is accessed du ring a sab memory access, it could take a very long time until the busy bit is cleared, and the sab becomes ready for the next operation. the cancel_access instruction pr ovides a possibility to abort an ongoing transfer and report a timeout to the jtag master. when the cancel_access instruction is select ed, the current access will be terminated as soon as possible. there are no guarantees about how long this will take, as the hardware may not always be able to cancel the access immedi ately. the sab is ready to respond to a new command when the busy bit clears. starting in run-test/idl e, cancel_access is acce ssed in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 31.5.3.7 sync this instruction allows external debuggers and testers to measure the ratio between the external jtag clock and the internal system clock. the sync data register is a 16-bit counter that counts down to zero using the internal system clock. the busy bit stays high until the counter reaches zero. starting in run-test/idle, sync inst ruction is used in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. dr input value (data write phase) dddddddd dddddddd dddddddd dddddddd xx dr output value (data read phase) eb dddddddd dddddddd dddddddd dddddddd dr output value (data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb table 31-22. memory_block_access details (continued) instructions details table 31-23. cancel_access details instructions details ir input value 10011 (0x13) ir output value peb01 dr size 1 dr input value x dr output value 0
764 32099a?avr32?06/09 at32uc3l 6. scan in an 16-bit counter value. 7. go to update-dr and re-enter select-dr scan. 8. in shift-dr: scan out the busy bit, and until the busy bit clears goto 7. 9. calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. return to run-test/idle. the full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined. when r eading status, shifting may be term inated once the required number of bits have been acquired. 31.5.3.8 avr_reset this instruction allows a debugger or tester to directly control separate reset domains inside the chip. the shift register contains one bit for each controllable reset domain. setting a bit to one resets that domain and holds it in reset. setting a bit to zero releases the reset for that domain. the avr_reset instruction can be used in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. 6. in shift-dr: scan in the value corresponding to the reset domains the jtag master wants to reset into the data register. 7. return to run-test/idle. 8. stay in run test idle for at least 10 tck clock cycles to let the reset propagate to the system. see the device specific document ation for the number of reset domains, and what these domains are. for any operation, all bits must be provided or th e result will be undefined. table 31-24. sync_access details instructions details ir input value 10111 (0x17) ir output value peb01 dr size 16 bits dr input value dddddddd dddddddd dr output value xxxxxxxx xxxxxxeb table 31-25. avr_reset details instructions details ir input value 01100 (0x0c) ir output value p0001
765 32099a?avr32?06/09 at32uc3l 31.5.3.9 chip_erase this instruction allows a programmer to completely erase all nonvolatile memories in a chip. this will also clear any security bits that are set, so the device can be accessed normally. in devices without non-volatile memories this instruction does nothing, and appears to complete immediately. the erasing of non-volatile memo ries starts as soon as the chi p_erase instruction is selected. the chip_erase instruction selects a 1 bit bypass data register. a chip erase operation should be performed as: 1. reset the system and stop the cpu from executing. 2. select the ir scan path. 3. in capture-ir: the ir output value is latched into the shift register. 4. in shift-ir: the instruction register is shifted by the tck input. 5. check the busy bit that was scanned out during shift-ir. if the busy bit was set goto 2. 6. return to run-test/idle. 31.5.3.10 halt this instruction allows a programmer to easily stop the cpu to ensure that it does not execute invalid code during programming. this instruction selects a 1-bit halt register. setting this bit to one halts the cpu. setting this bit to zero releases the cpu to run normally. the value shifted out from the data register is one if the cpu is halted. before releasing the halt command the cpu needs to be reset to ensure that it will start at the re set startup address. the halt instruction can be used in the following way: 1. select the ir scan path. 2. in capture-ir: the ir output value is latched into the shift register. 3. in shift-ir: the instruction register is shifted by the tck input. 4. return to run-test/idle. 5. select the dr scan path. dr size device specific. dr input value device specific. dr output value device specific. table 31-25. avr_reset details (continued) instructions details table 31-26. chip_erase details instructions details ir input value 01111 (0x0f) ir output value p0b01 where b is the busy bit. dr size 1 bit dr input value x dr output value 0
766 32099a?avr32?06/09 at32uc3l 6. in shift-dr: scan in the value 1 to halt the cpu, 0 to start cpu execution. 7. return to run-test/idle. table 31-27. halt details instructions details ir input value 11100 (0x1c) ir output value p0001 dr size 1 bit dr input value d dr output value d
767 32099a?avr32?06/09 at32uc3l 31.5.4 jtag data registers the following device specific registers can be selected as jtag scan chain depending on the instruction loaded in the jtag instruction register. additional registers exist, but are implicitly described in the functional description of the relevant instructions. 31.5.4.1 device identification register the device identification register contains a unique identifier for each product. the register is selected by the idcode instruction, which is the default instruction after a jtag reset. device specific id codes the different device configurations have different jtag id codes, as shown in table 31-28 . note that if the flash co ntroller is statically rese t, the id code will be undefined . 31.5.4.2 reset register the reset register is selected by the avr_reset instruction and co ntains one bit for each reset domain in the device. se tting each bit to one will keep that domain reset until the bit is cleared. msb lsb bit 31 28 27 12 11 1 0 device id revision part number manufacturer id 1 4 bits 16 bits 11 bits 1 bit revision this is a 4 bit number identifying the revision of the component. rev a = 0x0, b = 0x1, etc. part number the part number is a 16 bit code identifying the component. manufacturer id the manufacturer id is a 11 bit code identifying the manufacturer. the jtag manufacturer id for atmel is 0x01f. table 31-28. device and jtag id device name jtag id code (r is the revision number) at32uc3l064 0xr203003f at32uc3l032 0xr203403f at32uc3l016 0xr203803f bit 0 reset domain system system resets the whole chip, except the jtag itself.
768 32099a?avr32?06/09 at32uc3l 31.5.4.3 boundary-scan chain the boundary-scan chain has the ca pability of driving an d observing the logic levels on the dig- ital i/o pins, as well as driving and observing the logic levels between the digital i/o pins and the internal logic. typically, output value, output enable, and input data are all available in the boundary scan chain. the boundary scan chain is described in the bdsl (boundary scan description language) file available at the atmel web site.
769 32099a?avr32?06/09 at32uc3l 31.6 awire debug interface (aw) rev.: 2.1.0.0 31.6.1 features ? single pin debug system. ? half duplex asynchronous communication (uart compatible). ? full duplex mode for direct uart connection. ? compatible with jtag function ality, except boundary scan. ? failsafe packet-oriented protocol. ? read and write on-chip memory and program on -chip flash and fuses through sab interface. ? on-chip debug access through sab interface. ? asynchronous receiver or transmitter when the awire system is not used for debugging. 31.6.2 overview the awire debug interface (aw) offers a single pi n debug solution that is fully compatible with the functionality offered by the jtag interface, except boundary scan. this functionality includes memory access, programming capab ilities, and on-chip debug access. figure 31-8 on page 770 shows how the aw is connected in an av r32 device. the reset_n pin is used both as re set and debug pin. a special sequen ce on reset_n is needed to block the normal reset functionality and enable the aw. the service access bus (sab) interface cont ains address and data registers for the service access bus, which gives access to on-chip debug, programming, and other functions in the device. the sab offers several modes of access to the addre ss and data registers, as dis- cussed in section 31.6.6.8 . section 31.6.7 lists the supported awire commands and responses, with references to the description in this document. if the aw is not used for debugging, the awire ua rt can be used by the user to send or receive data with one stop bit, eight data bits, no parity bits, and one stop bit. this can be controlled through the awire user interface.
770 32099a?avr32?06/09 at32uc3l 31.6.3 block diagram figure 31-8. awire debug interface block diagram 31.6.4 i/o lines description 31.6.5 product dependencies in order to use this module, other parts of the system must be configured correctly, as described below. table 31-29. i/o lines description name description type data awire data multiplexed wit h the reset_n pin. input/output dataout awire data output in full duplex mode. output uart reset filter external reset aw_enable reset_n baudrate detector rw sz addr data crc aw control aw user interface sab interface reset command power manager cpu halt command flash controller chip_erase command awire debug interface pb sab
771 32099a?avr32?06/09 at32uc3l 31.6.5.1 i/o lines the pin used by aw is multiple xed with the reset_n pi n. the reset function ality is the default function of this pin. to enable the awire func tionality on the reset_n pin the user must enable the aw either by sending the enable sequence over the reset_n pin from an external awire master or by enabling the awire user interface. in full duplex mode data is received on the reset_n line, but transmitted on the dataout line. after sending the full_duplex command the dataout line is automatically enabled. all other peripheral functions on this pin is disabled. 31.6.5.2 power management when debugging through aw the system clocks are automatically turned on to allow debugging in sleep modes. 31.6.5.3 clocks the awire uart uses the internal 120 mhz rc oscillator (rc120m) as clock source for its operation. when enabling the aw the rc120m is automatically started. 31.6.5.4 external components the aw needs an external pullup on the reset_n pin to ensure that the pin is pulled up when the bus is not driven. 31.6.6 functional description 31.6.6.1 awire communication protocol the aw is accessed through the reset_n pin shown in table 31-29 on page 770 . the aw communicates through a uart operating at vari able baud rate (depending on a sync pattern) with one start bit, 8 data bits (lsb first), one stop bit, and no parity bits. the awire protocol is based upon command packets from an externalmaster and response packets from the slave (aw). the master always initiates communication and decides the baud rate. the packet contains a sync byte (0x55), a comm and/response byte, two length bytes (optional), a number of data bytes as defined in the length field (optional), and two crc bytes. if the com- mand/response has the most significant bit set, the command/response also carries the optional length and data fields. the crc field is not checked if the crc value transmitted is 0x0000. table 31-30. awire packet format field number of bytes description comment optional sync 1 sync pattern (0x55). used by the receiver to set the baud rate clock. no command/ response 1 command from the master or response from the slave. when the most significant bit is set the command/response has a length field. a response has the next most significant bit set. a command does not have this bit set. no
772 32099a?avr32?06/09 at32uc3l crc calculation the crc is calculated from th e command/response, length, and data fields. the polynomial used is the fcs16 (or crc-16-ccit) in reve rse mode (0x8408) and the starting value is 0x0000. example command below is an example command from the master with additional data. figure 31-9. example command example response below is an example response from the slave with additional data. figure 31-10. example response length 2 the number of bytes in the data field. ye s data length data according to command/ response. ye s crc 2 crc calculated with the fcs16 polynomial. crc value of 0x0000 makes the awire disregard the crc if the master does not support it. no table 31-30. awire packet format field number of bytes description comment optional baud_rate_clk data_pin ... field sync(0x55) command(0x81) length(msb) length(lsb) ... data(msb) data(lsb) crc(msb) crc(lsb) baud_rate_clk data_pin ... field sync(0x55) response(0xc1) length(msb) length(lsb) ... data(msb) data(lsb) crc(msb) crc(lsb)
773 32099a?avr32?06/09 at32uc3l avoiding drive contention when changing direction the awire debug protocol uses one dataline in both directions. to avoid both the master and the slave to drive this line when changing direction the aw has a built in guard time before it starts to drive the line. at reset this guard time is set to maximum (128 bit cycles), but can be lowered by the master upon command. the aw will release the line im mediately after the stop char acter has been transmitted. during the direction change there can be a period when the line is not driven. an external pullup has to be added to reset_n to keep the signal stable when neither master or slave is actively driving the line. 31.6.6.2 the reset_n pin normal reset functionality on the reset_n pin is disabled when using awire. however, the user can reset the system through the reset awire command. during awire operation the reset_n pin should not be conne cted to an external reset ci rcuitry, but disconnected via a switch or a jumper to avoid drive contention and speed problems. figure 31-11. reset circuitry and awire. 31.6.6.3 initializing the aw to enable aw, the user has to send a 0x55 patte rn with a baudrate of 1 khz on the reset_n pin. the aw is enabled after tr ansmitting this pattern and the us er can start transmitting com- mands. this pattern is not the sync pattern for the first command. after enabling the awire debug interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. to make the cpu run again set halt to zero using the halt command. 31.6.6.4 disabling the aw to disable aw, the user can keep the reset_n pin low for 100 ms. this will disable the aw, return reset_n to its normal fu nction, and reset the device. an awire master can also disable awire by sending the disable command. after acking the command the aw will be disabled and rese t_n returns to its normal function. reset_n aw debug interface jumper mcu power manager awire master connector board reset circuitry
774 32099a?avr32?06/09 at32uc3l 31.6.6.5 resetting the aw the awire master can reset the aw slave by pulling the reset_n pin low for 20 ms. this is equivalent to disabling and then enabling aw. 31.6.6.6 full duplex mode to avoid using special hardware when using a normal uart device as awire master, the awire slave has a full duplex mode where one pin is used as input and on pin is used as output. to enable this mode the full_duplex command must be sent. after sending the command, all responses will be sent on the dataout pin inst ead of the reset_n pin. commands are still received on the reset_n pin. 31.6.6.7 baud rate clock the communication speed is set by the master in the sync field of the command. the aw will use this to resynchronize its baud rate cloc k and reply on this frequency. the minimum fre- quency of the communication is 1 khz. the maximum frequency depends on the internal clock source for the aw (rc120m). the baud rate cl ock is generated by aw with the following formula: where is the baud rate frequency and is the frequency of the internal rc120m. tune is the value returned by the baud_rate response. to find the max frequency the user can issue the tune command to the aw to make it return the tune value. this value can be used to compute the . the maximum operational fre- quency ( ) is then: 31.6.6.8 service access bus the avr32 architecture offers a common interface for access to on-chip debug, programming, and test functions. these are mapped on a common bus called t he service acce ss bus (sab), which is linked to the awire through a bus mast er module, which also handles synchronization between the awire and sab clocks. for more information about the sab and a list of sab slaves see the service access bus chapter. sab clock when accessing the sab through the awire there are no limitations on baud rate frequency compared to chip frequency, although there must be an active system clock in order for the sab accesses to complete. if the system clock (clk_sys) is switched off in sleep mode, activity on the awire pin will restart the clk_sys automatica lly, without waking t he device from sleep. awire masters may optimize the transfer rate by adjusting the baud rate frequency in relation to the clk_sys. this ratio can be measur ed with the memory_speed_request command. when issuing the memory_speed_request comm and a counter value cv is returned. cv can be used to calculate the sab speed ( ) using this formula: f aw tune f br 8 ---------------------------- - = f br f aw f aw f brmax f brmax f aw 4 ------- = f sab
775 32099a?avr32?06/09 at32uc3l sab address mode the service access bus uses 36 address bits to address memory or registers in any of the slaves on the bus. the bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). all accesses must be aligned to the size of th e access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. two instructions exist to access the sab: memory_write and memory_read. these two instructions write and read words, halfwords, and bytes from the sab. busy reporting if the awire master, during a memory_wri te or a memory_read command, transmit another byte when the awire is still busy send ing the previous byte to the sab, the aw will respond with a memory_read_write_status error. see chapter section 31.6.8.5 for more details. the awire master should adjust its baudrate or delay between bytes when doing sab accesses to ensure that the sab is not overwhelmed with data. error reporting if a write is performed on a non-existing memory location the sab interface will respond with an error. if this happens, all further writes in this command will not be performed and the error and number of bytes written is reported in the memory_readwrite_status message from the aw after the write. if a read is performed on a non-existing memo ry location, the sab in terface will respond with an error. if this happens, the data bytes read after this event are not valid. the aw will include three extra bytes at the end of the transfer to indicate if the transfer was successful, or in the case of an error, how many valid bytes were received. 31.6.6.9 crc errors/nack response the aw will calculate a crc value when receiving the command, lengt h, and data fields of the command packets. if this value differs from the value from the crc field of the packet, the aw will reply with a nack response. otherwis e the command is carried out normally. an unknown command will be re plied with a nack response. in worst case a transmission error can happen in the length or command field of the packet. this can lead to the awire slave trying to receive a command with or without length (opposite of what the master intended) or receive an incorrect number of byte s. the awire slave will then either wait for more data when the master has finished or already have transmitted the nack response in congestion with the master. the master can implement a timeout on every com- mand and reset the slave if no response is returned after the timeout period has ended. f sab 3 f aw cv 3 ? ---------------- - =
776 32099a?avr32?06/09 at32uc3l 31.6.7 awire command summary the implemented awire commands are shown in the table below. the responses from the aw are listed in section 31.6.8 . all awire commands are described below, with a summary in table form. 31.6.7.1 aya this command asks the aw: ?are you aliv e?, where the aw should respond with an acknowledge. table 31-31. awire command summary command instruction description 0x01 aya ?are you alive?. 0x02 jtag_id asks aw to return the jtag idcode. 0x03 status_request request a status message from the aw. 0x04 tune tell the aw to report the current baud rate. 0x05 memory_speed_request reports the speed difference between the awire control and the sab clock domains. 0x06 chip_erase erases the flash and all volatile memories. 0x07 disable disables the aw. 0x08 full_duplex enables the dataout pin and puts the awire in full duplex mode, where all responses are sent on the dataout pin. 0x80 memory_write writes words, halfwords, or bytes to the sab. 0x81 memory_read reads words, halfwords, or bytes from the sab. 0x82 halt issues a halt command to the device. 0x83 reset issues a reset to the reset controller. 0x84 set_guard_time sets the guard time for the aw. table 31-32. command/response description notation command/response description command/response value shows the command/response value to put into the command/response field of the packet. additional data shows the format of the optional data field if applicable. possible responses shows the possi ble responses for this command. table 31-33. aya details command details command value 0x01 additional data n/a possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 )
777 32099a?avr32?06/09 at32uc3l 31.6.7.2 jtag_id this command instructs the aw to output the jtag idcode in the following response. 31.6.7.3 status_request asks the aw for a status message. 31.6.7.4 tune asks the aw for the current baud rate counter value. 31.6.7.5 memory_speed_request asks the aw for the relative speed between the awire clo ck (rc120m) and t he sab interface. 31.6.7.6 chip_erase this instruction allows a programmer to completely erase all nonvolatile memories in the chip. this will also clear any security bits that are set, so the device can be accessed normally. the command is acked immediately, but the status of the command can be monitored by checking table 31-34. jtag_id details command details command value 0x02 additional data n/a possible responses 0xc0: idcode ( section 31.6.8.3 ) 0x41: nack ( section 31.6.8.2 ) table 31-35. status_request details command details command value 0x03 additional data n/a possible responses 0xc4: status_info ( section 31.6.8.7 ) 0x41: nack ( section 31.6.8.2 ) table 31-36. tune details command details command value 0x04 additional data n/a possible responses 0xc3: baud_rate ( section 31.6.8.6 ) 0x41: nack ( section 31.6.8.2 ) table 31-37. memory_speed_request details command details command value 0x05 additional data n/a possible responses 0xc5: memory_speed ( section 31.6.8.8 ) 0x41: nack ( section 31.6.8.2 )
778 32099a?avr32?06/09 at32uc3l the chip erase ongoing bit in the status bytes received after the status_request command. 31.6.7.7 disable disables the aw. the aw will re spond with an ack response and then disable itself. 31.6.7.8 full_duplex enables the dataout pin as an ou tput pin. all respons es sent from the awire slave will be sent on this pin, instead of the reset_n pin, starting with the ack for the full_duplex command. 31.6.7.9 memory_write this command enables programming of memo ry/writing to registers on the sab. the memory_write command allows words, halfwords, and bytes to be programmed to a contin- uous sequence of addresses in one operation. before transferring the data, the user must supply: 1. the number of data bytes to write + 5 (size and starting address) in the length field. 2. the size of the transfer: words, halfwords, or bytes. 3. the starting address of the transfer. table 31-38. chip_erase details command details command value 0x06 additional data n/a possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 ) table 31-39. disable details command details command value 0x07 additional data n/a possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 ) table 31-40. disable details command details command value 0x07 additional data n/a possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 )
779 32099a?avr32?06/09 at32uc3l the 4 msb of the 36 bit sab address are submitted to gether with the size fi eld (2 bits). then fol- lows the 4 remaining address bytes and finally the data bytes. the size of the transfer is specified using the values from the following table: below is an example write command: 1. 0x55 (sync) 2. 0x80 (command) 3. 0x00 (length msb) 4. 0x09 (length lsb) 5. 0x25 (size and address msb, the two msb of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address lsb) 10. 0xca 11. 0xfe 12. 0xba 13. 0xbe 14. 0xxx (crc msb) 15. 0xxx (crc lsb) the length field is set to 0x0009 because there are 9 bytes of additional data: 5 address and size bytes and 4 bytes of data. the address and size field indicates that words should be written to address 0x5000 00004. the data written to 0x500000004 is 0xcafebabe. 31.6.7.10 memory_read this command enables reading of memory/registers on the service access bus (sab). the memory_read command allows words, halfwords, and bytes to be read from a continuous sequence of addresses in one operation. the user must supply: table 31-41. size field decoding size field description 00 byte transfer 01 halfword transfer 10 word transfer 11 reserved table 31-42. memory_write details command details command value 0x80 additional data size, address and data possible responses 0xc2: memory_readwrite_status ( section 31.6.8.5 ) 0x41: nack ( section 31.6.8.2 )
780 32099a?avr32?06/09 at32uc3l 1. the size of the data field: 7 (size and starting address + read length indicator) in the length field. 2. the size of the transfer: words, halfwords, or bytes. 3. the starting address of the transfer. 4. the number of bytes to read (max 65532). the 4 msb of the 36 bit sab addre ss are submitted together with th e size field (2 bits). the 4 remaining address bytes are submitted before the number of bytes to read. the size of the transfer is specified using the values from the following table: below is an example read command: 1. 0x55 (sync) 2. 0x81 (command) 3. 0x00 (length msb) 4. 0x07 (length lsb) 5. 0x25 (size and address msb, the two msb of this byte are unused and set to zero) 6. 0x00 7. 0x00 8. 0x00 9. 0x04 (address lsb) 10. 0x00 11. 0x04 12. 0xxx (crc msb) 13. 0xxx (crc lsb) the length field is set to 0x0007 because there ar e 7 bytes of additional data: 5 bytes of address and size and 2 bytes with the number of bytes to read. the address and size field indicates one word (four bytes) should be read from address 0x500000004. table 31-43. size field decoding size field description 00 byte transfer 01 halfword transfer 10 word transfer 11 reserved table 31-44. memory_read details command details command value 0x81 additional data size, address and length possible responses 0xc1: memdata ( section 31.6.8.4 ) 0xc2: memory_readwrite_status ( section 31.6.8.5 ) 0x41: nack ( section 31.6.8.2 )
781 32099a?avr32?06/09 at32uc3l 31.6.7.11 halt this command tells the cpu to halt code execution for safe programming. if the cpu is not halted during programming it can start executing partially loaded programs. to halt the proces- sor, the awire master should send 0x01 in the data field of the command. after programming the halting can be released by sending 0x00 in the data field of the command. 31.6.7.12 reset this command resets different domains in the part. the awire master sends a byte with the reset value. each bit in the reset value byte corresponds to a reset domain in the chip. if a bit is set the reset is activated and if a bit is not set the reset is released. the number of reset domains and their destinations are identical to the resets described in the jtag data registers chapter under reset register. 31.6.7.13 set_guard_time sets the guard time value in the aw, i.e. how long the aw will wait before starting its transfer after the master has finished. the guard time can be either 0x00 (128 bit lengths), 0x01 (16 bit lengths), 0x2 (4 bit lengths) or 0x3 (1 bit length). table 31-45. halt details command details command value 0x82 additional data 0x01 to halt the cpu 0x00 to release the halt and reset the device. possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 ) table 31-46. reset details command details command value 0x83 additional data reset value for each reset do main. the number of reset domains is part specific. possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 ) table 31-47. set_guard_time details command details command value 0x84 additional data guard time possible responses 0x40: ack ( section 31.6.8.1 ) 0x41: nack ( section 31.6.8.2 )
782 32099a?avr32?06/09 at32uc3l 31.6.8 awire response summary the implemented awire responses are shown in the table below. 31.6.8.1 ack the aw has received the command successfully and performed the operation. 31.6.8.2 nack the aw has received the command, but got a crc mismatch. 31.6.8.3 idcode the jtag idcode for this device. 31.6.8.4 memdata the data read from the address specified by the memory_read command. the last 3 bytes are status bytes from the read. the first status byte is the status of the command described in the table below. the last 2 bytes are the number of remaining data bytes to be sent in the data field of the packet when the error occurred. if the read was not successful all data bytes after the failure are undefined. a su ccessful word read (4 bytes) will look like this: table 31-48. awire response summary response instruction description 0x40 ack acknowledge. 0x41 nack not acknowledge. sent after crc errors and after unknown commands. 0xc0 idcode the jtag idcode. 0xc1 memdata values read from memory. 0xc2 memory_readwrite_status status after a memory_write or a memory_read command. ok, busy, error. 0xc3 baud_rate the current baudrate. 0xc4 status_info status information. 0xc5 memory_speed sab to awire speed information. table 31-49. ack details response details response value 0x40 additional data n/a table 31-50. nack details response details response value 0x41 additional data n/a table 31-51. idcode details response details response value 0xc0 additional data jtag idcode
783 32099a?avr32?06/09 at32uc3l 1. 0x55 (sync) 2. 0xc1 (command) 3. 0x00 (length msb) 4. 0x07 (length lsb) 5. 0xca (data msb) 6. 0xfe 7. 0xba 8. 0xbe (data lsb) 9. 0x00 (status byte) 10. 0x00 (bytes remaining msb) 11. 0x00 (bytes remaining lsb) 12. 0xxx (crc msb) 13. 0xxx (crc lsb) the status is 0x00 and all data read are valid. an unsuccessful four byte read can look like this: 1. 0x55 (sync) 2. 0xc1 (command) 3. 0x00 (length msb) 4. 0x07 (length lsb) 5. 0xca (data msb) 6. 0xfe 7. 0xxx (an error has occurred. data read is undefined. 5 bytes remaining of the data field) 8. 0xxx (more undefined data) 9. 0x02 (status byte) 10. 0x00 (bytes remaining msb) 11. 0x05 (bytes remaining lsb) 12. 0xxx (crc msb) 13. 0xxx (crc lsb) the error occurred after reading 2 bytes on the sab. the rest of the bytes read are undefined. the status byte indicates the error and the bytes remaining indicates how many bytes were remaining to be sent of the data field of the packet when the error occurred. table 31-52. memdata status byte status byte description 0x00 read successful 0x01 sab busy 0x02 bus error (wrong address) other reserved table 31-53. memdata details response details response value 0xc1 additional data data read, status byte, and byte count (2 bytes)
784 32099a?avr32?06/09 at32uc3l 31.6.8.5 memory_readwrite_status after a memory_write command this response is sent by aw. the response can also be sent after a memory_read command if aw encountered an error when receiving the address. the response contains 3 bytes, where t he first is the status of the command and the 2 next contains the byte count when the first erro r occurred. the first byte is encoded this way: 31.6.8.6 baud_rate the current baud rate in the aw. see section 31.6.6.7 for more details. 31.6.8.7 status_info a status message from aw. table 31-54. memory_readwrite_status status byte status byte description 0x00 write successful 0x01 sab busy 0x02 bus error (wrong address) other reserved table 31-55. memory_readwrite_status details response details response value 0xc2 additional data status byte and byte count (2 bytes) table 31-56. baud_rate details response details response value 0xc3 additional data baud rate table 31-57. status_info contents bit number name description 15-9 reserved 8protected the protection bit in the in ternal flash is set. sab acce ss is restricted. this bit will read as one during reset. 7 sab busy the sab bus is busy with a previous transf er. this could indi cate that the cpu is running on a very slow clock, the cpu clock has stopped for some reason or that the part is in constant reset. 6 chip erase ongoing the chip erase operation has not finished. 5 cpu halted this bit will be set if the cpu is halted. this bit will read as zero during reset. 4-1 reserved 0 reset status this bit will be set if aw has reset the cpu using the reset command.
785 32099a?avr32?06/09 at32uc3l 31.6.8.8 memory_speed counts the number of rc120m clock cycles it takes to sync one message to the sab interface and back again. the sab clock speed ( ) can be calculated using the following formula: 31.6.9 security restrictions when the security fuse in the flash is programmed, the following awire commands are limited: ? memory_write ? memory_read unlimited access to these instructions is restored when the security fuse is erased by the chip_erase awire command. note that the security bit will read as programmed and block these instructions also if the flash controller is statically reset. table 31-58. status_info details response details response value 0xc4 additional data 2 status bytes table 31-59. memory_speed details response details response value 0xc5 additional data clock cycle count (ms) f sab f sab 3 f aw cv 3 ? ---------------- - =
786 32099a?avr32?06/09 at32uc3l 32. electrical characteristics 32.1 disclaimer all values in this chapter are preliminary and subject to change without further notice. 32.2 absolute maximum ratings* 32.3 supply characteristics the following characteristi cs are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise specified and are certified for a junction temperature up to t j = 100c. table 32-1. absolute maximum ratings operating temperature..................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or other condi- tions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended peri- ods may affect device reliability. storage temperature...................................... -60c to +150c voltage on all pins (except those noted below) .....................................................................-0.3v to v vddio +0.3v voltage on pa11, pa13, pa 20............... .-0.3v to v vddin +0.3v voltage on 5v tolerant pins with respect to ground .... -0.3v to 5.5v dc current per i/o pin................................................. tbd ma dc current v cc and gnd pins .............. ........... .......... tbd ma maximum operating voltage (vddcore) ...................... 1.98v maximum operating voltage (vddio, vddin).................. 3.6v table 32-2. supply characteristics symbol parameter voltage min max unit v vddio dc supply peripheral i/os 1.62 3.6 v v vddin dc supply peripheral i/os, 1.8v single supply mode 1.62 1.98 v dc supply peripheral i/os and internal regulator, 3.3v single supply mode 1.98 3.6 v v vddcore dc supply core 1.62 1.98 v v vddana analog supply voltage 1.62 1.98 v v advrefp analog reference voltage 1.62 v vddana v
787 32099a?avr32?06/09 at32uc3l note: 1. slower rise time requir es external power-on circuit. 32.4 clock characteristics these parameters are given in the following conditions: v vddcore = 1.62 to 1.98v temperature = -40c to 85c table 32-3. supply rise rates and order symbol parameter rise rate min max unit comment v vddio dc supply peripheral i/os 0 2.5 v/s v vddin dc supply peripheral i/os and internal regulator 0.002 (1) 2.5 v/s v vddcore dc supply core 0 2.5 v/s rise before or at the same time as vddio v vddana analog supply voltage 0 2.5 v/s rise together with vddcore table 32-4. clock frequencies symbol parameter conditions min max units f cpu cpu clock frequency 50 mhz f pba pba clock frequency 50 mhz f pbb pbb clock frequency 50 mhz
788 32099a?avr32?06/09 at32uc3l 32.5 power consumption the values in table 32-5 are measured values of power consumption under the following condi- tions, except where noted: ? operating conditions ?v ddio = 1.8v ?v ddcore =1.8v ?t a = 25 c ? oscillators ? osc0 stopped ? osc32k running with external 32 khz crystal ? dfll running at 50 mhz with osc32k as reference ? clocks: ? dfll used as main clock source ? cpu and hsb clock undivided ? pba and pbb clocks divided by 8 ? all peripheral clocks running ? i/os are inactive with internal pull-up figure 32-1. measurement schematic, all modes except shutdown amp0 vddin vddcore vddana vddio
789 32099a?avr32?06/09 at32uc3l figure 32-2. measurement schematic, shutdown mode amp0 vddin vddcore vddana vddio table 32-5. power consumption for different modes mode conditions measured on consumption typ unit active cpu running a recursive fibonacci algorithm from flash with 1 wait state amp0 300 a/mhz idle amp0 150 a/mhz frozen amp0 90 a/mhz standby amp0 70 a/mhz stop amp0 30 a deepstop amp0 20 a static ast and osc32k running amp0 7 a ast and osc32k stopped amp0 5 a shutdown ast and osc32k running amp0 1.5 a ast and osc32k stopped amp0 0.1 a
790 32099a?avr32?06/09 at32uc3l table 32-6. power consumption by peripheral in active mode peripheral consumption typ unit acifb tbd a/mhz adcifb tbd ast tbd aw tbd cat tbd eic tbd flashcdw tbd freqm tbd gpio tbd hmatrix tbd intc tbd pdca tbd pm tbd pwma tbd sau tbd scif tbd spi tbd tc tbd twim tbd twis tbd usart tbd wdt tbd
791 32099a?avr32?06/09 at32uc3l 32.6 i/o pad characteristics note: 1. ibis simulated values note: 1. ibis simulated values table 32-7. normal i/o pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance 105k ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd v vddio +0.3 v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio -0.4 v i ol output low-level current 2 ma i oh output high-level current 2 ma i leak input leakage current pull-up resistors disabled 1 a c in input capacitance 3 (1) pf table 32-8. high-drive i/o pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance 105k ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd v vddio +0.3 v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio -0.4 v i ol output low-level current 4ma i oh output high-level current 4ma i leak input leakage current pull-up resistors disabled 1 a c in input capacitance 5 (1) pf table 32-9. 5v tolerant i/o pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance tbd ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd 5.5v v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio -0.4 v i ol output low-level current tbd ma i oh output high-level current tbd ma i leak input leakage current pull-up resistors disabled tbd a c in input capacitance tbd pf
792 32099a?avr32?06/09 at32uc3l table 32-10. twi pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance tbd ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd 5.5v v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio -0.4 v i ol output low-level current tbd ma i oh output high-level current tbd ma i leak input leakage current pull-up resistors disabled tbd a c in input capacitance tbd pf slew rate tbd v/s table 32-11. smbus compliant pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance tbd ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd 5.5v v v ol output low-level voltage 0.4 v input voltage range v oh output high-level voltage v vddio -0.4 v i ol output low-level current tbd ma i oh output high-level current tbd ma i leak input leakage current pull-up resistors disabled tbd a c in input capacitance tbd pf slew rate tbd v/s table 32-12. oscillator i/o pad characteristics symbol parameter condition min typ max units r pullup pull-up resistance 30k ohm v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage tbd 5.5v v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio -0.4 v i ol output low-level current tbd ma
793 32099a?avr32?06/09 at32uc3l 32.7 oscillator characteristics 32.7.1 oscillator 0 characteristics 32.7.1.1 digital clock characteristics the following table describes the characteristics for the oscillator when a digital clock is applied on xin. 32.7.1.2 crystal oscillator characteristics the following table describes the characteristics for the oscillator when a crystal is connected between xin and xout. i oh output high-level current tbd ma i leak input leakage current pull-up resistors disabled tbd a c in input capacitance tbd pf table 32-12. oscillator i/o pad characteristics symbol parameter condition min typ max units table 32-13. digital clock ch aracteristics symbol parameter conditions min typ max units f cpxin xin clock frequency 50 mhz t chxin xin clock duty cycle 40 60 % c in xin input capacitance tbd pf r in optional pull-down resistor tbd k table 32-14. crystal oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) tbd pf c l equivalent load capacitance tbd pf t st startup time tbd ms i osc current consumption active mode @3mhz. gain = g0 tbd a active mode @16mhz. gain = g3
794 32099a?avr32?06/09 at32uc3l 32.7.2 32 khz crystal oscillator characteristics note: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance. table 32-16. 32 khz crystal oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 hz t st startup time r s = tbd k , c l = tbd pf (1) tbd ms c l equivalent load capacitance tbd tbd pf i osc current consumption active mode 1.5 a
795 32099a?avr32?06/09 at32uc3l 32.7.3 dfll characteristics 32.7.4 rc120m characteristics 32.7.5 rc32k 32.7.6 rcsys 32.8 flash characteristics table 32-21 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. the fsw bit in the flashcdw fsr register controls the number of wait states used wh en accessing the flash memory. table 32-17. digital frequency locked loop characteristics symbol parameter conditions min typ max unit f out output frequency 20 150 mhz f in input frequency 0.02 16 mhz i dfll current consumption active mode tbd a/mhz t startup startup time tbd cycles t lock lock time f in = 32khz, f out = 50mhz tbd ms table 32-18. internal 120mhz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency 120 mhz i rc120m current consumption active mode tbd a t startup startup time tbd cycles table 32-19. 32khz rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency 20 32 44 khz i rc32k current consumption active mode tbd a t startup startup time tbd cycles table 32-20. system rc oscillator characteristics symbol parameter conditions min typ max unit f out output frequency 115 khz i rcsys current consumption active mode tbd a t startup startup time tbd cycles tuning resolution tbd %
796 32099a?avr32?06/09 at32uc3l 32.9 analog characteristics 32.9.1 regulator characteristics 32.9.1.1 electrical characteristics 32.9.1.2 decoupling requirements table 32-21. maximum operating frequency flash wait states read mode maximum operating frequency 1 high speed read mode 50mhz 0 25mhz 1 normal read mode 30mhz 0 15mhz table 32-22. electrical characteristics symbol parameter condition min typ max units i out maximum dc output current with v vddin = 3.3v tbd ma maximum dc output current with v vddin = 1.8v tbd ma i scr static current of internal regulator normal mode tbd a low power mode tbd a table 32-23. decoupling requirements symbol parameter condition typ techno. units c in1 input regulator capacitor 1 tbd nf c in2 input regulator capacitor 2 10 f c out1 output regulator capacitor 1 100 nf c out2 output regulator capacitor 2 2.2 tantalum 0.5 797 32099a?avr32?06/09 at32uc3l 32.9.2 por 32.9.3 sm33 32.9.4 por33 32.10 timing characteristics 32.10.1 reset_n characteristics table 32-24. power-on reset characteristics symbol parameter condition min typ max units v pot por threshold voltage (rising) 1.5 v por threshold voltage (falling) 1.3 v table 32-25. sm33 characteristics symbol parameter condition min typ max units v th voltage threshold onsm = ?1?, without calibration 1.8 v table 32-26. por33 characteristics symbol parameter condition min typ max units v th threshold voltage rising 1.5 v table 32-27. reset_n waveform parameters symbol parameter conditions min max units t reset reset_n minimum pulse length 10 ns
798 32099a?avr32?06/09 at32uc3l 33. mechanical characteristics 33.1 thermal considerations 33.1.1 thermal data table 33-1 summarizes the thermal resistance data depending on the package. 33.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 33-1 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 33-1 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in the section 32.5 on page 788 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 33-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air tqfp48 tbd c/w jc junction-to-case thermal resistance tqfp48 tbd ja junction-to-ambient thermal resistance still air qfn48 tbd c/w jc junction-to-case thermal resistance qfn48 tbd ja junction-to-ambient thermal resistance still air tllga48 tbd c/w jc junction-to-case thermal resistance tllga48 tbd t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
799 32099a?avr32?06/09 at32uc3l 33.2 package drawings figure 33-1. tqfp-48 package drawing table 33-2. device and package maximum weight tbd mg table 33-3. package characteristics moisture sensitivity level tbd table 33-4. package reference jedec drawing reference ms-026 jesd97 classification e3
800 32099a?avr32?06/09 at32uc3l figure 33-2. qfn-48 package drawing table 33-5. device and package maximum weight tbd mg table 33-6. package characteristics moisture sensitivity level tbd table 33-7. package reference jedec drawing reference m0-220 jesd97 classification e3
801 32099a?avr32?06/09 at32uc3l figure 33-3. tllga-48 package drawing table 33-8. device and package maximum weight tbd mg table 33-9. package characteristics moisture sensitivity level tbd table 33-10. package reference jedec drawing reference m0-220 jesd97 classification e3
802 32099a?avr32?06/09 at32uc3l 33.3 soldering profile table 33-11 gives the recommended soldering profile from j-std-20. a maximum of three reflow passes is allowed per component. table 33-11. soldering profile profile feature green package average ramp-up rate (217c to peak) 3c/s max preheat temperature 175c 25c 60-120 s temperature maintained above 217c 60-150 s time within 5 c of actual peak temperature 30 s peak temperature range 260c ramp-down rate 6c/s max time 25 c to peak temperature 8 minutes max
803 32099a?avr32?06/09 at32uc3l 34. ordering information table 34-1. ordering information device ordering code carrier type package package type temperature operating range at32uc3l064 at32uc3l064-aut tray tqfp 48 jesd97 classification e3 industrial (-40 c to 85 c) at32uc3l064-aur tape & reel tqfp 48 at32uc3l064-zaut tray qfn 48 at32uc3l064-zaur tape & reel qfn 48 at32uc3l064-d3ur tape & reel tllga 48 at32uc3l032 at32uc3l032-aut tray tqfp 48 at32uc3l032-aur tape & reel tqfp 48 at32uc3l032-zaut tray qfn 48 at32uc3l032-zaur tape & reel qfn 48 at32uc3l032-d3ur tape & reel tllga 48 at32uc3l016 at32uc3l016-aut tray tqfp 48 AT32UC3L016-AUR tape & reel tqfp 48 at32uc3l016-zaut tray qfn 48 at32uc3l016-zaur tape & reel qfn 48 at32uc3l016-d3ur tape & reel tllga 48
804 32099a?avr32?06/09 at32uc3l 35. errata 35.1 rev. c 35.1.1 scif 1. a reset from supply monitor 33 will be registered as por a supply monitor 33 reset will not be detected in the rese t cause register (rcause) as bod33, it will be detected as a power-on reset (por). fix/workaround none. 35.1.2 spi 1. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset. 2. spi bad serial clock generation on 2nd chip select when scbr = 1, cpol=1, and ncpha=0 when multiple cs are in use, if one of the baudrates equals 1 and one of the others does not equal 1, and cpol=1 and cpha=0, an a dditional pulse will be generate d on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if cpol=1 and cpha=0. 3. spi data transfer hangs with csaat=1 in csr0 and modfdis=0 in mr when csaat=1 in csr0 and mode fault detecti on is enabled (modfd is=0 in mr), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to modfdis in mr. 4. disabling spi has no effect on the tdre flag disabling spi has no effect on tdre whereas the write data command is filtered when spi is disabled. this means that as soon as the spi is disabled it becomes impossible to reset the tdre flag by writing in the tdr. so if the spi is disabled during a pdca transfer, the pdca will continue to write data in the tdr (as tdre stays hi gh) until its buffer is empty, and all data written after the disable command is lost. fix/workaround disable the pdca, 2 nop (minimum), disable spi. when you want to continue the transfer: enable spi, enable pdca. 35.2 rev. b 35.2.1 processor and architecture 1. rets behaves incorrectly when mpu is enabled rets behaves incorrectly when mpu is enabled and mpu is configured so that system stack is not readable in unprivileged mode.
805 32099a?avr32?06/09 at32uc3l fix/workaround make system stack readable in unprivileged mode, or return from supervisor mode using rete instead of rets. this requires: 1. changing the mode bits from 001 to 110 before issuing the instruction. updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. even if this step is described in general as not safe in the uc technical reference manual, it is safe in th is very specific case. 2. execute the rete instruction. 35.2.2 flashcdw 1. chip erase when performing chip erase, the device may report that it is protected (ir=0x11) and that chiperase failed, even if the chip erase was succesful. fix/workaround perform a reset before any further read and programming. 2. fuse programming programming of fuses does not work. fix/workaround do not program fuses. all fuses will be erased during chiperase command. 3. wait 500 ns before reading from the flash after switching read mode after switching between normal read mode and high-speed read mode, the application must wait at least 500 ns before attempting any access to the flash. fix/workaround two workarounds exist: 1. make sure that the appropriate instructions are executed from ram, and that a waiting- loop is executed from ram waiting 500ns or more before executing from flash. 2. execute from flash with a clock with period longer than 500 ns. this guarantees that no new read access is attempted before the flash has had time to settle in the new read mode. 4. version register reads 0x100 the version register reads 0x100 instead of 0x102. fix/workaround none. 35.2.3 hmatrix 1. in the hmatrix pras and prbs regi sters mxpr fields are only two bits in the hmatrix pras and prbs registers mxpr fields are only two bits wide, instead of four bits. the unused bits are undefined when reading the registers. fix/workaround mask undefined bits when reading pras and prbs. 35.2.4 pdca 1. pcontrol.chxres is nonfunctional pcontrol.chxres is nonfuncti onal. counters are reset at power-on, and cannot be reset by software. fix/workaround sw needs to keep history of performance counters. 2. transfer error will stall a transmit peripheral handshake interface.
806 32099a?avr32?06/09 at32uc3l if a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the acti ve channel will stall and the pdca will not do any more transfers on the affected peripheral handshake interface. fix/workaround disable and then enable the peripheral after the transfer error. 3. version register reads 0x120 the version register reads 0x120 instead of 0x122. fix/workaround none. 35.2.5 gpio 1. gpio interrupt flag can not be cleared when interrupts are disabled the gpio interrupt flag can not be cleared unless the interrupt is enabled for the pin. fix/workaround enable interrupt for the corresponding pin, then clear the interrupt flag. 2. version register reads 0x210 the version register reads 0x210 instead of 0x211. fix/workaround none. 35.2.6 pm 1. ocp and high frequency clock sources ocp does not work if the main cl ock source is a high frequency clock. if the frequency of the source exceeds the maximum frequency of the criposc the ocp will generate an inter- rupt and switch clock source to the slow clock upon enabling the ocp, even if the cpu clock is divided to a legal frequency. fix/workaround do not use clock sources with frequencies higher that the maximum cpu frequency while using the ocp. 2. config register reads 0x4f the config register reads 0x4f instead of 0x43. fix/workaround none. 3. pb writes via debugger in sleep modes are blocked during sleepwalking during sleepwalking, pb writes performed by a debugger will be di scarded by all pb mod- ules except the module that is requesting the clock. fix/workaround none. 4. version register reads 0x400 the version register reads 0x400 instead of 0x411. fix/workaround none. 5. wcause register should not be used the wcause register should not be used. fix/workaround none.
807 32099a?avr32?06/09 at32uc3l 6. clock failure detector does not work in some cases the clock failure detector will not detect if the cpu clock stops. in this case the cpu will halt operation. fix/workaround none. 35.2.7 scif 1. a reset from supply monitor 33 will be registered as por a supply monitor 33 reset will not be detected in the rese t cause register (rcause) as bod33, it will be detected as a power-on reset (por). fix/workaround none. 2. the dfll should be slowed down before disabled the frequency of the dfll should be set to minimum before disabled. fix/workaround before disabling the dfll the value of the coarse register should be set to zero. 3. writing to scif icr masks new interrupts received in the same clock cycle writing to scif icr masks any new scif interrupt received in the same clock cycle, regardless of write value. fix/workaround: for every interrupt except boddet, sm33det, and vregok the clksr register can be read to detect new interrup ts. boddet, sm33det and vre gok interrupts will not be gen- erated if they occur when writing scif icr. 4. fine value for dfll is not correct when dithering is disabled in open loop mode, the fine value used by the dfll dac is offseted by two compared to the value written to the dfll0conf.fine field. i. e. the value to the dfll dac is dfll0conf.fine-0x002. if dfll0conf.fine is written to 0x000, 0x001 or 0x002 the value to the dfll dac will be 0x1f e, 0x1ff or 0x000 respectively. fix/workaround write the desired value added by two to the dfll0conf.fine field. 5. bodversion register reads 0x100 the bodversion register reads 0x100 instead of 0x101. fix/workaround none. 7. brifa is non-functional brifa is non-functional. fix/workaround none. 8. vregcr deepmodedisable bit is not readable vregcr deepmodedisable bit is not readable. fix/workaround none. 9. dfll step size should be 7 or lower below 30 mhz if max step size is above 7, the dfll might not lock at the correct frequency if the target fre- quency is below 30 mhz.
808 32099a?avr32?06/09 at32uc3l fix/workaround if the target frequency is be low 30 mhz, use max step size (dfll0maxstep.maxstep) of 7 or lower. 10. generic clock sources are kept running in sleep modes if a clock is used as a source for a generic clock when going to a sleep mode where clock sources are stopped, the source of the generic cl ock will be kept running. please refer to the power manager chapter for details about sleep modes. fix/workaround disable generic clocks before going to sleep modes where clock sources are stopped to save power. 11. dfll clock is unstable with a fast reference clock the dfll clock can be unstable when a fast clock is used as reference clock in closed loop mode. fix/workaround use the 32 khz crystal oscillator clock or a cl ock with similar frequency as dfllif reference clock. 12. dfllif indicates coarse lock too early the dfllif might indicate coarse lock too early, the dfll will lo se coarse lock and regain it later. fix/workaround use max step size (dfll0maxs tep.maxstep) of 4 or higher. 13. dfllif dithering does not work the dfllif dithering does not work. fix/workaround none. 14. scif version register reads 0x100 the version register reads 0x100 instead of 0x102. fix/workaround none. 15. dfllversion register reads 0x200 the dfllversion register reads 0x200 instead of 0x201. fix/workaround none. 16. rccrversion register reads 0x100 the rccrversion register re ads 0x100 instead of 0x101. fix/workaround none. 17. osc32version register reads 0x100 the osc32version register reads 0x100 instead of 0x101. fix/workaround none. 18. vregversion register reads 0x100 the vregversion register reads 0x100 instead of 0x101. fix/workaround none.
809 32099a?avr32?06/09 at32uc3l 19. rc120mversion register reads 0x100 the rc120mversion register reads 0x100 instead of 0x101. fix/workaround none. 20. gclk5 is non-functional gclk5 is non-functional. fix/workaround none. 35.2.8 wdt 1. clearing of the wdt in window mode in window mode, if the wdt is cleared clk_wdt cycles after entering the window. the counter will be clea red, but will not exit the window. if this occurs, the sr.window bit will not be cleared after clearing the wdt. fix/workaround check sr.window immediately af ter clearing the wdt. if set then clear the wdt once more. 2. version register reads 0x400 the version register reads 0x400 instead of 0x402. fix/workaround none. 35.2.9 freqm 1.) measured clock (clk_msr) sources 15-17 are shifted clksel = 14 selects the rc120m aw clock, clksel = 15 selects the rc120m clock, and clksel = 16 selects the rc32k clock as s ource for the measured clock (clk_msr). fix/workaround none. 2.) gclk5 can not be used as source for the clk_msr the frequency for gclk5 can not be measured by the freqm. fix/workaround none. 35.2.10 spi 1. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset. 2. spi bad serial clock generation on 2nd chip select when scbr = 1, cpol=1, and ncpha=0 when multiple cs are in use, if one of the baudrates equals 1 and one of the others does not equal 1, and cpol=1 and cpha=0, an a dditional pulse will be generate d on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if cpol=1 and cpha=0. 3. spi data transfer hangs with csaat=1 in csr0 and modfdis=0 in mr 2 tban
810 32099a?avr32?06/09 at32uc3l when csaat=1 in csr0 and mode fault detecti on is enabled (modfd is=0 in mr), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to modfdis in mr. 4. disabling spi has no effect on the tdre flag disabling spi has no effect on tdre whereas the write data command is filtered when spi is disabled. this means that as soon as the spi is disabled it becomes impossible to reset the tdre flag by writing in the tdr. so if the spi is disabled during a pdca transfer, the pdca will continue to write data in the tdr (as tdre stays hi gh) until its buffer is empty, and all data written after the disable command is lost. fix/workaround disable the pdca, 2 nop (minimum), disable spi. when you want to continue the transfer: enable spi, enable pdca. 35.2.11 twi 1. twim version register is zero twim version register (vr) reads zero instead of 0x101. fix/workaround none. 2. twis version register is zero twis version register (vr) reads zero instead of 0x112. fix/workaround none. 3. twis cr.stren does not wo rk in deep sleep modes when the device is in stop, deepstop or static sleep modes, address reception will not wake device if both cr.soam and cr.stren are set. fix/workaround do not set both cr.stren and cr.soam if the device needs to wake from deep sleep. 4. twi pads are not smbus compatible the twi pads draws current when the pins ar e supplied with 3.3v and the part is left unpowered. fix/workaround none. 5. pa21, pb04, and pb05 are not 5v tolerant pins pa21, pb04, and pb05 are only 3.3 v tolerant. fix/workaround none. 6. pb04 smbalert function should not be used the smbalert function from twims0 should not be selected on pin pb04. fix/workaround none. 7. twi0.twck on pb05 is non-functional twi0.twck on pb05 is non-functional. fix/workaround use twi0.twck on other pins.
811 32099a?avr32?06/09 at32uc3l 8. twim stop bit in imr always read as zero the stop bit in imr always reads as zero. fix/workaround none. 35.2.12 pwma 1. parameter register reads 0x2424 the parameter register reads 0x2424 instead of 0x24. fix/workaround none. 2. open drain mode does not work the open drain mode does not work. fix/workaround none. 3. version register reads 0x100 the version register reads 0x100 instead of 0x101. fix/workaround none. 4. writing to the duty cycle registers wh en the timebase counter overflows can give undefined result the duty cycle registers will be corrupted if writt en when the timebase co unter overflows. if the duty cycle registers are written exactly when the timebase counter overflows at top, the duty cycle registers may become corrupted. fix/workaround write to the duty cycle registers only directly after the timebase overflow bit in the status register is set. 35.2.13 sau 1. idle bit reads as zero the idle bit reads as zero. fix/workaround none. 2. open mode is not functional the open mode is not functional. fix/workaround none. 3. version register reads 0x100 the version register reads 0x100 instead of 0x110. fix/workaround none. 35.2.14 adcifb 1. pendetect in sleep modes without clk_adcifb will not wake the system the pendetect will not wake the system fr om a sleep mode if the clock for the adcifb (clk_adcifb) is turned off. fix/workaround
812 32099a?avr32?06/09 at32uc3l use a sleep mode where clk_adcifb is not turned off to wake the part using pendetect. 2. 8-bit mode is not working do not use the 8-bit mode of the adcifb. fix/workaround use the 10-bit mode and shift right by 2 bits. 3. adc channels six to eight is non-functional adc channels six to eight is non-functional. fix/workaround none. 4. version register reads 0x100 the version register reads 0x100 instead of 0x101. fix/workaround none. 35.2.15 acifb 1. negative offset the static offset of the analog comparator is appriximately -50mv. fix/workaround none. 2. generic clock sources in sleep modes the acifb should not use rc32k, or clk_1k as generic clock source if the chip uses sleep modes. fix/workaround none. 3. version register reads 0x200 the version register reads 0x200 instead of 0x212. fix/workaround none. 4. confw.wevsrc and confw.weven are no t correctly described in the user interface confw.wevsrc is only two bits instead of three bits wide. only values 0, 1, and 2 can be written to this register. confw.weven is in bit position 10 instead of 11. fix/workaround only write values 0, 1, and 2 to confw.wevsrc. when reading confw.wevsrc, dis- regard the third bit. read/write bit 10 to access confw.weven. 35.2.16 usart 1. the rts output does not function correctly in hardware handshaking mode the rts signal is not generated properly when the usart receives data in hardware hand- shaking mode. when the peripheral dma receive buffer becomes full, the rts output should go high, bu t it will stay low. fix/workaround do not use the hardware handshaking mode of the usart. if it is necessary to drive the rts output high when the peripheral dma receive buffer becomes full, use the normal mode of the usart. configure the peripheral dma controller to signal an interrupt when
813 32099a?avr32?06/09 at32uc3l the receive buffer is full. in the interrupt handler code, write a one to the rtsdis bit in the usart control register (cr). this will drive th e rts output high. afte r the next dma trans- fer is started and a receive buffer is available, write a one to the rtsen bit in the usart cr so that rts will be driven low. 35.2.17 tc 1. when the main clock is rcsys, ti mer_clock5 is eq ual to pba clock when the main clock is gen erated from rcsys, timer_cl ock5 is equal to pba clock and not pba clock / 128. fix/workaround none. 35.2.18 cat 1. switch off discharge current when reaching 0v the discharge current will swit ch off when reaching mgcfg1 .max, not when reaching 0v. fix/workaround none. 2. cat external capacitors are not clamped to ground when cat is idle the cat module does not clamp the external capacitors to ground when it is idle. the capacitors are left floating, so they could accumulate small amounts of charge. fix/workaround none. 3. cat dishift field is stuck at zero the dishift field in the mgcfg1, tgacfg1, tgbcfg1, and atcfg1 registers is stuck at zero and cannot be written to a different value. capacitor discharge time will be deter- mined only by the dilen field. fix/workaround none. 4. cat acctrl bit is stuck at zero the acctrl bit in the mgcfg2 register is stuck at zero and cannot be written to one. the analog comparators will be constantly enabled. fix/workaround none. 5. cat consen field is stuck at zero the consen field in the mgcfg2 register is stuck at zero and cannot be written to a differ- ent value. the cat consensus filter does not function properly, so termination of qmatrix data acquisition is controlled only by the max field in mgcfg1. fix/workaround none. 6. version register reads 0x100 the version register reads 0x100 instead of 0x200. fix/workaround none. 35.2.19 awire 1. awire pb mapping and pb clock mask number
814 32099a?avr32?06/09 at32uc3l the awire pb has a different pb address and pb clock mask number. fix/workaround use awire pb address 0xffff6 c00 and pb clock (pbamask) 24. 2. sab multiaccess reads are not working reading more than one word, halfword, or byte in one command is not workingcorrectly. fix/workaround split the access into several single word, halfword, or byte accesses. 3. if a reset happens during the last sab write, the awire will stall if a reset happens during the last word, halfword or byte writ e the awire will wait forever for an acknowledge from the sab. fix/workaround reset the awire by keeping th e reset_n line low for 100 ms. 4. awire enable does not work in static mode awire enable does not work in static mode. fix/workaround none. 5. version register reads 0x200 the version register reads 0x200 instead of 0x210. fix/workaround none. 35.2.20 gloc 1. gloc is non-functional gloc is non-functional. fix/workaround none. 35.2.21 i/o pins 1. pb10 is not 3.3v tolerant pb10 should be grounded on the pcb and left unused. fix/workaround none. 2. analog multiplexing consumes extra power current consumption on vddio increases when the voltage on analog inputs is close to vddio/2. fix/workaround none. 3. pa02, pb01, pb04, pb05, reset_n have half of the pullup strength pins pa02, pb01, pb04, pb05, reset_n have half of the specif ied pullup strength. fix/workaround none. 4. ocd mcko and mdo[3] are swapped in the aux1 mapping when using the ocd aux1 mapping of trace signals mdo[3] is located on pin pb05 and mcko is located on pb01. fix/workaround
815 32099a?avr32?06/09 at32uc3l swap pins pb01 and pb05 if using ocd aux1. 35.2.22 chip 1. power consumption in static mode is too high power consumption in static mode is too high when pa21 is high fix/workaround ensure pa21 is low. 2. shutdown mode is not functional do not enter shutdown mode. fix/workaround none. 3. static mode cannot be entered if the wdt is using osc32 if the wdt is using osc32 as clock source and the user tries to enter the static sleep mode, the deepstop sleep mode will be entered instead. fix/workaround none. 4. vddin current consumption increase above 1.8v when vddin increases above 1.8 v, current on vddin increases with up to 40 ua. fix/workaround none.
816 32099a?avr32?06/09 at32uc3l 36. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 36.1 rev. a ? 06/09 1. initial revision.
i 32099a?avr32?06/09 at32uc3l table of contents features ................ ................ .............. .............. .............. .............. ............. 1 1 description ............ .............. .............. .............. .............. .............. ............. 3 2 overview ............ ................ ................ .............. .............. .............. ............. 5 2.1 block diagram ...................................................................................................5 2.2 configuration summary .....................................................................................6 3 package and pinout ................. ................ ................. ................ ............... 7 3.1 package .............................................................................................................7 3.2 peripheral multiplexing on i/o lines ...................................................................7 3.3 signal descriptions ..........................................................................................12 3.4 i/o line considerations ...................................................................................15 3.5 power considerations .....................................................................................15 4 processor and architecture .... ................ ................. ................ ............. 21 4.1 features ..........................................................................................................21 4.2 avr32 architecture .........................................................................................21 4.3 the avr32uc cpu ........................................................................................22 4.4 programming model ........................................................................................26 4.5 exceptions and interrupts ................................................................................30 5 memories ............... .............. .............. .............. .............. .............. ........... 35 5.1 embedded memories ......................................................................................35 5.2 physical memory map .....................................................................................35 5.3 peripheral address map ..................................................................................36 5.4 cpu local bus mapping .................................................................................37 6 boot sequence ............. ................. ................ ................ .............. ........... 39 6.1 starting of clocks ............................................................................................39 6.2 fetching of initial instructions ..........................................................................39 6.3 rc32k clock output at startup .......................................................................39 7 flash controller (fla shcdw) ................ ................. ................ ............. 40 7.1 features ..........................................................................................................40 7.2 overview ..........................................................................................................40 7.3 product dependencies ....................................................................................40 7.4 functional description .....................................................................................41 7.5 flash commands ............................................................................................46
ii 32099a?avr32?06/09 at32uc3l 7.6 general-purpose fuse bits ..............................................................................48 7.7 security bit ......................................................................................................51 7.8 user interface ..................................................................................................52 7.9 fuse settings ...................................................................................................63 7.10 module configuration ......................................................................................65 8 hsb bus matrix (hmatrix) .. .............. .............. .............. .............. ........ 66 8.1 features ..........................................................................................................66 8.2 overview ..........................................................................................................66 8.3 product dependencies ....................................................................................66 8.4 functional description .....................................................................................66 8.5 user interface ..................................................................................................70 8.6 module configuration ......................................................................................78 9 secure access unit (sau) ....... ................ ................. ................ ............. 80 9.1 features ..........................................................................................................80 9.2 overview ..........................................................................................................80 9.3 block diagram .................................................................................................81 9.4 product dependencies ....................................................................................82 9.5 functional description .....................................................................................82 9.6 user interface ..................................................................................................86 9.7 module configuration ....................................................................................103 10 peripheral dma controller (pdca) .............. .............. .............. ........... 104 10.1 features ........................................................................................................104 10.2 overview ........................................................................................................104 10.3 block diagram ...............................................................................................105 10.4 product dependencies ..................................................................................105 10.5 functional description ...................................................................................106 10.6 performance monitors ...................................................................................108 10.7 user interface ................................................................................................110 10.8 module configuration ....................................................................................138 11 peripheral event system .... .............. .............. .............. .............. ......... 140 11.1 features ........................................................................................................140 11.2 overview ........................................................................................................140 11.3 peripheral event system block diagram .......................................................140 11.4 functional description ...................................................................................140 11.5 application example ......................................................................................142
iii 32099a?avr32?06/09 at32uc3l 12 interrupt controller (intc) ............. .............. .............. .............. ........... 143 12.1 features ........................................................................................................143 12.2 overview ........................................................................................................143 12.3 block diagram ...............................................................................................143 12.4 product dependencies ..................................................................................144 12.5 functional description ...................................................................................144 12.6 user interface ................................................................................................146 12.7 module configuration ....................................................................................150 13 power manager (pm) ........... .............. .............. .............. .............. ......... 153 13.1 features ........................................................................................................153 13.2 overview ........................................................................................................153 13.3 block diagram ...............................................................................................154 13.4 i/o lines description .....................................................................................154 13.5 product dependencies ..................................................................................154 13.6 functional description ...................................................................................155 13.7 user interface ................................................................................................164 13.8 module configuration ....................................................................................188 14 system control interface (s cif) ........... ................ ................. ............. 189 14.1 features ........................................................................................................189 14.2 overview ........................................................................................................189 14.3 i/o lines description .....................................................................................189 14.4 product dependencies ..................................................................................189 14.5 functional description ...................................................................................190 14.6 user interface ................................................................................................202 14.7 module configuration ....................................................................................249 15 asynchronous timer (ast) ....... ................. ................ .............. ........... 250 15.1 features ........................................................................................................250 15.2 overview ........................................................................................................250 15.3 block diagram ...............................................................................................251 15.4 product dependencies ..................................................................................251 15.5 functional description ...................................................................................252 15.6 user interface ................................................................................................258 15.7 module configuration ....................................................................................279 16 watchdog timer (wdt) ......... ................ ................ ................. ............. 280 16.1 features ........................................................................................................280
iv 32099a?avr32?06/09 at32uc3l 16.2 overview ........................................................................................................280 16.3 block diagram ...............................................................................................280 16.4 product dependencies ..................................................................................280 16.5 functional description ...................................................................................281 16.6 user interface ................................................................................................286 16.7 module configuration ....................................................................................292 17 external interrupt controller (eic) ...... .............. .............. ........... ......... 293 17.1 features ........................................................................................................293 17.2 overview ........................................................................................................293 17.3 block diagram ...............................................................................................294 17.4 i/o lines description .....................................................................................294 17.5 product dependencies ..................................................................................294 17.6 functional description ...................................................................................295 17.7 user interface ................................................................................................299 17.8 module configuration ....................................................................................315 18 frequency meter (freqm) ...... ................ ................. ................ ........... 316 18.1 features ........................................................................................................316 18.2 overview ........................................................................................................316 18.3 block diagram ...............................................................................................316 18.4 product dependencies ..................................................................................316 18.5 functional description ...................................................................................317 18.6 user interface ................................................................................................319 18.7 module configuration ....................................................................................330 19 general-purpose input /output controller (gpio) ................ ............. 331 19.1 features ........................................................................................................331 19.2 overview ........................................................................................................331 19.3 block diagram ...............................................................................................332 19.4 io lines description ......................................................................................332 19.5 product dependencies ..................................................................................333 19.6 functional description ...................................................................................334 19.7 user interface ................................................................................................340 19.8 module configuration ....................................................................................370 20 universal synchronous asynchronous receiver tran smitter (usart) 371 20.1 features ........................................................................................................371 20.2 overview ........................................................................................................371
v 32099a?avr32?06/09 at32uc3l 20.3 block diagram ...............................................................................................372 20.4 application block diagram .............................................................................373 20.5 i/o lines description ....................................................................................374 20.6 product dependencies ..................................................................................375 20.7 functional description ...................................................................................377 20.8 user interface ................................................................................................423 20.9 module configuration ....................................................................................447 21 serial peripheral interface (spi) ............ ................ ................. ............. 448 21.1 features ........................................................................................................448 21.2 overview ........................................................................................................448 21.3 block diagram ...............................................................................................449 21.4 application block diagram .............................................................................449 21.5 i/o lines description .....................................................................................450 21.6 product dependencies ..................................................................................450 21.7 functional description ...................................................................................450 21.8 user interface ................................................................................................461 21.9 module configuration ....................................................................................482 22 two-wire master interface (twim) ....... ................ ................. ............. 483 22.1 features ........................................................................................................483 22.2 overview ........................................................................................................483 22.3 list of abbreviations ......................................................................................484 22.4 block diagram ...............................................................................................485 22.5 application block diagram .............................................................................485 22.6 i/o lines description .....................................................................................485 22.7 product dependencies ..................................................................................486 22.8 functional description ...................................................................................487 22.9 user interface ................................................................................................499 22.10 module configuration ....................................................................................515 23 two-wire slave interface (twis) .......... ................ ................. ............. 516 23.1 features ........................................................................................................516 23.2 overview ........................................................................................................516 23.3 list of abbreviations ......................................................................................517 23.4 block diagram ...............................................................................................517 23.5 application block diagram .............................................................................518 23.6 i/o lines description .....................................................................................518
vi 32099a?avr32?06/09 at32uc3l 23.7 product dependencies ..................................................................................518 23.8 functional description ...................................................................................519 23.9 user interface ................................................................................................528 23.10 module configuration ....................................................................................545 24 basic pulse width modulat ion controller (pwma) .. .............. ........... 546 24.1 features ........................................................................................................546 24.2 overview ........................................................................................................546 24.3 block diagram ...............................................................................................547 24.4 i/o lines description .....................................................................................547 24.5 product dependencies ..................................................................................547 24.6 functional description ...................................................................................548 24.7 user interface ................................................................................................553 24.8 module configuration ....................................................................................567 25 timer/counter (tc) ........... .............. .............. .............. .............. ........... 568 25.1 features ........................................................................................................568 25.2 overview ........................................................................................................568 25.3 block diagram ...............................................................................................569 25.4 i/o lines description .....................................................................................569 25.5 product dependencies ..................................................................................569 25.6 functional description ...................................................................................570 25.7 user interface ................................................................................................585 25.8 module configuration ....................................................................................605 26 adc interface (adcifb) .... ............. .............. .............. .............. ........... 606 26.1 features ........................................................................................................606 26.2 overview ........................................................................................................606 26.3 block diagram ...............................................................................................607 26.4 i/o lines description .....................................................................................608 26.5 product dependencies ..................................................................................608 26.6 functional description ...................................................................................609 26.7 resisitve touch screen .................................................................................614 26.8 operating modes ...........................................................................................619 26.9 user interface ................................................................................................621 26.10 module configuration ....................................................................................639 27 analog comparator interface (acifb) ........ .............. .............. ........... 640 27.1 features ........................................................................................................640
vii 32099a?avr32?06/09 at32uc3l 27.2 overview ........................................................................................................640 27.3 block diagram ...............................................................................................641 27.4 i/o lines description .....................................................................................641 27.5 product dependencies ..................................................................................641 27.6 functional description ...................................................................................642 27.7 peripheral event triggers ..............................................................................646 27.8 ac test mode ................................................................................................647 27.9 user interface ................................................................................................648 27.10 module configuration ....................................................................................662 28 capacitive touch module (cat) ............. ................. ................ ........... 663 28.1 features ........................................................................................................663 28.2 overview ........................................................................................................663 28.3 block diagram ...............................................................................................664 28.4 i/o lines description .....................................................................................665 28.5 product dependencies ..................................................................................665 28.6 functional description ...................................................................................667 28.7 user interface ................................................................................................673 28.8 module configuration ....................................................................................704 29 glue logic controller (gloc) ............... ................ ................. ............. 705 29.1 features ........................................................................................................705 29.2 overview ........................................................................................................705 29.3 block diagram ...............................................................................................705 29.4 i/o lines description .....................................................................................706 29.5 product dependencies ..................................................................................706 29.6 functional description ...................................................................................706 29.7 user interface ................................................................................................708 29.8 module configuration ....................................................................................713 30 awire uart (aw) .............. .............. .............. .............. .............. ........... 714 30.1 features ........................................................................................................714 30.2 overview ........................................................................................................714 30.3 block diagram ...............................................................................................715 30.4 i/o lines description .....................................................................................715 30.5 product dependencies ..................................................................................715 30.6 functional description ...................................................................................716 30.7 user interface ................................................................................................719
viii 32099a?avr32?06/09 at32uc3l 30.8 module configuration ....................................................................................732 31 programming and debugging ... ................. ................ .............. ........... 733 31.1 overview ........................................................................................................733 31.2 service access bus .......................................................................................733 31.3 on-chip debug ..............................................................................................736 31.4 jtag and boundary-scan (jtag) ................................................................744 31.5 jtag instruction summary ...........................................................................752 31.6 awire debug interface (aw) .........................................................................769 32 electrical characteristics .. ............. .............. .............. .............. ........... 786 32.1 disclaimer ......................................................................................................786 32.2 absolute maximum ratings* .........................................................................786 32.3 supply characteristics ...................................................................................786 32.4 clock characteristics .....................................................................................787 32.5 power consumption ......................................................................................788 32.6 i/o pad characteristics ..................................................................................791 32.7 oscillator characteristics ...............................................................................793 32.8 flash characteristics .....................................................................................795 32.9 analog characteristics ...................................................................................796 32.10 timing characteristics ...................................................................................797 33 mechanical characteristics ..... ................ ................. ................ ........... 798 33.1 thermal considerations ................................................................................798 33.2 package drawings .........................................................................................799 33.3 soldering profile ............................................................................................802 34 ordering information .......... .............. .............. .............. .............. ......... 803 35 errata ........... ................ ................ ................. ................ .............. ........... 804 35.1 rev. c ............................................................................................................804 35.2 rev. b ............................................................................................................804 36 datasheet revision history ... ................ ................ ................. ............. 816 36.1 rev. a ? 06/09 ...............................................................................................816 table of contents.......... ................. ................ ................ ................. ........... i
32099a?avr32?06/09 ? 2009 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr32@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life.

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